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[/] [zet86/] [trunk/] [sim/] [testbench.v] - Diff between revs 2 and 14
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Rev 14 |
`timescale 10ns/100ps
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`timescale 10ns/100ps
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module testbench;
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module testbench;
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// Net declarations
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// Net declarations
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wire [15:0] rd_data;
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wire [15:0] rd_data;
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wire [15:0] wr_data, mem_data, io_data;
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wire [15:0] wr_data, mem_data, io_data;
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wire [19:0] addr;
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wire [19:0] addr;
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wire we;
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wire we;
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wire m_io;
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wire m_io;
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wire byte_m;
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wire byte_m;
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wire ack_i;
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reg clk, rst;
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reg clk, rst;
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reg [15:0] io_reg;
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reg [15:0] io_reg;
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reg [ 1:0] ack;
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// Module instantiations
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// Module instantiations
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memory mem0 (clk, addr, wr_data, mem_data, we & ~m_io, byte_m);
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memory mem0 (clk, addr, wr_data, mem_data, we & ~m_io, byte_m);
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cpu cpu0 (clk, rst, rd_data, wr_data, addr, we, m_io, byte_m,, 1'b1);
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cpu cpu0 (
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.clk_i (clk),
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.rst_i (rst),
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.dat_i (rd_data),
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.dat_o (wr_data),
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.adr_o (addr),
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.we_o (we),
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.mio_o (m_io),
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.byte_o (byte_m),
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.ack_i (ack_i)
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);
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// Assignments
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// Assignments
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assign io_data = (addr[15:0]==16'hb7) ? io_reg : 16'd0;
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assign io_data = (addr[15:0]==16'hb7) ? io_reg : 16'd0;
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assign rd_data = m_io ? io_data : mem_data;
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assign rd_data = m_io ? io_data : mem_data;
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assign ack_i = (ack==2'b10);
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// Behaviour
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// Behaviour
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// IO Stub
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// IO Stub
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always @(posedge clk)
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always @(posedge clk)
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if (addr==20'hb7 & ~we & m_io)
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if (addr==20'hb7 & we & m_io)
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io_reg <= byte_m ? { io_reg[15:8], wr_data[7:0] } : wr_data;
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io_reg <= byte_m ? { io_reg[15:8], wr_data[7:0] } : wr_data;
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always #1 clk = ~clk;
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always #1 clk = ~clk;
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always #2.13 ack = ack + 2'd1;
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initial
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initial
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begin
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begin
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clk <= 1'b1;
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clk <= 1'b1;
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rst <= 1'b0;
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rst <= 1'b0;
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ack <= 2'b0;
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#5 rst <= 1'b1;
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#5 rst <= 1'b1;
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#2 rst <= 1'b0;
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#2 rst <= 1'b0;
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end
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end
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endmodule
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endmodule
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