///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: cpuops.v
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// Filename: cpuops.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: This supports the instruction set reordering of operations
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// Purpose: This supports the instruction set reordering of operations
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// created by the second generation instruction set, as well as
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// created by the second generation instruction set, as well as
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// the new operations of POPC (population count) and BREV (bit reversal).
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// the new operations of POPC (population count) and BREV (bit reversal).
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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module cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
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module cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
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o_illegal, o_busy);
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o_illegal, o_busy);
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parameter IMPLEMENT_MPY = 1;
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parameter IMPLEMENT_MPY = 1;
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input i_clk, i_rst, i_ce;
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input i_clk, i_rst, i_ce;
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input [3:0] i_op;
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input [3:0] i_op;
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input [31:0] i_a, i_b;
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input [31:0] i_a, i_b;
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input i_valid;
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input i_valid;
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output reg [31:0] o_c;
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output reg [31:0] o_c;
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output wire [3:0] o_f;
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output wire [3:0] o_f;
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output reg o_valid;
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output reg o_valid;
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output wire o_illegal;
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output wire o_illegal;
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output wire o_busy;
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output wire o_busy;
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// Rotate-left pre-logic
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// Rotate-left pre-logic
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wire [63:0] w_rol_tmp;
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wire [63:0] w_rol_tmp;
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assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
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assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
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wire [31:0] w_rol_result;
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wire [31:0] w_rol_result;
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assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
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assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
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// Shift register pre-logic
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// Shift register pre-logic
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wire [32:0] w_lsr_result, w_asr_result;
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wire [32:0] w_lsr_result, w_asr_result;
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assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
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assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
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: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
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: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
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assign w_lsr_result = (|i_b[31:5])? 33'h00
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assign w_lsr_result = (|i_b[31:5])? 33'h00
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: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
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: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
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// Bit reversal pre-logic
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// Bit reversal pre-logic
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wire [31:0] w_brev_result;
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wire [31:0] w_brev_result;
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genvar k;
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genvar k;
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generate
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generate
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for(k=0; k<32; k=k+1)
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for(k=0; k<32; k=k+1)
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begin : bit_reversal_cpuop
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assign w_brev_result[k] = i_b[31-k];
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assign w_brev_result[k] = i_b[31-k];
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endgenerate
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end endgenerate
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// Popcount pre-logic
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// Popcount pre-logic
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wire [31:0] w_popc_result;
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wire [31:0] w_popc_result;
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assign w_popc_result[5:0]=
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assign w_popc_result[5:0]=
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({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]})
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({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]})
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+({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]})
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+({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]})
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+({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]})
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+({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]})
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+({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]})
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+({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]})
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+({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]})
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+({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]})
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+({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]})
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+({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]})
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+({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]})
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+({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]})
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+({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]});
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+({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]});
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assign w_popc_result[31:6] = 26'h00;
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assign w_popc_result[31:6] = 26'h00;
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// Prelogic for our flags registers
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// Prelogic for our flags registers
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wire z, n, v;
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wire z, n, v;
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reg c, pre_sign, set_ovfl;
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reg c, pre_sign, set_ovfl;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce) // 1 LUT
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if (i_ce) // 1 LUT
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set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
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set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
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||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
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||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
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||(i_op == 4'h6) // LSL
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||(i_op == 4'h6) // LSL
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||(i_op == 4'h5)); // LSR
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||(i_op == 4'h5)); // LSR
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// A 4-way multiplexer can be done in one 6-LUT.
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// A 4-way multiplexer can be done in one 6-LUT.
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// A 16-way multiplexer can therefore be done in 4x 6-LUT's with
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// A 16-way multiplexer can therefore be done in 4x 6-LUT's with
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// the Xilinx multiplexer fabric that follows.
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// the Xilinx multiplexer fabric that follows.
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// Given that we wish to apply this multiplexer approach to 33-bits,
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// Given that we wish to apply this multiplexer approach to 33-bits,
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// this will cost a minimum of 132 6-LUTs.
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// this will cost a minimum of 132 6-LUTs.
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generate
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generate
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if (IMPLEMENT_MPY == 0)
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if (IMPLEMENT_MPY == 0)
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begin
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begin
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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begin
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begin
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pre_sign <= (i_a[31]);
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pre_sign <= (i_a[31]);
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c <= 1'b0;
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c <= 1'b0;
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casez(i_op)
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casez(i_op)
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4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
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4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
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4'b0001: o_c <= i_a & i_b; // BTST/And
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4'b0001: o_c <= i_a & i_b; // BTST/And
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4'b0010:{c,o_c } <= i_a + i_b; // Add
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4'b0010:{c,o_c } <= i_a + i_b; // Add
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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// 4'h1010: The unimplemented MPYU,
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// 4'h1010: The unimplemented MPYU,
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// 4'h1011: and here for the unimplemented MPYS
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// 4'h1011: and here for the unimplemented MPYS
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4'b1100: o_c <= w_brev_result; // BREV
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4'b1100: o_c <= w_brev_result; // BREV
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4'b1101: o_c <= w_popc_result; // POPC
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4'b1101: o_c <= w_popc_result; // POPC
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4'b1110: o_c <= w_rol_result; // ROL
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4'b1110: o_c <= w_rol_result; // ROL
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default: o_c <= i_b; // MOV, LDI
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default: o_c <= i_b; // MOV, LDI
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endcase
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endcase
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end
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end
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assign o_busy = 1'b0;
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assign o_busy = 1'b0;
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reg r_illegal;
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reg r_illegal;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4));
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r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4));
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assign o_illegal = r_illegal;
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assign o_illegal = r_illegal;
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end else begin
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end else begin
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//
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//
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// Multiply pre-logic
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// Multiply pre-logic
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//
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//
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wire [16:0] w_mpy_a_input, w_mpy_b_input;
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wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
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wire [33:0] w_mpy_result;
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wire [33:0] w_mpy_result;
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reg [31:0] r_mpy_result;
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reg [31:0] r_mpy_result;
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assign w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] };
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assign w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] };
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assign w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] };
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assign w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] };
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assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
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assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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r_mpy_result = w_mpy_result[31:0];
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r_mpy_result = w_mpy_result[31:0];
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//
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//
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// The master ALU case statement
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// The master ALU case statement
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//
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//
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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begin
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begin
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pre_sign <= (i_a[31]);
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pre_sign <= (i_a[31]);
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c <= 1'b0;
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c <= 1'b0;
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casez(i_op)
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casez(i_op)
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4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
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4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
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4'b0001: o_c <= i_a & i_b; // BTST/And
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4'b0001: o_c <= i_a & i_b; // BTST/And
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4'b0010:{c,o_c } <= i_a + i_b; // Add
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4'b0010:{c,o_c } <= i_a + i_b; // Add
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0011: o_c <= i_a | i_b; // Or
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0100: o_c <= i_a ^ i_b; // Xor
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'b1010: o_c <= r_mpy_result; // MPYU
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4'b1010: o_c <= r_mpy_result; // MPYU
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4'b1011: o_c <= r_mpy_result; // MPYS
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4'b1011: o_c <= r_mpy_result; // MPYS
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4'b1100: o_c <= w_brev_result; // BREV
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4'b1100: o_c <= w_brev_result; // BREV
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4'b1101: o_c <= w_popc_result; // POPC
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4'b1101: o_c <= w_popc_result; // POPC
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4'b1110: o_c <= w_rol_result; // ROL
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4'b1110: o_c <= w_rol_result; // ROL
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default: o_c <= i_b; // MOV, LDI
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default: o_c <= i_b; // MOV, LDI
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endcase
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endcase
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end else if (r_busy)
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end else if (r_busy)
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o_c <= r_mpy_result;
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o_c <= r_mpy_result;
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reg r_busy;
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reg r_busy;
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initial r_busy = 1'b0;
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initial r_busy = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_busy <= (~i_rst)&&(i_ce)&&(i_valid)
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r_busy <= (~i_rst)&&(i_ce)&&(i_valid)
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&&(i_op[3:1] == 3'h5);
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&&(i_op[3:1] == 3'h5);
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assign o_busy = r_busy;
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assign o_busy = r_busy;
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assign o_illegal = 1'b0;
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assign o_illegal = 1'b0;
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end endgenerate
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end endgenerate
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assign z = (o_c == 32'h0000);
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assign z = (o_c == 32'h0000);
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assign n = (o_c[31]);
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assign n = (o_c[31]);
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assign v = (set_ovfl)&&(pre_sign != o_c[31]);
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assign v = (set_ovfl)&&(pre_sign != o_c[31]);
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assign o_f = { v, n, c, z };
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assign o_f = { v, n, c, z };
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initial o_valid = 1'b0;
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initial o_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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o_valid <= 1'b0;
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o_valid <= 1'b0;
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else
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else
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o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5)
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o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5)
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||(o_busy);
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||(o_busy);
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endmodule
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endmodule
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