///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: flashcache.v
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// Filename: flashcache.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: Since my Zip CPU has primary access to a flash, which requires
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// Purpose: Since my Zip CPU has primary access to a flash, which requires
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// nearly 24 clock cycles per read, this 'cache' module
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// nearly 24 clock cycles per read, this 'cache' module
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// is offered to minimize the effect. The CPU may now request
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// is offered to minimize the effect. The CPU may now request
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// some amount of flash to be copied into this on-chip RAM,
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// some amount of flash to be copied into this on-chip RAM,
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// and then access it with nearly zero latency.
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// and then access it with nearly zero latency.
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//
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//
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// Status: This file is no longer being used as an active file within
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// the ZipCPU project. It's an older file from an idea that
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// never really caught traction.
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//
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// Interface:
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// Interface:
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// FlashCache sits on the Wishbone bus as both a slave and a master.
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// FlashCache sits on the Wishbone bus as both a slave and a master.
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// Slave requests for memory will get mapped to a local RAM, from which
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// Slave requests for memory will get mapped to a local RAM, from which
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// reads and writes may take place.
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// reads and writes may take place.
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//
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//
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// This cache supports a single control register: the base wishbone address
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// This cache supports a single control register: the base wishbone address
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// of the device to copy memory from. The bottom bit if this address must
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// of the device to copy memory from. The bottom bit if this address must
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// be zero (or it will be silently rendered as zero). When read, this
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// be zero (or it will be silently rendered as zero). When read, this
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// bottom bit will indicate 1) that the controller is still loading memory
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// bottom bit will indicate 1) that the controller is still loading memory
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// into the cache, or 0) that the cache is ready to be used.
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// into the cache, or 0) that the cache is ready to be used.
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//
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//
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// Writing to this register will initiate a memory copy from the (new)
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// Writing to this register will initiate a memory copy from the (new)
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// address. Once done, the loading bit will be cleared and an interrupt
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// address. Once done, the loading bit will be cleared and an interrupt
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// generated.
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// generated.
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//
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//
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// Where this memory is placed on the wishbone bus is entirely up to the
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// Where this memory is placed on the wishbone bus is entirely up to the
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// wishbone bus control logic. Setting the memory base to an
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// wishbone bus control logic. Setting the memory base to an
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// address controlled by this flashcache will produce unusable
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// address controlled by this flashcache will produce unusable
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// results, and may well hang the bus.
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// results, and may well hang the bus.
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// Reads from the memory before complete will return immediately with
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// Reads from the memory before complete will return immediately with
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// the value if read address is less than the current copy
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// the value if read address is less than the current copy
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// address, or else they will stall until the read address is
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// address, or else they will stall until the read address is
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// less than the copy address.
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// less than the copy address.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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module flashcache(i_clk,
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module flashcache(i_clk,
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// Wishbone contrl interface
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// Wishbone contrl interface
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i_wb_cyc, i_wb_stb,i_wb_ctrl_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb,i_wb_ctrl_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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// Wishbone copy interface
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// Wishbone copy interface
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o_cp_cyc, o_cp_stb, o_cp_we, o_cp_addr, o_cp_data,
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o_cp_cyc, o_cp_stb, o_cp_we, o_cp_addr, o_cp_data,
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i_cp_ack, i_cp_stall, i_cp_data,
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i_cp_ack, i_cp_stall, i_cp_data,
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o_int);
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o_int);
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parameter LGCACHELEN=10; // 4 kB
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parameter LGCACHELEN=10; // 4 kB
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input i_clk;
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input i_clk;
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// Control interface, CPU interface to cache
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// Control interface, CPU interface to cache
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input i_wb_cyc, i_wb_stb,i_wb_ctrl_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb,i_wb_ctrl_stb, i_wb_we;
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input [(LGCACHELEN-1):0] i_wb_addr;
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input [(LGCACHELEN-1):0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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// Interface to peripheral bus, including flash
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// Interface to peripheral bus, including flash
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output reg o_cp_cyc, o_cp_stb;
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output reg o_cp_cyc, o_cp_stb;
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output wire o_cp_we;
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output wire o_cp_we;
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output reg [31:0] o_cp_addr;
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output reg [31:0] o_cp_addr;
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output wire [31:0] o_cp_data;
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output wire [31:0] o_cp_data;
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input i_cp_ack, i_cp_stall;
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input i_cp_ack, i_cp_stall;
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input [31:0] i_cp_data;
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input [31:0] i_cp_data;
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// And an interrupt to send once we complete
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// And an interrupt to send once we complete
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output reg o_int;
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output reg o_int;
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reg loading;
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reg loading;
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reg [31:0] cache_base;
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reg [31:0] cache_base;
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reg [31:0] cache [0:((1<<LGCACHELEN)-1)];
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reg [31:0] cache [0:((1<<LGCACHELEN)-1)];
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// Decouple writing the cache base from the highly delayed bus lines
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// Decouple writing the cache base from the highly delayed bus lines
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reg wr_cache_base_flag;
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reg wr_cache_base_flag;
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reg [31:0] wr_cache_base_value;
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reg [31:0] wr_cache_base_value;
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always @(posedge i_clk)
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always @(posedge i_clk)
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wr_cache_base_flag <= ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we));
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wr_cache_base_flag <= ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we));
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always @(posedge i_clk)
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always @(posedge i_clk)
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wr_cache_base_value<= { i_wb_data[31:1], 1'b0 };
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wr_cache_base_value<= { i_wb_data[31:1], 1'b0 };
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initial cache_base = 32'hffffffff;
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initial cache_base = 32'hffffffff;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (wr_cache_base_flag)
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if (wr_cache_base_flag)
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cache_base <= wr_cache_base_value;
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cache_base <= wr_cache_base_value;
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reg new_cache_base;
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reg new_cache_base;
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initial new_cache_base = 1'b0;
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initial new_cache_base = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((wr_cache_base_flag)&&(cache_base != wr_cache_base_value))
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if ((wr_cache_base_flag)&&(cache_base != wr_cache_base_value))
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new_cache_base <= 1'b1;
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new_cache_base <= 1'b1;
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else
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else
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new_cache_base <= 1'b0;
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new_cache_base <= 1'b0;
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reg [(LGCACHELEN-1):0] rdaddr;
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reg [(LGCACHELEN-1):0] rdaddr;
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initial loading = 1'b0;
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initial loading = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (new_cache_base)
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if (new_cache_base)
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begin
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begin
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loading <= 1'b1;
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loading <= 1'b1;
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o_cp_cyc <= 1'b0;
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o_cp_cyc <= 1'b0;
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end else if ((~o_cp_cyc)&&(loading))
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end else if ((~o_cp_cyc)&&(loading))
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begin
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begin
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o_cp_cyc <= 1'b1;
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o_cp_cyc <= 1'b1;
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end else if (o_cp_cyc)
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end else if (o_cp_cyc)
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begin
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begin
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// Handle the ack/read line
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// Handle the ack/read line
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if (i_cp_ack)
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if (i_cp_ack)
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begin
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begin
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if (&rdaddr)
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if (&rdaddr)
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begin
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begin
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o_cp_cyc <= 1'b0;
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o_cp_cyc <= 1'b0;
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loading <= 1'b0;
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loading <= 1'b0;
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end
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end
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end
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end
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~o_cp_cyc)
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if (~o_cp_cyc)
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o_cp_addr <= cache_base;
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o_cp_addr <= cache_base;
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else if ((o_cp_cyc)&&(o_cp_stb)&&(~i_cp_stall))
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else if ((o_cp_cyc)&&(o_cp_stb)&&(~i_cp_stall))
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o_cp_addr <= o_cp_addr + 1;;
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o_cp_addr <= o_cp_addr + 1;;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((~o_cp_cyc)&&(loading))
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if ((~o_cp_cyc)&&(loading))
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o_cp_stb <= 1'b1;
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o_cp_stb <= 1'b1;
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else if ((o_cp_cyc)&&(o_cp_stb)&&(~i_cp_stall))
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else if ((o_cp_cyc)&&(o_cp_stb)&&(~i_cp_stall))
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begin
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begin
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// We've made our last request
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// We've made our last request
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if (o_cp_addr >= cache_base + { {(32-LGCACHELEN-1){1'b0}}, 1'b1, {(LGCACHELEN){1'b0}}})
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if (o_cp_addr >= cache_base + { {(32-LGCACHELEN-1){1'b0}}, 1'b1, {(LGCACHELEN){1'b0}}})
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o_cp_stb <= 1'b0;
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o_cp_stb <= 1'b0;
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~loading)
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if (~loading)
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rdaddr <= 0;
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rdaddr <= 0;
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else if ((o_cp_cyc)&&(i_cp_ack))
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else if ((o_cp_cyc)&&(i_cp_ack))
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rdaddr <= rdaddr + 1;
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rdaddr <= rdaddr + 1;
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initial o_int = 1'b0;
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initial o_int = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_cp_cyc)&&(i_cp_ack)&&(&rdaddr))
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if ((o_cp_cyc)&&(i_cp_ack)&&(&rdaddr))
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o_int <= 1'b1;
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o_int <= 1'b1;
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else
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else
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o_int <= 1'b0;
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o_int <= 1'b0;
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assign o_cp_we = 1'b0;
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assign o_cp_we = 1'b0;
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assign o_cp_data = 32'h00;
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assign o_cp_data = 32'h00;
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//
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//
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// Writes to our cache ... always delayed by a clock.
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// Writes to our cache ... always delayed by a clock.
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// Clock 0 : Write request
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// Clock 0 : Write request
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// Clock 1 : Write takes place
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// Clock 1 : Write takes place
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// Clock 2 : Available for reading
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// Clock 2 : Available for reading
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//
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//
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reg we;
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reg we;
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reg [(LGCACHELEN-1):0] waddr;
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reg [(LGCACHELEN-1):0] waddr;
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reg [31:0] wval;
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reg [31:0] wval;
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always @(posedge i_clk)
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always @(posedge i_clk)
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we <= (loading)?((o_cp_cyc)&&(i_cp_ack)):(i_wb_cyc)&&(i_wb_stb)&&(i_wb_we);
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we <= (loading)?((o_cp_cyc)&&(i_cp_ack)):(i_wb_cyc)&&(i_wb_stb)&&(i_wb_we);
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always @(posedge i_clk)
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always @(posedge i_clk)
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waddr <= (loading)?rdaddr:i_wb_addr;
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waddr <= (loading)?rdaddr:i_wb_addr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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wval <= (loading)?i_cp_data:i_wb_data;
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wval <= (loading)?i_cp_data:i_wb_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (we)
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if (we)
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cache[waddr] <= wval;
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cache[waddr] <= wval;
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reg [31:0] cache_data;
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reg [31:0] cache_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_wb_cyc)&&(i_wb_stb))
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if ((i_wb_cyc)&&(i_wb_stb))
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cache_data <= cache[i_wb_addr];
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cache_data <= cache[i_wb_addr];
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= (i_wb_cyc)&&(
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o_wb_ack <= (i_wb_cyc)&&(
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((i_wb_stb)&&(~loading))
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((i_wb_stb)&&(~loading))
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||(i_wb_ctrl_stb));
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||(i_wb_ctrl_stb));
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reg ctrl;
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reg ctrl;
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always @(posedge i_clk)
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always @(posedge i_clk)
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ctrl <= i_wb_ctrl_stb;
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ctrl <= i_wb_ctrl_stb;
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assign o_wb_data = (ctrl)?({cache_base[31:1],loading}):cache_data;
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assign o_wb_data = (ctrl)?({cache_base[31:1],loading}):cache_data;
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assign o_wb_stall = (loading)&&(~o_wb_ack);
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assign o_wb_stall = (loading)&&(~o_wb_ack);
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endmodule
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endmodule
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