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;
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;
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; Filename: divu.S
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; Filename: divu.S
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;
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;
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; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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;
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;
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; Purpose: Zip assembly file for running doing an unsigned divide.
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; Purpose: Zip assembly file for running doing an unsigned divide.
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; This routine is also called by the signed divide.
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; This routine is also called by the signed divide.
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;
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;
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; Creator: Dan Gisselquist, Ph.D.
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; Creator: Dan Gisselquist, Ph.D.
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; Gisselquist Tecnology, LLC
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; Gisselquist Technology, LLC
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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;
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; Copyright (C) 2015, Gisselquist Technology, LLC
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; Copyright (C) 2015, Gisselquist Technology, LLC
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;
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;
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; This program is free software (firmware): you can redistribute it and/or
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; This program is free software (firmware): you can redistribute it and/or
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; modify it under the terms of the GNU General Public License as published
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; modify it under the terms of the GNU General Public License as published
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; by the Free Software Foundation, either version 3 of the License, or (at
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; by the Free Software Foundation, either version 3 of the License, or (at
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; your option) any later version.
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; your option) any later version.
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;
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;
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; This program is distributed in the hope that it will be useful, but WITHOUT
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; This program is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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; for more details.
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; for more details.
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;
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;
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; License: GPL, v3, as defined and found on www.gnu.org,
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; License: GPL, v3, as defined and found on www.gnu.org,
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; http://www.gnu.org/licenses/gpl.html
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; http://www.gnu.org/licenses/gpl.html
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;
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;
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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;
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;
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;
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;
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;
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divu: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1
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lib_divu: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1
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TST -1,R1
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TST -1,R1
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; BNZ divu_valid_divide
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; BNZ divu_valid_divide
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CLR.Z R0 ; Should be a divide by zero error / trap
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CLR.Z R0 ; Should be a divide by zero error / trap
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RETN.Z
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JMP.Z R2
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divu_valid_divide:
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divu_valid_divide:
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SUB 1,SP
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SUB 2,SP
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STO R2,(SP)
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STO R3,1(SP)
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STO R3,1(SP)
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;
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;
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LDI 1,R2 ; Here's where we record the bit we are working on
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LDI 1,R2 ; Here's where we record the bit we are working on
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CLR R3 ; Here's where we build our result
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CLR R3 ; Here's where we build our result
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; Our original loop rejoin point, before a touch of unrolling
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; Our original loop rejoin point, before a touch of unrolling
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CMP R1,R0
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CMP R1,R0
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BRC divu_prep_next_bit
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BRC divu_prep_next_bit
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TST -1,R1
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TST -1,R1
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BLT divu_top_bit_set
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BLT divu_top_bit_set
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divu_rotate_up_r1:
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divu_rotate_up_r1:
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LSL 1,R2
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LSL 1,R2
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LSL 1,R1
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LSL 1,R1
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/*
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/*
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CMP R1,R0
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CMP R1,R0
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BRC divu_prep_next_bit
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BRC divu_prep_next_bit
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TST -1,R1
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TST -1,R1
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BGT divu_rotate_up_r1
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BGT divu_rotate_up_r1
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*/
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*/
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BLT divu_top_bit_set
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BLT divu_top_bit_set
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CMP R1,R0
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CMP R1,R0
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BRC divu_prep_next_bit
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BRC divu_prep_next_bit
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;
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;
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LSL 1,R2
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LSL 1,R2
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LSL 1,R1
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LSL 1,R1
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BLT divu_top_bit_set
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BLT divu_top_bit_set
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CMP R1,R0
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CMP R1,R0
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BRC divu_prep_next_bit
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BRC divu_prep_next_bit
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;
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;
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LSL 1,R2
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LSL 1,R2
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LSL 1,R1
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LSL 1,R1
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BLT divu_top_bit_set
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BLT divu_top_bit_set
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CMP R1,R0
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CMP R1,R0
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BRC divu_prep_next_bit
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BRC divu_prep_next_bit
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;
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;
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LSL 1,R2
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LSL 1,R2
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LSL 1,R1
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LSL 1,R1
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BLT divu_top_bit_set
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BLT divu_top_bit_set
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CMP R1,R0
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CMP R1,R0
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BRC divu_prep_next_bit
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BRC divu_prep_next_bit
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BRA divu_rotate_up_r1
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BRA divu_rotate_up_r1
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divu_top_bit_set:
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divu_top_bit_set:
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CMP R1,R0
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CMP R1,R0
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BRC divu_prep_next_bit
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BRC divu_prep_next_bit
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SUB R1,R0
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SUB R1,R0
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OR R2,R3
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OR R2,R3
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divu_prep_next_bit:
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divu_prep_next_bit:
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LSR 1,R1
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LSR 1,R1
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LSR 1,R2
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LSR 1,R2
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BZ divu_record_result
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BZ divu_record_result
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;
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;
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divu_next_loop:
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divu_next_loop:
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CMP R1,R0 ;
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CMP R1,R0 ;
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SUB.GE R1,R0 ; We also switch to signed arithmetic, since
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SUB.GE R1,R0 ; We also switch to signed arithmetic, since
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OR.GE R2,R3 ; after the first bit, we are signed
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OR.GE R2,R3 ; after the first bit, we are signed
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LSR 1,R1
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LSR 1,R1
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LSR 1,R2
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LSR 1,R2
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BZ divu_record_result
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BZ divu_record_result
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;
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;
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CMP R1,R0
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CMP R1,R0
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SUB.GE R1,R0
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SUB.GE R1,R0
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OR.GE R2,R3
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OR.GE R2,R3
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LSR 1,R1
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LSR 1,R1
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LSR 1,R2
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LSR 1,R2
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BZ divu_record_result
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BZ divu_record_result
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;
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;
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CMP R1,R0
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CMP R1,R0
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SUB.GE R1,R0
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SUB.GE R1,R0
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OR.GE R2,R3
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OR.GE R2,R3
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LSR 1,R1
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LSR 1,R1
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LSR 1,R2
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LSR 1,R2
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BZ divu_record_result
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BZ divu_record_result
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;
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;
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CMP R1,R0
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CMP R1,R0
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SUB.GE R1,R0
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SUB.GE R1,R0
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OR.GE R2,R3
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OR.GE R2,R3
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LSR 1,R1
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LSR 1,R1
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LSR 1,R2
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LSR 1,R2
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BNZ divu_next_loop
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BNZ divu_next_loop
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divu_record_result:
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divu_record_result:
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MOV R0,R1
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MOV R0,R1
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MOV R3,R0
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MOV R3,R0
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LOD (SP),R2
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LOD 1(SP),R3
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LOD 1(SP),R3
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LOD 2(SP),R2
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ADD 2,SP
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ADD 1,SP
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JMP R2
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JMP R2
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