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;
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;
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; Filename: sys.i
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; Filename: sys.i
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;
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;
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; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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;
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;
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; Purpose: This is the beginnings of a system wide header file for the
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; Purpose: This is the beginnings of a system wide header file for the
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; Zip System. It describes and declares the peripherals
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; Zip System. It describes and declares the peripherals
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; that will the be used and referenced by the assembly files.
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; that will the be used and referenced by the assembly files.
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;
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;
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; Status: As of August, 2015, I have no confidence that the preprocessor
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; Status: As of August, 2015, I have no confidence that the preprocessor
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; can properly include this file. It certainly cannot handle
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; can properly include this file. It certainly cannot handle
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; macros (yet).
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; macros (yet).
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;
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;
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; Creator: Dan Gisselquist, Ph.D.
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; Creator: Dan Gisselquist, Ph.D.
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; Gisselquist Tecnology, LLC
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; Gisselquist Technology, LLC
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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;
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; Copyright (C) 2015, Gisselquist Technology, LLC
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; Copyright (C) 2015, Gisselquist Technology, LLC
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;
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;
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; This program is free software (firmware): you can redistribute it and/or
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; This program is free software (firmware): you can redistribute it and/or
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; modify it under the terms of the GNU General Public License as published
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; modify it under the terms of the GNU General Public License as published
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; by the Free Software Foundation, either version 3 of the License, or (at
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; by the Free Software Foundation, either version 3 of the License, or (at
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; your option) any later version.
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; your option) any later version.
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;
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;
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; This program is distributed in the hope that it will be useful, but WITHOUT
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; This program is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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; for more details.
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; for more details.
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;
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;
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; License: GPL, v3, as defined and found on www.gnu.org,
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; License: GPL, v3, as defined and found on www.gnu.org,
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; http://www.gnu.org/licenses/gpl.html
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; http://www.gnu.org/licenses/gpl.html
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;
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;
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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;
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sys.bus equ 0xc0000000
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sys.bus equ 0xc0000000
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sys.breaken equ 0x080
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sys.breaken equ 0x080
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sys.step equ 0x040
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sys.step equ 0x040
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sys.gie equ 0x020
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sys.gie equ 0x020
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sys.sleep equ 0x010
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sys.sleep equ 0x010
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sys.ccv equ 0x008
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sys.ccv equ 0x008
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sys.ccn equ 0x004
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sys.ccn equ 0x004
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sys.ccc equ 0x002
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sys.ccc equ 0x002
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sys.ccz equ 0x001
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sys.ccz equ 0x001
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sys.bus.pic equ 0x000
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sys.bus.pic equ 0x000
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sys.bus.wdt equ 0x001
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sys.bus.wdt equ 0x001
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sys.bus.cache equ 0x002
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sys.bus.cache equ 0x002
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sys.bus.ctrpic equ 0x003
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sys.bus.ctrpic equ 0x003
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sys.bus.tma equ 0x004
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sys.bus.tma equ 0x004
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sys.bus.tmb equ 0x005
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sys.bus.tmb equ 0x005
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sys.bus.tmc equ 0x006
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sys.bus.tmc equ 0x006
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; Define the location(s) of our peripherals,
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; Define the location(s) of our peripherals,
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#define sys.base 0xc0000000
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#define sys.base 0xc0000000
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#define sys.cache.base 0xc0100000
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#define sys.cache.base 0xc0100000
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#struct sys
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#struct sys
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pic
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pic
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wdt
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wdt
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cache
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cache
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ctrpic
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ctrpic
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tma
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tma
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tmb
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tmb
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tmc
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tmc
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jiffies
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jiffies
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mtask
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mtask
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mstl
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mstl
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mpstl
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mpstl
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mastl
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mastl
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utask
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utask
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ustl
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ustl
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upstl
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upstl
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uastl
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uastl
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#endstruct
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#endstruct
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; and their associated interrupt vectors ...
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; and their associated interrupt vectors ...
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#define CACHEINT 0x01
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#define CACHEINT 0x01
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#define JIFFYINT 0x02 ;
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#define JIFFYINT 0x02 ;
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#define TMCINT 0x04 ;
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#define TMCINT 0x04 ;
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#define TMBINT 0x08 ;
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#define TMBINT 0x08 ;
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#define TMAINT 0x10 ;
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#define TMAINT 0x10 ;
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#define CTRPICINT 0x20 ; The aux interrupt controller
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#define CTRPICINT 0x20 ; The aux interrupt controller
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; Masks to send to enable those same vectors
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; Masks to send to enable those same vectors
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#define CACHEINTEN 0x80010000
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#define CACHEINTEN 0x80010000
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#define JIFFYINTEN 0x80020000
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#define JIFFYINTEN 0x80020000
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#define TMCINTEN 0x80040000
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#define TMCINTEN 0x80040000
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#define TMBINTEN 0x80080000
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#define TMBINTEN 0x80080000
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#define TMAINTEN 0x80100000
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#define TMAINTEN 0x80100000
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#define CTRPICEN 0x80200000
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#define CTRPICEN 0x80200000
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; And similar masks to disable them
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; And similar masks to disable them
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#define CACHEINTDIS 0x00010000
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#define CACHEINTDIS 0x00010000
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#define JIFFYINTDIS 0x00020000
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#define JIFFYINTDIS 0x00020000
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#define TMCINTDIS 0x00040000
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#define TMCINTDIS 0x00040000
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#define TMBINTDIS 0x00080000
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#define TMBINTDIS 0x00080000
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#define TMAINTDIS 0x00100000
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#define TMAINTDIS 0x00100000
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#define CTRPICDIS 0x00200000
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#define CTRPICDIS 0x00200000
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; Define our condition code bits
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; Define our condition code bits
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#define CCZ 0x001
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#define CCZ 0x001
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#define CCC 0x002
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#define CCC 0x002
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#define CCN 0x004
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#define CCN 0x004
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#define CCV 0x008
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#define CCV 0x008
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#define CCSLEEP 0x010
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#define CCSLEEP 0x010
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#define CCGIE 0x020
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#define CCGIE 0x020
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#define CCSTEP 0x040
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#define CCSTEP 0x040
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#define CCUBRK 0x080
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#define CCUBRK 0x080
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; Now, some macros
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; Now, some macros
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#define PUSH(RG,SP) SUB 1,SP \
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#define PUSH(RG,SP) SUB 1,SP \
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STO RG,1(SP)
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STO RG,1(SP)
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#define POP(RG,SP) LOD 1(SP),RG \
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#define POP(RG,SP) LOD 1(SP),RG \
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ADD 1,SP
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ADD 1,SP
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#define FJSR(LBL,RG) MOV __here__+2(PC),RG \
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#define FJSR(LBL,RG) MOV __here__+2(PC),RG \
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BRA LBL
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BRA LBL
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#define FRET(RG) MOV RG,PC
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#define FRET(RG) MOV RG,PC
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#define JSR(LBL,RG) SUB 1,SP \
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#define JSR(LBL,RG) SUB 1,SP \
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MOV __here__+3(PC),RG \
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MOV __here__+3(PC),RG \
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STO RG,1(SP) \
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STO RG,1(SP) \
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BRA LBL \
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BRA LBL \
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ADD 1,SP
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ADD 1,SP
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#define RET LOD 1(SP),PC
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#define RET LOD 1(SP),PC
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#define SAVE_USER_CONTEXT(DR,AR) \
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#define SAVE_USER_CONTEXT(DA,DB,DC,DD,AR) \
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MOV -15(uSP),AR \
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MOV -15(uSP),AR \
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MOV uPC,DR \
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MOV uR0,DA \
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STO DR,15(AR) \
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MOV uR1,DB \
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MOV uCC,DR \
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MOV uR2,DC \
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STO DR,14(AR) \
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MOV uR3,DD \
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MOV uR12,DR \
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STO DA,(AR) \
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STO DR,13(AR) \
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STO DB,1(AR) \
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MOV uR11,DR \
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STO DC,2(AR) \
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STO DR,12(AR) \
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STO DD,3(AR) \
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MOV uR10,DR \
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MOV uR4,DA \
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STO DR,11(AR) \
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MOV uR5,DB \
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MOV uR9,DR \
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MOV uR6,DC \
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STO DR,10(AR) \
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MOV uR7,DD \
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MOV uR8,DR \
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STO DA,4(AR) \
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STO DR,9(AR) \
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STO DB,5(AR) \
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MOV uR7,DR \
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STO DC,6(AR) \
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STO DR,8(AR) \
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STO DD,7(AR) \
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MOV uR6,DR \
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MOV uR8,DA \
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STO DR,7(AR) \
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MOV uR9,DB \
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MOV uR5,DR \
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MOV uR10,DC \
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STO DR,6(AR) \
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MOV uR11,DD \
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MOV uR4,DR \
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STO DA,8(AR) \
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STO DR,5(AR) \
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STO DB,9(AR) \
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MOV uR3,DR \
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STO DC,10(AR) \
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STO DR,4(AR) \
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STO DD,11(AR) \
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MOV uR2,DR \
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MOV uR12,DA \
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STO DR,3(AR) \
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MOV uCC,DC \
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MOV uR1,DR \
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MOV uPC,DD \
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STO DR,2(AR) \
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STO DA,12(AR) \
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MOV uR0,DR \
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STO DC,13(AR) \
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STO DR,1(AR)
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STO DD,14(AR)
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#define RESTORE_USER_CONTEXT(DR,AR) \
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#define RESTORE_USER_CONTEXT(DA,DB,DC,DD,AR) \
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LOD 1(AR),DR \
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LOD (AR),DA \
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MOV DR,uR0 \
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LOD 1(AR),DB \
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LOD 2(AR),DR \
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LOD 2(AR),DC \
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MOV DR,uR1 \
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LOD 3(AR),DD \
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LOD 3(AR),DR \
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MOV DA,uR0 \
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MOV DR,uR2 \
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MOV DB,uR1 \
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LOD 4(AR),DR \
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MOV DC,uR2 \
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MOV DR,uR3 \
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MOV DD,uR3 \
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LOD 5(AR),DR \
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LOD 4(AR),DA \
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MOV DR,uR4 \
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LOD 5(AR),DB \
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LOD 6(AR),DR \
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LOD 6(AR),DC \
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MOV DR,uR5 \
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LOD 7(AR),DD \
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LOD 7(AR),DR \
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MOV DA,uR4 \
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MOV DR,uR6 \
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MOV DB,uR5 \
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LOD 8(AR),DR \
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MOV DC,uR6 \
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MOV DR,uR7 \
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MOV DD,uR7 \
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LOD 9(AR),DR \
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LOD 8(AR),DA \
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MOV DR,uR8 \
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LOD 9(AR),DB \
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LOD 10(AR),DR \
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LOD 10(AR),DC \
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MOV DR,uR9 \
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LOD 11(AR),DD \
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LOD 11(AR),DR \
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MOV DA,uR8 \
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MOV DR,uR10 \
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MOV DB,uR9 \
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LOD 12(AR),DR \
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MOV DC,uR10 \
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MOV DR,uR11 \
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MOV DD,uR11 \
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LOD 13(AR),DR \
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LOD 12(AR),DA \
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MOV DR,uR12 \
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LOD 13(AR),DB \
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LOD 14(AR),DR \
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LOD 14(AR),DC \
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MOV DR,uCC \
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MOV DA,uR12 \
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LOD 15(AR),DR \
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MOV DB,uCC \
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MOV DR,uPC
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MOV DC,uPC \
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MOV 15(AR),uSP
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#define READ_USER_TRAP(RG) \
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#define READ_USER_TRAP(RG) \
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MOV uCC,RG \
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MOV uCC,RG \
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AND -256,RG
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AND -256,RG
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