`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Dept. Architecture and Computing Technology. University of Seville
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// Company: Dept. Architecture and Computing Technology. University of Seville
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// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
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// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
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//
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//
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// Create Date: 19:13:39 4-Apr-2012
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// Create Date: 19:13:39 4-Apr-2012
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// Design Name: ZX Spectrum
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// Design Name: ZX Spectrum
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// Module Name: tld_spartan3_sp48k
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// Module Name: tld_spartan3_sp48k
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 1.00 - File Created
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// Revision 1.00 - File Created
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// Additional Comments: GPL License policies apply to the contents of this file.
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// Additional Comments: GPL License policies apply to the contents of this file.
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module tld_spartan3_sp48k (
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module tld_spartan3_sp48k (
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input clk50,
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input clk50,
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input reset,
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input reset,
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output r,
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output r,
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output g,
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output g,
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output b,
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output b,
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output i,
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output i,
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output csync,
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output csync,
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// ULA I/O
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// ULA I/O
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input ear,
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input ear,
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output audio_out,
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output audio_out,
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output [7:0] kbd_rows,
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output [7:0] kbd_rows,
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input [4:0] kbd_columns,
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input [4:0] kbd_columns,
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// diagnostics
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// diagnostics
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output [7:0] leds,
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output [7:0] leds,
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// SRAM memory
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// SRAM memory
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output [17:0] sa,
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output [17:0] sa,
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inout [7:0] sd1,
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inout [7:0] sd1,
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output sramce1,
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output sramce1,
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output sramub1,
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output sramub1,
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output sramlb1,
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output sramlb1,
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output sramoe,
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output sramoe,
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output sramwe
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output sramwe
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);
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);
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// CPU signals
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// CPU signals
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wire [15:0] a;
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wire [15:0] a;
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wire [7:0] cpudout;
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wire [7:0] cpudout;
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wire [7:0] cpudin;
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wire [7:0] cpudin;
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wire clkcpu;
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wire clkcpu;
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wire mreq_n;
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wire mreq_n;
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wire iorq_n;
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wire iorq_n;
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wire wr_n;
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wire wr_n;
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wire rd_n;
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wire rd_n;
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wire rfsh_n;
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wire rfsh_n;
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wire int_n;
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wire int_n;
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// VRAM signals
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// VRAM signals
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wire [13:0] va;
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wire [13:0] va;
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wire [7:0] vramdin;
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wire [7:0] vramdin;
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wire [7:0] vramdout;
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wire [7:0] vramdout;
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wire vramoe;
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wire vramoe;
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wire vramcs;
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wire vramcs;
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wire vramwe;
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wire vramwe;
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// I/O
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// I/O
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wire mic;
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wire mic;
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wire spk;
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wire spk;
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assign audio_out = spk;
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assign audio_out = spk;
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// ULA data bus
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// ULA data bus
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wire [7:0] uladout;
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wire [7:0] uladout;
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wire [7:0] uladin;
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wire [7:0] uladin;
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// SRAM data bus
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// SRAM data bus
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wire [7:0] sramdout;
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wire [7:0] sramdout;
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wire [7:0] sramdin;
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wire [7:0] sramdin;
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// ROM data bus
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// ROM data bus
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wire [7:0] romdout;
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wire [7:0] romdout;
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wire sram_cs = a[15] & !mreq_n;
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wire sram_cs = a[15] & !mreq_n;
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wire ula_cs = !a[0] & !iorq_n;
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wire ula_cs = !a[0] & !iorq_n;
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wire vram_cs = !a[15] & a[14] & !mreq_n;
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wire vram_cs = !a[15] & a[14] & !mreq_n;
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wire port255_cs = !iorq_n && a[7:0]==8'hFF && !rd_n;
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wire port255_cs = !iorq_n && a[7:0]==8'hFF && !rd_n;
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wire rom_cs = !a[15] & !a[14] & !mreq_n & !rd_n;
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wire rom_cs = !a[15] & !a[14] & !mreq_n & !rd_n;
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/////////////////////////////////////
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/////////////////////////////////////
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// Master clock (14MHz) generation
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// Master clock (14MHz) generation
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/////////////////////////////////////
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/////////////////////////////////////
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wire clk28mhz;
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wire clk28mhz;
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master_clock clock28mhz (
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master_clock clock28mhz (
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.CLKIN_IN(clk50),
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.CLKIN_IN(clk50),
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.CLKFX_OUT(clk28mhz),
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.CLKFX_OUT(clk28mhz),
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.CLKIN_IBUFG_OUT(),
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.CLKIN_IBUFG_OUT(),
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.CLK0_OUT()
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.CLK0_OUT()
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);
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);
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reg clk14 = 0;
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reg clk14 = 0;
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always @(posedge clk28mhz) begin
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always @(posedge clk28mhz) begin
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clk14 = !clk14;
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clk14 = !clk14;
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end
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end
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wire clkula = clk14;
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wire clkula = clk14;
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wire clkmem = clk28mhz;
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wire clkmem = clk28mhz;
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/////////////////////////////////////
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/////////////////////////////////////
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// ROM
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// ROM
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/////////////////////////////////////
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/////////////////////////////////////
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rom the_rom (
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rom the_rom (
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.clka(clkmem),
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.clka(clkmem),
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.ena(rom_cs),
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.ena(rom_cs),
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.addra(a[13:0]),
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.addra(a[13:0]),
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.douta(romdout)
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.douta(romdout)
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);
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);
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// /////////////////////////////////////
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// // VRAM (first 16K of RAM)
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// /////////////////////////////////////
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// vram lower_ram (
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// .clka(clkmem),
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// .addra(va),
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// .dina(vramdin),
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// .douta(vramdout),
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// .ena(vramcs),
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// .wea(vramwe)
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// );
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// /////////////////////////////////////
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// // SRAM (top 32K of RAM). External SRAM chip
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// /////////////////////////////////////
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// ram32k upper_ram (
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// .a(a[14:0]),
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// .cs_n(!sram_cs),
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// .oe_n(rd_n),
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// .we_n(wr_n),
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// .din(sramdin),
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// .dout(sramdout),
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// .sa(sa),
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// .sd(sd1),
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// .sramce(sramce1),
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// .sramub(sramub1),
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// .sramlb(sramlb1),
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// .sramoe(sramoe),
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// .sramwe(sramwe)
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// );
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/////////////////////////////////////
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/////////////////////////////////////
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// VRAM and upper RAM banks
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// VRAM and upper RAM banks
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/////////////////////////////////////
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/////////////////////////////////////
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ram_controller vram_and_upper_ram (
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ram_controller vram_and_upper_ram (
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.clk(clkmem),
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.clk(clkmem),
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// Bank 1 (VRAM)
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// Bank 1 (VRAM)
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.a1({2'b00,va}),
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.a1({2'b00,va}),
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.cs1_n(!vramcs),
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.cs1_n(!vramcs),
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.oe1_n(!vramoe),
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.oe1_n(!vramoe),
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.we1_n(!vramwe),
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.we1_n(!vramwe),
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.din1(vramdin),
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.din1(vramdin),
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.dout1(vramdout),
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.dout1(vramdout),
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// Bank 2 (upper RAM)
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// Bank 2 (upper RAM)
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.a2({1'b0,a[14:0]}),
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.a2({1'b0,a[14:0]}),
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.cs2_n(!sram_cs),
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.cs2_n(!sram_cs),
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.oe2_n(rd_n),
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.oe2_n(rd_n),
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.we2_n(wr_n),
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.we2_n(wr_n),
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.din2(sramdin),
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.din2(sramdin),
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.dout2(sramdout),
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.dout2(sramdout),
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// Outputs to actual SRAM on board
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// Outputs to actual SRAM on board
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.sa(sa),
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.sa(sa),
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.sd(sd1),
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.sd(sd1),
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.sramce(sramce1),
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.sramce(sramce1),
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.sramub(sramub1),
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.sramub(sramub1),
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.sramlb(sramlb1),
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.sramlb(sramlb1),
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.sramoe(sramoe),
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.sramoe(sramoe),
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.sramwe(sramwe)
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.sramwe(sramwe)
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);
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);
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/////////////////////////////////////
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/////////////////////////////////////
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// The ULA
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// The ULA
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/////////////////////////////////////
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/////////////////////////////////////
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ula the_ula (
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ula the_ula (
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.clk14(clkula),
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.clk14(clkula),
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.a(a),
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.a(a),
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.din(uladin),
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.din(uladin),
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.dout(uladout),
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.dout(uladout),
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.mreq_n(mreq_n),
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.mreq_n(mreq_n),
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.iorq_n(iorq_n),
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.iorq_n(iorq_n),
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.rd_n(rd_n),
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.rd_n(rd_n),
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.wr_n(wr_n),
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.wr_n(wr_n),
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.rfsh_n(rfsh_n),
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.rfsh_n(rfsh_n),
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.clkcpu(clkcpu),
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.clkcpu(clkcpu),
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.msk_int_n(int_n),
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.msk_int_n(int_n),
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.va(va),
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.va(va),
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.vramdout(vramdout),
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.vramdout(vramdout),
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.vramdin(vramdin),
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.vramdin(vramdin),
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.vramoe(vramoe),
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.vramoe(vramoe),
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.vramcs(vramcs),
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.vramcs(vramcs),
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.vramwe(vramwe),
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.vramwe(vramwe),
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.ear(ear),
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.ear(ear),
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.mic(mic),
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.mic(mic),
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.spk(spk),
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.spk(spk),
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.kbrows(kbd_rows),
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.kbrows(kbd_rows),
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.kbcolumns(kbd_columns),
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.kbcolumns(kbd_columns),
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.r(r),
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.r(r),
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.g(g),
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.g(g),
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.b(b),
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.b(b),
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.i(i),
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.i(i),
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.csync(csync)
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.csync(csync)
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);
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);
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/////////////////////////////////////
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/////////////////////////////////////
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// The CPU Z80A
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// The CPU Z80A
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/////////////////////////////////////
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/////////////////////////////////////
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tv80n cpu (
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tv80n cpu (
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// Outputs
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// Outputs
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.m1_n(),
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.m1_n(),
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.mreq_n(mreq_n),
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.mreq_n(mreq_n),
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.iorq_n(iorq_n),
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.iorq_n(iorq_n),
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.rd_n(rd_n),
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.rd_n(rd_n),
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.wr_n(wr_n),
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.wr_n(wr_n),
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.rfsh_n(rfsh_n),
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.rfsh_n(rfsh_n),
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.halt_n(),
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.halt_n(),
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.busak_n(),
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.busak_n(),
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.A(a),
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.A(a),
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.dout(cpudout),
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.dout(cpudout),
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// Inputs
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// Inputs
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.reset_n(!reset),
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.reset_n(!reset),
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.clk(clkcpu),
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.clk(clkcpu),
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.wait_n(1'b1),
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.wait_n(1'b1),
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.int_n(int_n),
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.int_n(int_n),
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.nmi_n(1'b1),
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.nmi_n(1'b1),
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.busrq_n(1'b1),
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.busrq_n(1'b1),
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.di(cpudin)
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.di(cpudin)
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);
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);
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// T80s cpu (
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// // Outputs
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// .M1_n(),
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// .MREQ_n(mreq_n),
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// .IORQ_n(iorq_n),
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// .RD_n(rd_n),
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// .WR_n(wr_n),
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// .RFSH_n(rfsh_n),
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// .HALT_n(),
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// .BUSAK_n(),
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// .A(a),
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// .DO(cpudout),
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// // Inputs
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// .RESET_n(!reset),
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// .CLK_n(clkcpu),
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// .WAIT_n(1'b1),
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// .INT_n(int_n),
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// .NMI_n(1'b1),
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// .BUSRQ_n(1'b1),
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// .DI(cpudin)
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// );
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/////////////////////////////////////
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/////////////////////////////////////
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// Connecting all togther
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// Connecting all togther
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/////////////////////////////////////
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/////////////////////////////////////
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assign sramdin = cpudout;
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assign sramdin = cpudout;
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assign uladin = cpudout;
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assign uladin = cpudout;
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assign cpudin = (rom_cs)? romdout :
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assign cpudin = (rom_cs)? romdout :
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(ula_cs | vram_cs | port255_cs)? uladout :
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(ula_cs | vram_cs | port255_cs)? uladout :
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(sram_cs)? sramdout :
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(sram_cs)? sramdout :
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8'hFF;
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8'hFF;
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/////////////////////////////////////
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/////////////////////////////////////
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// Diagnostics
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// Diagnostics
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/////////////////////////////////////
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/////////////////////////////////////
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reg [7:0] rLeds = 8'b10000000;
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reg [7:0] rLeds = 8'b10000000;
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assign leds = rLeds;
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assign leds = rLeds;
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reg [1:0] cntleds = 2'b00;
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reg [1:0] cntleds = 2'b00;
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always @(posedge int_n) begin
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always @(posedge int_n) begin
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cntleds <= cntleds + 1;
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cntleds <= cntleds + 1;
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if (cntleds == 2'b11) begin
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if (cntleds == 2'b11) begin
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rLeds <= { rLeds[0], rLeds[7:1] };
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rLeds <= { rLeds[0], rLeds[7:1] };
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end
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end
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end
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end
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endmodule
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endmodule
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