`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Dept. Architecture and Computing Technology. University of Seville
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// Company: Dept. Architecture and Computing Technology. University of Seville
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// Engineer: Miguel Angel Rodriguez Jodar
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// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
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//
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//
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// Create Date: 19:13:39 4-Apr-2012
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// Create Date: 19:13:39 4-Apr-2012
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// Design Name: ULA
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// Design Name: ZX Spectrum
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// Module Name: ula_reference_design
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// Module Name: ula
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 1.00 - File Created
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// Additional Comments:
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// Additional Comments: GPL License policies apply to the contents of this file.
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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`define cyclestart(a,b) ((a)==(b))
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`define cyclestart(a,b) ((a)==(b))
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`define cycleend(a,b) ((a)==(b+1))
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`define cycleend(a,b) ((a)==(b+1))
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module ula(
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module ula(
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input clk14, // 14MHz master clock
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input clk14, // 14MHz master clock
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// CPU interfacing
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// CPU interfacing
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input [15:0] a, // Address bus from CPU (not all lines are used)
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input [15:0] a, // Address bus from CPU (not all lines are used)
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input [7:0] din, // Input data bus from CPU
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input [7:0] din, // Input data bus from CPU
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output [7:0] dout, // Output data bus to CPU
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output [7:0] dout, // Output data bus to CPU
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input mreq_n, // MREQ from CPU
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input mreq_n, // MREQ from CPU
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input iorq_n, // IORQ from CPU
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input iorq_n, // IORQ from CPU
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input rd_n, // RD from CPU
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input rd_n, // RD from CPU
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input wr_n, // WR from CPU
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input wr_n, // WR from CPU
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input rfsh_n, // RFSH from CPU
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input rfsh_n, // RFSH from CPU
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output clkcpu, // CLK to CPU
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output clkcpu, // CLK to CPU
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output msk_int_n, // Vertical retrace interrupt, to CPU
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output msk_int_n, // Vertical retrace interrupt, to CPU
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// VRAM interfacing
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// VRAM interfacing
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output [13:0] va, // Address bus to VRAM (16K)
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output [13:0] va, // Address bus to VRAM (16K)
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input [7:0] vramdout,// Data from VRAM to ULA/CPU
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input [7:0] vramdout,// Data from VRAM to ULA/CPU
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output [7:0] vramdin,// Data from CPU to VRAM
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output [7:0] vramdin,// Data from CPU to VRAM
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output vramoe, //
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output vramoe, //
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output vramcs, // Control signals for VRAM
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output vramcs, // Control signals for VRAM
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output vramwe, //
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output vramwe, //
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// ULA I/O
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// ULA I/O
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input ear, //
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input ear, //
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output mic, // I/O ports
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output mic, // I/O ports
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output spk, //
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output spk, //
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output [7:0] kbrows, // Keyboard rows
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output [7:0] kbrows, // Keyboard rows
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input [4:0] kbcolumns, // Keyboard columns
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input [4:0] kbcolumns, // Keyboard columns
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// Video output
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// Video output
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output r, //
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output r, //
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output g, // RGB TTL signal
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output g, // RGB TTL signal
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output b, // with separate bright
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output b, // with separate bright
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output i, // and composite sync
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output i, // and composite sync
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output csync //
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output csync //
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);
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);
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reg [2:0] BorderColor = 3'b100;
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reg [2:0] BorderColor = 3'b100;
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// Pixel clock
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// Pixel clock
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reg clk7 = 0;
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reg clk7 = 0;
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always @(posedge clk14)
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always @(posedge clk14)
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clk7 <= !clk7;
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clk7 <= !clk7;
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// Horizontal counter
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// Horizontal counter
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reg [8:0] hc = 0;
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reg [8:0] hc = 0;
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always @(posedge clk7) begin
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always @(posedge clk7) begin
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if (hc==447)
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if (hc==447)
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hc <= 0;
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hc <= 0;
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else
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else
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hc <= hc + 1;
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hc <= hc + 1;
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end
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end
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// Vertical counter
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// Vertical counter
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reg [8:0] vc = 0;
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reg [8:0] vc = 0;
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always @(posedge clk7) begin
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always @(posedge clk7) begin
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if (hc==447) begin
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if (hc==447) begin
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if (vc == 311)
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if (vc == 311)
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vc <= 0;
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vc <= 0;
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else
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else
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vc <= vc + 1;
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vc <= vc + 1;
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end
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end
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end
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end
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// HBlank generation
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// HBlank generation
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reg HBlank_n = 1;
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reg HBlank_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (`cyclestart(hc,320))
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if (`cyclestart(hc,320))
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HBlank_n <= 0;
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HBlank_n <= 0;
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else if (`cycleend(hc,415))
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else if (`cycleend(hc,415))
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HBlank_n <= 1;
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HBlank_n <= 1;
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end
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end
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// HSync generation (6C ULA version)
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// HSync generation (6C ULA version)
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reg HSync_n = 1;
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reg HSync_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (`cyclestart(hc,344))
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if (`cyclestart(hc,344))
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HSync_n <= 0;
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HSync_n <= 0;
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else if (`cycleend(hc,375))
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else if (`cycleend(hc,375))
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HSync_n <= 1;
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HSync_n <= 1;
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end
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end
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// VBlank generation
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// VBlank generation
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reg VBlank_n = 1;
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reg VBlank_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (`cyclestart(vc,248))
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if (`cyclestart(vc,248))
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VBlank_n <= 0;
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VBlank_n <= 0;
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else if (`cycleend(vc,255))
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else if (`cycleend(vc,255))
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VBlank_n <= 1;
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VBlank_n <= 1;
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end
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end
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// VSync generation (PAL)
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// VSync generation (PAL)
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reg VSync_n = 1;
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reg VSync_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (`cyclestart(vc,248))
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if (`cyclestart(vc,248))
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VSync_n <= 0;
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VSync_n <= 0;
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else if (`cycleend(vc,251))
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else if (`cycleend(vc,251))
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VSync_n <= 1;
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VSync_n <= 1;
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end
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end
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// INT generation
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// INT generation
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reg INT_n = 1;
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reg INT_n = 1;
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assign msk_int_n = INT_n;
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assign msk_int_n = INT_n;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (`cyclestart(vc,248) && `cyclestart(hc,0))
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if (`cyclestart(vc,248) && `cyclestart(hc,0))
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INT_n <= 0;
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INT_n <= 0;
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else if (`cyclestart(vc,248) && `cycleend(hc,31))
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else if (`cyclestart(vc,248) && `cycleend(hc,31))
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INT_n <= 1;
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INT_n <= 1;
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end
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end
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// Border control signal (=0 when we're not displaying paper/ink pixels)
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// Border control signal (=0 when we're not displaying paper/ink pixels)
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reg Border_n = 1;
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reg Border_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if ( (vc[7] & vc[6]) | vc[8] | hc[8])
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if ( (vc[7] & vc[6]) | vc[8] | hc[8])
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Border_n <= 0;
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Border_n <= 0;
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else
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else
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Border_n <= 1;
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Border_n <= 1;
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end
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end
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// VidEN generation (delaying Border 8 clocks)
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// VidEN generation (delaying Border 8 clocks)
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reg VidEN_n = 1;
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reg VidEN_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (hc[3])
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if (hc[3])
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VidEN_n <= !Border_n;
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VidEN_n <= !Border_n;
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end
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end
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// DataLatch generation (posedge to capture data from memory)
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// DataLatch generation (posedge to capture data from memory)
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reg DataLatch_n = 1;
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reg DataLatch_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (hc[0] & !hc[1] & Border_n & hc[3])
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if (hc[0] & !hc[1] & Border_n & hc[3])
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DataLatch_n <= 0;
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DataLatch_n <= 0;
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else
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else
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DataLatch_n <= 1;
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DataLatch_n <= 1;
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end
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end
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// AttrLatch generation (posedge to capture data from memory)
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// AttrLatch generation (posedge to capture data from memory)
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reg AttrLatch_n = 1;
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reg AttrLatch_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (hc[0] & hc[1] & Border_n & hc[3])
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if (hc[0] & hc[1] & Border_n & hc[3])
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AttrLatch_n <= 0;
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AttrLatch_n <= 0;
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else
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else
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AttrLatch_n <= 1;
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AttrLatch_n <= 1;
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end
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end
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// SLoad generation (negedge to load shift register)
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// SLoad generation (negedge to load shift register)
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reg SLoad = 0;
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reg SLoad = 0;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (!hc[0] & !hc[1] & hc[2] & !VidEN_n)
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if (!hc[0] & !hc[1] & hc[2] & !VidEN_n)
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SLoad <= 1;
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SLoad <= 1;
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else
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else
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SLoad <= 0;
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SLoad <= 0;
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end
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end
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// AOLatch generation (negedge to update attr output latch)
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// AOLatch generation (negedge to update attr output latch)
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reg AOLatch_n = 1;
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reg AOLatch_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (hc[0] & !hc[1] & hc[2])
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if (hc[0] & !hc[1] & hc[2])
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AOLatch_n <= 0;
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AOLatch_n <= 0;
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else
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else
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AOLatch_n <= 1;
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AOLatch_n <= 1;
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end
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end
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// First buffer for bitmap
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// First buffer for bitmap
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reg [7:0] BitmapReg = 0;
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reg [7:0] BitmapReg = 0;
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always @(negedge DataLatch_n) begin
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always @(negedge DataLatch_n) begin
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BitmapReg <= vramdout;
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BitmapReg <= vramdout;
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end
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end
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// Shift register (second bitmap register)
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// Shift register (second bitmap register)
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reg [7:0] SRegister = 0;
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reg [7:0] SRegister = 0;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (SLoad)
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if (SLoad)
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SRegister <= BitmapReg;
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SRegister <= BitmapReg;
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else
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else
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SRegister <= {SRegister[6:0],1'b0};
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SRegister <= {SRegister[6:0],1'b0};
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end
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end
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// First buffer for attribute
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// First buffer for attribute
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reg [7:0] AttrReg = 0;
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reg [7:0] AttrReg = 0;
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always @(negedge AttrLatch_n) begin
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always @(negedge AttrLatch_n) begin
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AttrReg <= vramdout;
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AttrReg <= vramdout;
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end
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end
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// Second buffer for attribute
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// Second buffer for attribute
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reg [7:0] AttrOut = 0;
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reg [7:0] AttrOut = 0;
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always @(negedge AOLatch_n) begin
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always @(negedge AOLatch_n) begin
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if (!VidEN_n)
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if (!VidEN_n)
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AttrOut <= AttrReg;
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AttrOut <= AttrReg;
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else
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else
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AttrOut <= {2'b00,BorderColor,BorderColor};
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AttrOut <= {2'b00,BorderColor,BorderColor};
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end
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end
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// Flash counter and pixel generation
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// Flash counter and pixel generation
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reg [4:0] FlashCnt = 0;
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reg [4:0] FlashCnt = 0;
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always @(negedge VSync_n) begin
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always @(negedge VSync_n) begin
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FlashCnt <= FlashCnt + 1;
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FlashCnt <= FlashCnt + 1;
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end
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end
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wire Pixel = SRegister[7] ^ (AttrOut[7] & FlashCnt[4]);
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wire Pixel = SRegister[7] ^ (AttrOut[7] & FlashCnt[4]);
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// RGB generation
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// RGB generation
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reg rI,rG,rR,rB;
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reg rI,rG,rR,rB;
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assign r = rR;
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assign r = rR;
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assign g = rG;
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assign g = rG;
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assign b = rB;
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assign b = rB;
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assign i = rI;
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assign i = rI;
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always @(*) begin
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always @(*) begin
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if (HBlank_n && VBlank_n)
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if (HBlank_n && VBlank_n)
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{rI,rG,rR,rB} = (Pixel)? {AttrOut[6],AttrOut[2:0]} : {AttrOut[6],AttrOut[5:3]};
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{rI,rG,rR,rB} = (Pixel)? {AttrOut[6],AttrOut[2:0]} : {AttrOut[6],AttrOut[5:3]};
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else
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else
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{rI,rG,rR,rB} = 4'b0000;
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{rI,rG,rR,rB} = 4'b0000;
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end
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end
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//CSync generation
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//CSync generation
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assign csync = HSync_n & VSync_n;
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assign csync = HSync_n & VSync_n;
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// VRAM address and control line generation
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// VRAM address and control line generation
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reg [13:0] rVA = 0;
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reg [13:0] rVA = 0;
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reg rVCS = 0;
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reg rVCS = 0;
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reg rVOE = 0;
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reg rVOE = 0;
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reg rVWE = 0;
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reg rVWE = 0;
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assign va = rVA;
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assign va = rVA;
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assign vramcs = rVCS;
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assign vramcs = rVCS;
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assign vramoe = rVOE;
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assign vramoe = rVOE;
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assign vramwe = rVWE;
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assign vramwe = rVWE;
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// Latches to hold delayed versions of V and H counters
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// Latches to hold delayed versions of V and H counters
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reg [8:0] v = 0;
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reg [8:0] v = 0;
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reg [8:0] c = 0;
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reg [8:0] c = 0;
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// Address and control line multiplexor ULA/CPU
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// Address and control line multiplexor ULA/CPU
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (Border_n && (hc[3:0]==4'b0111 || hc[3:0]==4'b1011)) begin // cycles 7 and 11: load V and C from VC and HC
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if (Border_n && (hc[3:0]==4'b0111 || hc[3:0]==4'b1011)) begin // cycles 7 and 11: load V and C from VC and HC
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c <= hc;
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c <= hc;
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v <= vc;
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v <= vc;
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end
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end
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end
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end
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// Address and control line multiplexor ULA/CPU
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// Address and control line multiplexor ULA/CPU
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always @(*) begin
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always @(*) begin
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if (Border_n && (hc[3:0]==4'b1000 || hc[3:0]==4'b1001 || hc[3:0]==4'b1100 || hc[3:0]==4'b1101)) begin // cycles 8 and 12: present display address to VRAM
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if (Border_n && (hc[3:0]==4'b1000 || hc[3:0]==4'b1001 || hc[3:0]==4'b1100 || hc[3:0]==4'b1101)) begin // cycles 8 and 12: present display address to VRAM
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rVA = {1'b0,v[7:6],v[2:0],v[5:3],c[7:3]}; // (cycles 9 and 13 load display byte)
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rVA = {1'b0,v[7:6],v[2:0],v[5:3],c[7:3]}; // (cycles 9 and 13 load display byte)
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rVCS = 1;
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rVCS = 1;
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rVOE = 1;
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rVOE = !hc[0];
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rVWE = 0;
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rVWE = 0;
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end
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end
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else if (Border_n && (hc[3:0]==4'b1010 || hc[3:0]==4'b1011 || hc[3:0]==4'b1110 || hc[3:0]==4'b1111)) begin // cycles 10 and 14: present attribute address to VRAM
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else if (Border_n && (hc[3:0]==4'b1010 || hc[3:0]==4'b1011 || hc[3:0]==4'b1110 || hc[3:0]==4'b1111)) begin // cycles 10 and 14: present attribute address to VRAM
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rVA = {4'b0110,v[7:3],c[7:3]}; // (cycles 11 and 15 load attr byte)
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rVA = {4'b0110,v[7:3],c[7:3]}; // (cycles 11 and 15 load attr byte)
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rVCS = 1;
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rVCS = 1;
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rVOE = 1;
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rVOE = !hc[0];
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rVWE = 0;
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end
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else if (Border_n && hc[3:0]==4'b0000) begin
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rVA = a[13:0];
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rVCS = 0;
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rVOE = 0;
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rVWE = 0;
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rVWE = 0;
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end
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end
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else begin // when VRAM is not in use by ULA, give it to CPU
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else begin // when VRAM is not in use by ULA, give it to CPU
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rVA = a[13:0];
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rVA = a[13:0];
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rVCS = !a[15] & a[14] & !mreq_n;
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rVCS = !a[15] & a[14] & !mreq_n;
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rVOE = !rd_n;
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rVOE = !rd_n;
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rVWE = !wr_n;
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rVWE = !wr_n;
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end
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end
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end
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end
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// CPU contention
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// CPU contention
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reg CPUClk = 0;
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reg CPUClk = 0;
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assign clkcpu = CPUClk;
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assign clkcpu = CPUClk;
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reg ioreqtw3 = 0;
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reg ioreqtw3 = 0;
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reg mreqt23 = 0;
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reg mreqt23 = 0;
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wire ioreq_n = a[0] | iorq_n;
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wire ioreq_n = a[0] | iorq_n;
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wire Nor1 = (~(a[14] | ~ioreq_n)) |
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wire Nor1 = (~(a[14] | ~ioreq_n)) |
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(~(~a[15] | ~ioreq_n)) |
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(~(~a[15] | ~ioreq_n)) |
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(~(hc[2] | hc[3])) |
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(~(hc[2] | hc[3])) |
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(~Border_n | ~ioreqtw3 | ~CPUClk | ~mreqt23);
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(~Border_n | ~ioreqtw3 | ~CPUClk | ~mreqt23);
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wire Nor2 = (~(hc[2] | hc[3])) |
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wire Nor2 = (~(hc[2] | hc[3])) |
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~Border_n |
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~Border_n |
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~CPUClk |
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~CPUClk |
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ioreq_n |
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ioreq_n |
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~ioreqtw3;
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~ioreqtw3;
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wire CLKContention = ~Nor1 | ~Nor2;
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wire CLKContention = ~Nor1 | ~Nor2;
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always @(posedge clk7) begin // change clk7 by clk14 for 7MHz CPU clock operation
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always @(posedge clk7) begin // change clk7 by clk14 for 7MHz CPU clock operation
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if (CPUClk && !CLKContention) // if there's no contention, the clock can go low
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if (CPUClk && !CLKContention) // if there's no contention, the clock can go low
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CPUClk <= 0;
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CPUClk <= 0;
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else
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else
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CPUClk <= 1;
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CPUClk <= 1;
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end
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end
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always @(posedge CPUClk) begin
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always @(posedge CPUClk) begin
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ioreqtw3 <= ioreq_n;
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ioreqtw3 <= ioreq_n;
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mreqt23 <= mreq_n;
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mreqt23 <= mreq_n;
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end
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end
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// ULA-CPU interface
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// ULA-CPU interface
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assign dout = (!a[15] & a[14] & !mreq_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
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assign dout = (!a[15] & a[14] & !mreq_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
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(!iorq_n & !a[0])? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
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(!iorq_n & !a[0])? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
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(Border_n)? vramdout : // to emulate
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(Border_n)? AttrReg : // to emulate
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8'hFF; // port FF
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8'hFF; // port FF
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assign vramdin = din; // The CPU doesn't need to share the memory input data bus with the ULA
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assign vramdin = din; // The CPU doesn't need to share the memory input data bus with the ULA
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assign kbrows = {a[11]? 1'bz : 0, // high impedance or 0, as if diodes were been placed in between
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assign kbrows = {a[11]? 1'bz : 1'b0, // high impedance or 0, as if diodes were been placed in between
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a[10]? 1'bz : 0, // if the keyboard matrix is to be implemented within the FPGA, then
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a[10]? 1'bz : 1'b0, // if the keyboard matrix is to be implemented within the FPGA, then
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a[9]? 1'bz : 0, // there's no need to do this.
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a[9]? 1'bz : 1'b0, // there's no need to do this.
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a[12]? 1'bz : 0,
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a[12]? 1'bz : 1'b0,
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a[13]? 1'bz : 0,
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a[13]? 1'bz : 1'b0,
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a[8]? 1'bz : 0,
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a[8]? 1'bz : 1'b0,
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a[14]? 1'bz : 0,
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a[14]? 1'bz : 1'b0,
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a[15]? 1'bz : 0 };
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a[15]? 1'bz : 1'b0 };
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// assign kbrows = {a[8]? 1'bz : 1'b0, // high impedance or 0, as if diodes were been placed in between
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// a[9]? 1'bz : 1'b0, // if the keyboard matrix is to be implemented within the FPGA, then
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// a[10]? 1'bz : 1'b0, // there's no need to do this.
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// a[11]? 1'bz : 1'b0,
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// a[12]? 1'bz : 1'b0,
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// a[13]? 1'bz : 1'b0,
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// a[14]? 1'bz : 1'b0,
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// a[15]? 1'bz : 1'b0 };
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reg rMic = 0;
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reg rMic = 0;
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reg rSpk = 0;
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reg rSpk = 0;
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assign mic = rMic;
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assign mic = rMic;
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assign spk = rSpk;
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assign spk = rSpk;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (!iorq_n & !a[0] & !wr_n)
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if (!iorq_n & !a[0] & !wr_n)
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{rSpk,rMic,BorderColor} <= din[5:0];
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{rSpk,rMic,BorderColor} <= din[5:0];
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end
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end
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endmodule
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endmodule
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