| Line 27... |
Line 27... |
use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use WORK.common.all;
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use WORK.common.all;
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use WORK.xsasdram.all;
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use WORK.xsasdram.all;
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use WORK.sdram.all;
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use WORK.sdram.all;
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use WORK.vga_pckg.all;
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use WORK.vga_pckg.all;
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use WORK.blitter_pckg.all;
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entity gpuChip is
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entity gpuChip is
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generic(
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generic(
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FREQ : natural := 50_000; -- frequency of operation in KHz
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FREQ : natural := 50_000; -- frequency of operation in KHz
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| Line 39... |
Line 40... |
CLK_DIV : real := 1.0; -- SDRAM Clock div
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CLK_DIV : real := 1.0; -- SDRAM Clock div
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NROWS : natural := 4096; -- number of rows in the SDRAM
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NROWS : natural := 4096; -- number of rows in the SDRAM
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NCOLS : natural := 256; -- number of columns in each SDRAM row
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NCOLS : natural := 256; -- number of columns in each SDRAM row
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SADDR_WIDTH : natural := 12;
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SADDR_WIDTH : natural := 12;
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DATA_WIDTH : natural := 16; -- SDRAM databus width
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DATA_WIDTH : natural := 16; -- SDRAM databus width
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ADDR_WIDTH : natural := 22; -- host-side address width
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ADDR_WIDTH : natural := 23; -- host-side address width
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VGA_CLK_DIV : natural := 2; -- pixel clock = FREQ / CLK_DIV
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VGA_CLK_DIV : natural := 4; -- pixel clock = FREQ / CLK_DIV
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PIXEL_WIDTH : natural := 8; -- width of a pixel in memory
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PIXEL_WIDTH : natural := 8; -- width of a pixel in memory
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NUM_RGB_BITS : natural := 2; -- #bits in each R,G,B component of a pixel
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NUM_RGB_BITS : natural := 2; -- #bits in each R,G,B component of a pixel
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PIXELS_PER_LINE : natural := 640; -- width of image in pixels
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PIXELS_PER_LINE : natural := 320; -- width of image in pixels
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LINES_PER_FRAME : natural := 480; -- height of image in scanlines
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LINES_PER_FRAME : natural := 240; -- height of image in scanlines
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FIT_TO_SCREEN : boolean := true; -- adapt video timing to fit image width x
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FIT_TO_SCREEN : boolean := true; -- adapt video timing to fit image width x
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PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000000000000000"
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PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000111111111111"
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);
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);
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port(
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port(
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pin_clkin : in std_logic; -- main clock input from external clock source
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pin_clkin : in std_logic; -- main clock input from external clock source
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pin_ce_n : out std_logic; -- Flash RAM chip-enable
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pin_ce_n : out std_logic; -- Flash RAM chip-enable
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| Line 84... |
Line 85... |
constant YES: std_logic := '1';
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constant YES: std_logic := '1';
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constant NO: std_logic := '0';
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constant NO: std_logic := '0';
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constant HI: std_logic := '1';
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constant HI: std_logic := '1';
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constant LO: std_logic := '0';
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constant LO: std_logic := '0';
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type gpuState is (
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INIT, -- init
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INIT_BKG,
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DRAW_BKG,
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BLIT_REST,
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INIT_SPRITE,
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DRAW_SPRITE,
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UPDATE
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);
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signal state_r, state_x : gpuState; -- state register and next state
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--registers
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signal plane0_dest_r, plane0_dest_x : std_logic_vector (ADDR_WIDTH - 1 downto 0); -- sprite dest register
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signal plane0_ypos_r, plane0_ypos_x : std_logic_vector (11 downto 0);
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signal delay_r, delay_x : std_logic_vector (19 downto 0); --20 bit counter for delay
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signal source_address_x, source_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0);
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signal target_address_x, target_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0);
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signal line_size_x, line_size_r : std_logic_vector (11 downto 0);
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signal source_lines_x, source_lines_r : std_logic_vector (15 downto 0);
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signal alphaOp_x, alphaOp_r : std_logic;
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signal front_buffer_x, front_buffer_r : std_logic;
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--internal signals
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--internal signals
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signal sysClk : std_logic; -- system clock
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signal sysReset : std_logic; -- system reset
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signal sysReset : std_logic; -- system reset
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signal blit_reset : std_logic;
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signal reset_blitter : std_logic;
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-- Blitter signals
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signal blit_begin : std_logic;
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signal source_address : std_logic_vector(ADDR_WIDTH-1 downto 0);
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signal source_lines : std_logic_vector (15 downto 0);
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signal line_size : std_logic_vector (11 downto 0);
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signal target_address : std_logic_vector(ADDR_WIDTH-1 downto 0);
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signal blit_done : std_logic;
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signal alphaOp : std_logic;
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signal front_buffer : std_logic;
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--Application Side Signals for the DualPort Controller
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--Application Side Signals for the DualPort Controller
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signal rst_i : std_logic; --tied reset signal
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signal rst_i : std_logic; --tied reset signal
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signal opBegun0, opBegun1 : std_logic; -- read/write operation started indicator
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signal opBegun0, opBegun1 : std_logic; -- read/write operation started indicator
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signal earlyOpBegun0, earlyOpBegun1 : std_logic; -- read/write operation started indicator
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signal earlyOpBegun0, earlyOpBegun1 : std_logic; -- read/write operation started indicator
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| Line 125... |
Line 159... |
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-- VGA related signals
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-- VGA related signals
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signal eof : std_logic; -- end-of-frame signal from VGA controller
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signal eof : std_logic; -- end-of-frame signal from VGA controller
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signal full : std_logic; -- indicates when the VGA pixel buffer is full
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signal full : std_logic; -- indicates when the VGA pixel buffer is full
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signal vga_address : unsigned(ADDR_WIDTH-1 downto 0); -- SDRAM address counter
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signal vga_address : unsigned(ADDR_WIDTH-1 downto 0); -- SDRAM address counter
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signal pixels : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal rst_n : std_logic; --VGA reset (active low)
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signal rst_n : std_logic; --VGA reset (active low)
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signal drawframe : std_logic; -- flag to indicate whether we are drawing current frame
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--------------------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------------------
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-- Beginning of Submodules
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-- Beginning of Submodules
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-- All instances of submodules and signals associated with them
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-- All instances of submodules and signals associated with them
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-- are declared within. Signals not directly associated with
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-- are declared within. Signals not directly associated with
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-- submodules are declared elsewhere.
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-- submodules are declared elsewhere.
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| Line 175... |
Line 212... |
done1 => done1,
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done1 => done1,
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hAddr1 => hAddr1,
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hAddr1 => hAddr1,
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hDIn1 => hDIn1,
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hDIn1 => hDIn1,
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hDOut1 => hDOut1,
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hDOut1 => hDOut1,
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status1 => open,
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status1 => open,
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-- connections to the SDRAM controller
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-- connections to the SDRAM controller
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rst => sdram_rst,
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rst => sdram_rst,
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rd => sdram_rd,
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rd => sdram_rd,
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wr => sdram_wr,
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wr => sdram_wr,
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rdPending => sdram_rdPending,
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rdPending => sdram_rdPending,
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| Line 242... |
Line 280... |
sData => pin_sData, -- SDRAM databus
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sData => pin_sData, -- SDRAM databus
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dqmh => pin_dqmh, -- SDRAM DQMH
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dqmh => pin_dqmh, -- SDRAM DQMH
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dqml => pin_dqml -- SDRAM DQML
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dqml => pin_dqml -- SDRAM DQML
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);
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);
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------------------------------------------------------------------------------------------------------------
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-- Instance of VGA driver, this unit generates the video signals from VRAM
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------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- Instantiate the VGA module
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------------------------------------------------------------------------
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u3 : vga
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u3 : vga
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generic map (
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generic map (
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FREQ => FREQ,
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FREQ => FREQ,
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CLK_DIV => VGA_CLK_DIV,
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CLK_DIV => VGA_CLK_DIV,
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PIXEL_WIDTH => PIXEL_WIDTH,
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PIXEL_WIDTH => PIXEL_WIDTH,
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| Line 260... |
Line 299... |
)
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)
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port map (
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port map (
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rst => rst_i,
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rst => rst_i,
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clk => sdram_clk1x, -- use the resync'ed master clock so VGA generator is in sync with SDRAM
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clk => sdram_clk1x, -- use the resync'ed master clock so VGA generator is in sync with SDRAM
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wr => rdDone0, -- write to pixel buffer when the data read from SDRAM is available
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wr => rdDone0, -- write to pixel buffer when the data read from SDRAM is available
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pixel_data_in => hDOut0, -- pixel data from SDRAM
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pixel_data_in => pixels, -- pixel data from SDRAM
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full => full, -- indicates when the pixel buffer is full
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full => full, -- indicates when the pixel buffer is full
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eof => eof, -- indicates when the VGA generator has finished a video frame
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eof => eof, -- indicates when the VGA generator has finished a video frame
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r => pin_red, -- RGB components (output)
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r => pin_red, -- RGB components (output)
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g => pin_green,
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g => pin_green,
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b => pin_blue,
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b => pin_blue,
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hsync_n => pin_hsync_n, -- horizontal sync
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hsync_n => pin_hsync_n, -- horizontal sync
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vsync_n => pin_vsync_n, -- vertical sync
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vsync_n => pin_vsync_n, -- vertical sync
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blank => open
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blank => open
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);
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);
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------------------------------------------------------------------------------------------------------------
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-- instance of main blitter
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------------------------------------------------------------------------------------------------------------
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u4: Blitter
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generic map(
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FREQ => FREQ,
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PIPE_EN => PIPE_EN,
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DATA_WIDTH => DATA_WIDTH,
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ADDR_WIDTH => ADDR_WIDTH
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)
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port map (
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clk =>sdram_clk1x,
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rst =>blit_reset,
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rd =>rd1,
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wr =>wr1,
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opBegun =>opBegun1,
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earlyopBegun =>earlyOpBegun1,
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done =>done1,
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rddone =>rddone1,
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rdPending =>rdPending1,
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Addr =>hAddr1,
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DIn =>hDIn1,
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DOut =>hDOut1,
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blit_begin =>blit_begin,
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source_address =>source_address,
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source_lines =>source_lines,
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target_address =>target_address,
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line_size =>line_size,
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alphaOp =>alphaOp,
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blit_done =>blit_done,
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front_buffer =>front_buffer
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);
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--------------------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------------------
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-- End of Submodules
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-- End of Submodules
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--------------------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------------------
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-- Begin Top Level Module
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-- Begin Top Level Module
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-- connect internal signals
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-- connect internal signals
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rst_i <= sysReset;
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rst_i <= sysReset;
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pin_ce_n <= '1'; -- disable Flash RAM
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pin_ce_n <= '1'; -- disable Flash RAM
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rd0 <= not full; -- negate the full signal for use in controlling the SDRAM read operation
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hDIn0 <= "0000000000000000000000"; -- don't need to write to port 0 (VGA Port)
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rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation
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hDIn0 <= "0000000000000000"; -- don't need to write to port 0 (VGA Port)
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wr0 <= '0';
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wr0 <= '0';
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hAddr0 <= std_logic_vector(vga_address);
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hAddr0 <= std_logic_vector(vga_address);
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blit_reset <= rst_i or reset_blitter;
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-- Port0 is reserved for VGA
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-- Port0 is reserved for VGA
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pixels <= hDOut0 when drawframe = '1' else "0000000000000000";
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source_address <= source_address_r;
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line_size <= line_size_r;
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target_address <= target_address_r;
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source_lines <= source_lines_r;
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alphaOp <= alphaOp_r;
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front_buffer <= YES;--front_buffer_r;
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comb:process(state_r, delay_r, plane0_dest_r)
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begin
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blit_begin <= NO; --default operations
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reset_blitter <= NO;
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state_x <= state_r; --default register values
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delay_x <= delay_r + 1;
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source_address_x <= source_address_r;
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line_size_x <= line_size_r;
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target_address_x <= target_address_r;
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source_lines_x <= source_lines_r;
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alphaOp_x <= alphaOp_r;
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plane0_dest_x <= plane0_dest_r;
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plane0_ypos_x <= plane0_ypos_r;
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front_buffer_x <= front_buffer_r;
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case state_r is
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when INIT =>
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blit_begin <= NO;
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reset_blitter <= YES;
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state_x <= INIT_BKG;
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plane0_dest_x <= x"000060";
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plane0_ypos_x <= x"000";
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front_buffer_x <= YES;
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when INIT_BKG =>
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--flip buffers
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source_address_x <= x"012C00";
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line_size_x <= x"0A0";
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target_address_x <= x"000000";
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source_lines_x <= x"00EF";
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alphaOp_x <= NO;
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blit_begin <= YES;
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state_x <= DRAW_BKG;
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when DRAW_BKG =>
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blit_begin <= YES;
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if (blit_done = YES) then
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reset_blitter <= YES;
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state_x <= BLIT_REST;
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end if;
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when BLIT_REST =>
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source_address_x <= x"01EBE5";
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line_size_x <= x"024";
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target_address_x <= plane0_dest_r;
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source_lines_x <= x"004E";
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alphaOp_x <= YES;
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reset_blitter <= YES;
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state_x <= INIT_SPRITE;
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when INIT_SPRITE =>
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blit_begin <= YES;
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state_x <= DRAW_SPRITE;
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when DRAW_SPRITE =>
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blit_begin <= YES;
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if (blit_done = YES) then
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reset_blitter <= YES;
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state_x <= UPDATE;
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end if;
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when UPDATE =>
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reset_blitter <= YES;
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if (delay_r = x"FFFFF") then
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plane0_dest_x <= plane0_dest_r + x"000140";
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plane0_ypos_x <= plane0_ypos_r + x"001";
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if (plane0_ypos_r = x"050") then
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plane0_dest_x <= x"000060";
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plane0_ypos_x <= x"000";
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end if;
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state_x <= INIT_BKG;
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end if;
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end case;
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end process;
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-- update the SDRAM address counter
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-- update the SDRAM address counter
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process(sdram_clk1x)
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process(sdram_clk1x)
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begin
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begin
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if rising_edge(sdram_clk1x) then
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if rising_edge(sdram_clk1x) then
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--VGA Related Stuff
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if eof = YES then
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if eof = YES then
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vga_address <= "0000000000000000000000"; -- reset the address at the end of a video frame
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drawframe <= not drawframe; -- draw every other frame
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elsif earlyOpBegun0 = YES then
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-- reset the address at the end of a video frame depending on which buffer is the front
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if (front_buffer = YES) then
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vga_address <= x"000000";
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else
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vga_address <= x"009600";
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end if;
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elsif (earlyOpBegun0 = YES) then
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vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun
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vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun
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end if;
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end if;
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--reset stuff
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if (sysReset = YES) then
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state_r <= INIT;
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end if;
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state_r <= state_x;
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delay_r <= delay_x;
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source_address_r <= source_address_x;
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line_size_r <= line_size_x;
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target_address_r <= target_address_x;
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source_lines_r <= source_lines_x;
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alphaOp_r <= alphaOp_x;
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plane0_dest_r <= plane0_dest_x;
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plane0_ypos_r <= plane0_ypos_x;
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front_buffer_r <= front_buffer_x;
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end if;
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end if;
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end process;
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end process;
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--process reset circuitry
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--process reset circuitry
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process(sdram_bufclk)
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process(sdram_bufclk)
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| Line 309... |
Line 501... |
--sysReset <= '0';
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--sysReset <= '0';
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sysReset <= not pin_pushbtn; -- push button will reset
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sysReset <= not pin_pushbtn; -- push button will reset
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end arch;
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end arch;
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No newline at end of file
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No newline at end of file
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