URL
https://opencores.org/ocsvn/395_vgs/395_vgs/trunk
[/] [395_vgs/] [trunk/] [hdl/] [fill-unit.vhd] - Diff between revs 15 and 16
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 15 |
Rev 16 |
| Line 85... |
Line 85... |
type cntrl_state is (idle, write_state, wait_state);
|
type cntrl_state is (idle, write_state, wait_state);
|
|
|
signal pixeldata, output : std_logic_vector(15 downto 0); -- broken down to 2 8 bit pixels
|
signal pixeldata, output : std_logic_vector(15 downto 0); -- broken down to 2 8 bit pixels
|
signal currentbuffer, write, start : std_logic;
|
signal currentbuffer, write, start : std_logic;
|
signal address : std_logic_vector(22 downto 0);
|
signal address : std_logic_vector(22 downto 0);
|
|
signal counter : std_logic_vector(11 downto 0);
|
begin
|
begin
|
hDIn1 <= output;
|
hDIn1 <= output;
|
hAddr1 <= address;
|
hAddr1 <= address;
|
wr1 <= '1';
|
wr1 <= '1';
|
start <= '1';
|
start <= '1';
|
|
output <= pixeldata;
|
|
|
|
|
process (clk)
|
process (clk, reset)
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
if address = "0000001001011000000000" then
|
if address = "0000001001011000000000" then
|
address <= "00000000000000000000000";
|
address <= "00000000000000000000000";
|
output <= "1111111111111111";
|
counter <= counter + 1;
|
elsif done1 = '1' then
|
elsif done1 = '1' then
|
address <= address + 1;
|
address <= address + 1;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
screendivide: process (counter)
|
|
begin
|
|
if (counter = "100000000000") then
|
|
pixeldata <= pixeldata + "0000010000000100";
|
|
else
|
|
pixeldata <= pixeldata;
|
|
end if;
|
|
end process;
|
|
|
end arch;
|
end arch;
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.