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Line 1... |
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--ECE395 GPU:
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--GPU Core Intermediate Block
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--=====================================================
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--Designed by:
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--Zuofu Cheng
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--James Cavanaugh
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--Eric Sands
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--
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--of the University of Illinois at Urbana Champaign
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--under the direction of Dr. Lippold Haken
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--====================================================
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--
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--Heavily based off of HDL examples provided by XESS Corporation
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--www.xess.com
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--
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--Based in part on Doug Hodson's work which in turn
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--was based off of the XSOC from Gray Research LLC.
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--
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--
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--release under the GNU General Public License
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--and kindly hosted by www.opencores.org
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library IEEE, UNISIM;
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library IEEE, UNISIM;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use UNISIM.VComponents.all;
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use UNISIM.VComponents.all;
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use WORK.common.all;
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use WORK.common.all;
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Line 55... |
size : in std_logic_vector(9 downto 0)
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size : in std_logic_vector(9 downto 0)
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);
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);
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end component GPU_core;
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end component GPU_core;
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end package GPU_core_pckg;
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end package GPU_core_pckg;
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 21:06:27 09/14/05
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-- Design Name:
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-- Module Name: GPU_core - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use WORK.fifo_cc_pckg.all;
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use WORK.fifo_cc_pckg.all;
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Line 105... |
Line 105... |
signal datain_q, dataout_q : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal datain_q, dataout_q : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal level_q : std_logic_vector(7 downto 0);
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signal level_q : std_logic_vector(7 downto 0);
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begin
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begin
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-- getstate : process (clk, rst, state)
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-- begin
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--
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-- if rst = '0' then
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-- state <= wait4Go;
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-- elsif state = wait4Go then
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-- if start_read = '1' then
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-- state <= getLine;
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-- end if;
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-- end if;
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--
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-- end process;
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-- getandwritedata : process(clk, rst, start_read, rdPending1, done1, dataout_q, opBegun1, datain_q)
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-- begin
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-- if rst = '1' then
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-- state <= wait4Go;
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-- wr_q <= '0';
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-- rd_q <= '0';
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-- wr1 <= '0';
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-- rd1 <= '0';
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-- hAddr1 <= (others => '0');
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-- else
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--
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-- case state is
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-- when wait4Go =>
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-- if start_read = '1' then
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-- state <= getLine;
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-- end if;
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--
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-- when writeLine =>
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-- address <= target_address;
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-- stop_address <= size + target_address;
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-- if rising_edge(clk) then
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-- -- check to see if the Line is done being written into SDRAM
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-- if address = stop_address and
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-- opBegun1 = '0' and done1 = '0' then
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-- state <= wait4Go;
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-- end if;
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--
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-- rd_q <= '1'; -- read from the queue
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-- hDIn1 <= dataout_q; -- data from the queue to SDRAM
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-- wr1 <= '1'; -- write to the SDRAM
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-- hAddr1 <= address; -- at target_address
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--
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-- if done1 = '1' then
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-- address <= address + 1;
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-- end if;
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--
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-- end if;
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--
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-- when getLine =>
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-- address <= source_address;
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-- stop_address <= size + source_address;
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-- if rising_edge(clk) then
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--
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-- -- check to see if the Line is loaded into the queue
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-- if address = stop_address and -- entire line has been read
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-- rdPending1 = '0' and done1 = '0' then -- read operation is complete
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-- state <= writeLine;
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-- end if;
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--
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-- wr_q <= '1';
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-- datain_q <= hDOut1;
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-- rd1 <= '1';
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-- hAddr1 <= address;
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--
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-- if done1 = '1' then
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-- address <= address + 1;
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-- end if;
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--
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-- end if;
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-- end case;
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-- end if;
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-- end process;
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statemachineread : process()
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statemachineread : process()
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begin
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begin
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case state is
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case state is
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when halt =>
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when halt =>
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Line 272... |
Line 196... |
rd_q <= '0';
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rd_q <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- getLinedata : process( clk, rst, rdPending1, done1, opBegun1, datain_q)
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-- begin
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-- if rst = '1' then
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-- state <= wait4Go;
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-- wr_q <= '0';
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-- rd_q <= '0';
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-- wr1 <= '0';
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-- rd1 <= '0';
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-- count <= (others <= '0');
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-- elsif state <= getLine then
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-- address <= source_address;
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-- if rising_edge(clk) then
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--
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-- -- check to see if the Line is loaded into the queue
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-- if count = size and -- entire line has been read
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-- rdPending = '0' and done1 = '0' then -- read operation is complete
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-- state <= writeLine;
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-- end if;
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--
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-- wr_q <= '1';
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-- datain_q <= hDOut1;
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-- rd1 <= 1;
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-- hAddr1 <= address;
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--
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-- if done1 = '1' then
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-- count <= count + 1;
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-- address <= address + 1;
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-- end if;
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--
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-- end if;
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-- end if;
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-- end process;
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u1 : fifo_cc
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u1 : fifo_cc
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port map(
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port map(
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clk=>clk,
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clk=>clk,
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rst=>rst,
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rst=>rst,
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rd=>rd_q,
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rd=>rd_q,
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