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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use WORK.common.all;
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use WORK.common.all;
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use WORK.xsasdram.all;
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use WORK.xsasdram.all;
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use WORK.sdram.all;
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use WORK.sdram.all;
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use WORK.vga_pckg.all;
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use WORK.vga_pckg.all;
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use WORK.fillunit_pckg.all;
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entity gpuChip is
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entity gpuChip is
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generic(
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generic(
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FREQ : natural := 50_000; -- frequency of operation in KHz
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FREQ : natural := 50_000; -- frequency of operation in KHz
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PIXEL_WIDTH : natural := 8; -- width of a pixel in memory
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PIXEL_WIDTH : natural := 8; -- width of a pixel in memory
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NUM_RGB_BITS : natural := 2; -- #bits in each R,G,B component of a pixel
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NUM_RGB_BITS : natural := 2; -- #bits in each R,G,B component of a pixel
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PIXELS_PER_LINE : natural := 320; -- width of image in pixels
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PIXELS_PER_LINE : natural := 320; -- width of image in pixels
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LINES_PER_FRAME : natural := 240; -- height of image in scanlines
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LINES_PER_FRAME : natural := 240; -- height of image in scanlines
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FIT_TO_SCREEN : boolean := true; -- adapt video timing to fit image width x
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FIT_TO_SCREEN : boolean := true; -- adapt video timing to fit image width x
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PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000000000000000"
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PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000111100001111"
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);
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);
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port(
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port(
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pin_clkin : in std_logic; -- main clock input from external clock source
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pin_clkin : in std_logic; -- main clock input from external clock source
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pin_ce_n : out std_logic; -- Flash RAM chip-enable
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pin_ce_n : out std_logic; -- Flash RAM chip-enable
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sData => pin_sData, -- SDRAM databus
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sData => pin_sData, -- SDRAM databus
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dqmh => pin_dqmh, -- SDRAM DQMH
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dqmh => pin_dqmh, -- SDRAM DQMH
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dqml => pin_dqml -- SDRAM DQML
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dqml => pin_dqml -- SDRAM DQML
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);
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);
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------------------------------------------------------------------------------------------------------------
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-- instance of vga
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------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- Instantiate the VGA module
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------------------------------------------------------------------------
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u3 : vga
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u3 : vga
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generic map (
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generic map (
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FREQ => FREQ,
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FREQ => FREQ,
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CLK_DIV => VGA_CLK_DIV,
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CLK_DIV => VGA_CLK_DIV,
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PIXEL_WIDTH => PIXEL_WIDTH,
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PIXEL_WIDTH => PIXEL_WIDTH,
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b => pin_blue,
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b => pin_blue,
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hsync_n => pin_hsync_n, -- horizontal sync
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hsync_n => pin_hsync_n, -- horizontal sync
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vsync_n => pin_vsync_n, -- vertical sync
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vsync_n => pin_vsync_n, -- vertical sync
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blank => open
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blank => open
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);
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);
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------------------------------------------------------------------------------------------------------------
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-- instance of fill-unit
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------------------------------------------------------------------------------------------------------------
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u4: fillunit
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generic map(
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FREQ => FREQ,
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DATA_WIDTH => DATA_WIDTH,
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HADDR_WIDTH => ADDR_WIDTH
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)
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port map(
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clk => sdram_clk1x, -- master clock
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reset => sysReset, -- reset for this entity
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rd1 => rd1, -- initiate read operation
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wr1 => wr1, -- initiate write operation
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opBegun => opBegun1, --operation recieved
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done1 => done1, -- read or write operation is done
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hAddr1 => hAddr1, -- address to SDRAM
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hDIn1 => hDIn1, -- data to dualport to SDRAM
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hDOut1 => hDOut1 -- data from dualport to SDRAM
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);
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--------------------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------------------
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-- End of Submodules
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-- End of Submodules
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--------------------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------------------
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-- Begin Top Level Module
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-- Begin Top Level Module
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