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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use WORK.common.all;
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use WORK.common.all;
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use WORK.xsasdram.all;
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use WORK.xsasdram.all;
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use WORK.sdram.all;
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use WORK.sdram.all;
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use WORK.vga_pckg.all;
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use WORK.vga_pckg.all;
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<<<<<<< gpuchip.vhd
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use WORK.gpu_core_pckg.all;
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=======
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use WORK.fillunit_pckg.all;
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use WORK.fillunit_pckg.all;
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>>>>>>> 1.5
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entity gpuChip is
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entity gpuChip is
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generic(
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generic(
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FREQ : natural := 50_000; -- frequency of operation in KHz
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FREQ : natural := 50_000; -- frequency of operation in KHz
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pin_green : out std_logic_vector(1 downto 0);
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pin_green : out std_logic_vector(1 downto 0);
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pin_blue : out std_logic_vector(1 downto 0);
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pin_blue : out std_logic_vector(1 downto 0);
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pin_hsync_n : out std_logic;
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pin_hsync_n : out std_logic;
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pin_vsync_n : out std_logic;
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pin_vsync_n : out std_logic;
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-- SRAM Cache connections
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pin_cData : inout std_logic_vector(15 downto 0); -- data bus to Cache
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pin_cAddr : out std_logic_vector(14 downto 0); -- Cache address bus
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pin_cwrite : out std_logic;
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pin_cread : out std_logic;
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-- SDRAM pin connections
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-- SDRAM pin connections
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pin_sclkfb : in std_logic; -- feedback SDRAM clock with PCB delays
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pin_sclkfb : in std_logic; -- feedback SDRAM clock with PCB delays
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pin_sclk : out std_logic; -- clock to SDRAM
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pin_sclk : out std_logic; -- clock to SDRAM
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pin_cke : out std_logic; -- SDRAM clock-enable
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pin_cke : out std_logic; -- SDRAM clock-enable
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pin_cs_n : out std_logic; -- SDRAM chip-select
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pin_cs_n : out std_logic; -- SDRAM chip-select
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hsync_n => pin_hsync_n, -- horizontal sync
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hsync_n => pin_hsync_n, -- horizontal sync
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vsync_n => pin_vsync_n, -- vertical sync
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vsync_n => pin_vsync_n, -- vertical sync
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blank => open
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blank => open
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);
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);
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------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------
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-- instance of fill-unit
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-- instance of fill-unit
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------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------
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u4: fillunit
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-- u4: fillunit
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-- generic map(
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-- FREQ => FREQ,
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-- DATA_WIDTH => DATA_WIDTH,
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-- HADDR_WIDTH => ADDR_WIDTH
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-- )
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-- port map(
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-- clk => sdram_clk1x, -- master clock
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-- reset => sysReset, -- reset for this entity
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-- rd1 => rd1, -- initiate read operation
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-- wr1 => wr1, -- initiate write operation
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-- opBegun => opBegun1, --operation recieved
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-- done1 => done1, -- read or write operation is done
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-- hAddr1 => hAddr1, -- address to SDRAM
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-- hDIn1 => hDIn1, -- data to dualport to SDRAM
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-- hDOut1 => hDOut1 -- data from dualport to SDRAM
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-- );
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--
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u5: gpu_core
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generic map(
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generic map(
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FREQ => FREQ,
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FREQ => FREQ,
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DATA_WIDTH => DATA_WIDTH,
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DATA_WIDTH => DATA_WIDTH,
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HADDR_WIDTH => ADDR_WIDTH
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HADDR_WIDTH => ADDR_WIDTH
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)
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)
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port map(
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port map(
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clk => sdram_clk1x, -- master clock
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clk =>sdram_clk1x,
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reset => sysReset, -- reset for this entity
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rst =>sysReset,
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rd1 => rd1, -- initiate read operation
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rd1 =>rd1,
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wr1 => wr1, -- initiate write operation
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wr1 =>wr1,
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opBegun => opBegun1, --operation recieved
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opBegun =>opBegun1,
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done1 => done1, -- read or write operation is done
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done1 =>done1,
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hAddr1 => hAddr1, -- address to SDRAM
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rddone1 =>rddone1,
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hDIn1 => hDIn1, -- data to dualport to SDRAM
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hAddr1 =>hAddr1,
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hDOut1 => hDOut1 -- data from dualport to SDRAM
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hDIn1 =>hDIn1,
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hDOut1 =>hDOut1,
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CacheDIn =>pin_cData,
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CacheAddr =>pin_cAddr,
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cread =>pin_cread,
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cwrite =>pin_cwrite
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);
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);
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--------------------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------------------
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-- End of Submodules
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-- End of Submodules
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--------------------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------------------
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-- Begin Top Level Module
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-- Begin Top Level Module
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-- connect internal signals
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-- connect internal signals
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rst_i <= sysReset;
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rst_i <= sysReset;
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pin_ce_n <= '1'; -- disable Flash RAM
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pin_ce_n <= '1'; -- disable Flash RAM
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rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation
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rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation
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hDIn0 <= "0000000000000000000000"; -- don't need to write to port 0 (VGA Port)
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hDIn0 <= "0000000000000000"; -- don't need to write to port 0 (VGA Port)
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wr0 <= '0';
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wr0 <= '0';
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hAddr0 <= std_logic_vector(vga_address);
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hAddr0 <= std_logic_vector(vga_address);
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-- Port0 is reserved for VGA
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-- Port0 is reserved for VGA
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