| Line 27... |
Line 27... |
use IEEE.numeric_std.all;
|
use IEEE.numeric_std.all;
|
use WORK.common.all;
|
use WORK.common.all;
|
use WORK.xsasdram.all;
|
use WORK.xsasdram.all;
|
use WORK.sdram.all;
|
use WORK.sdram.all;
|
use WORK.vga_pckg.all;
|
use WORK.vga_pckg.all;
|
use WORK.gpu_core_pckg.all;
|
use WORK.blitter_pckg.all;
|
|
|
entity gpuChip is
|
entity gpuChip is
|
|
|
generic(
|
generic(
|
FREQ : natural := 50_000; -- frequency of operation in KHz
|
FREQ : natural := 50_000; -- frequency of operation in KHz
|
| Line 47... |
Line 47... |
PIXEL_WIDTH : natural := 8; -- width of a pixel in memory
|
PIXEL_WIDTH : natural := 8; -- width of a pixel in memory
|
NUM_RGB_BITS : natural := 2; -- #bits in each R,G,B component of a pixel
|
NUM_RGB_BITS : natural := 2; -- #bits in each R,G,B component of a pixel
|
PIXELS_PER_LINE : natural := 320; -- width of image in pixels
|
PIXELS_PER_LINE : natural := 320; -- width of image in pixels
|
LINES_PER_FRAME : natural := 240; -- height of image in scanlines
|
LINES_PER_FRAME : natural := 240; -- height of image in scanlines
|
FIT_TO_SCREEN : boolean := true; -- adapt video timing to fit image width x
|
FIT_TO_SCREEN : boolean := true; -- adapt video timing to fit image width x
|
PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000111100001111"
|
PORT_TIME_SLOTS : std_logic_vector(15 downto 0) := "0000111111111111"
|
);
|
);
|
|
|
port(
|
port(
|
pin_clkin : in std_logic; -- main clock input from external clock source
|
pin_clkin : in std_logic; -- main clock input from external clock source
|
pin_ce_n : out std_logic; -- Flash RAM chip-enable
|
pin_ce_n : out std_logic; -- Flash RAM chip-enable
|
| Line 62... |
Line 62... |
pin_green : out std_logic_vector(1 downto 0);
|
pin_green : out std_logic_vector(1 downto 0);
|
pin_blue : out std_logic_vector(1 downto 0);
|
pin_blue : out std_logic_vector(1 downto 0);
|
pin_hsync_n : out std_logic;
|
pin_hsync_n : out std_logic;
|
pin_vsync_n : out std_logic;
|
pin_vsync_n : out std_logic;
|
|
|
-- SRAM Cache connections
|
|
--pin_cData : inout std_logic_vector(15 downto 0); -- data bus to Cache
|
|
--pin_cAddr : out std_logic_vector(14 downto 0); -- Cache address bus
|
|
--pin_cwrite : out std_logic;
|
|
--pin_cread : out std_logic;
|
|
|
|
-- SDRAM pin connections
|
-- SDRAM pin connections
|
pin_sclkfb : in std_logic; -- feedback SDRAM clock with PCB delays
|
pin_sclkfb : in std_logic; -- feedback SDRAM clock with PCB delays
|
pin_sclk : out std_logic; -- clock to SDRAM
|
pin_sclk : out std_logic; -- clock to SDRAM
|
pin_cke : out std_logic; -- SDRAM clock-enable
|
pin_cke : out std_logic; -- SDRAM clock-enable
|
pin_cs_n : out std_logic; -- SDRAM chip-select
|
pin_cs_n : out std_logic; -- SDRAM chip-select
|
| Line 91... |
Line 85... |
constant YES: std_logic := '1';
|
constant YES: std_logic := '1';
|
constant NO: std_logic := '0';
|
constant NO: std_logic := '0';
|
constant HI: std_logic := '1';
|
constant HI: std_logic := '1';
|
constant LO: std_logic := '0';
|
constant LO: std_logic := '0';
|
|
|
|
type gpuState is (
|
|
INIT, -- init
|
|
INIT_BKG,
|
|
DRAW_BKG,
|
|
BLIT_REST,
|
|
INIT_SPRITE,
|
|
DRAW_SPRITE,
|
|
UPDATE
|
|
);
|
|
|
|
signal state_r, state_x : gpuState; -- state register and next state
|
|
|
|
--registers
|
|
signal plane0_dest_r, plane0_dest_x : std_logic_vector (ADDR_WIDTH - 1 downto 0); -- sprite dest register
|
|
signal plane0_ypos_r, plane0_ypos_x : std_logic_vector (11 downto 0);
|
|
signal delay_r, delay_x : std_logic_vector (19 downto 0); --20 bit counter for delay
|
|
signal source_address_x, source_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0);
|
|
signal target_address_x, target_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0);
|
|
signal line_size_x, line_size_r : std_logic_vector (11 downto 0);
|
|
signal source_lines_x, source_lines_r : std_logic_vector (15 downto 0);
|
|
signal alphaOp_x, alphaOp_r : std_logic;
|
|
signal front_buffer_x, front_buffer_r : std_logic;
|
|
|
--internal signals
|
--internal signals
|
signal sysClk : std_logic; -- system clock
|
|
signal sysReset : std_logic; -- system reset
|
signal sysReset : std_logic; -- system reset
|
|
signal blit_reset : std_logic;
|
|
signal reset_blitter : std_logic;
|
|
|
signal start_read : std_logic;
|
-- Blitter signals
|
|
signal blit_begin : std_logic;
|
signal source_address : std_logic_vector(ADDR_WIDTH-1 downto 0);
|
signal source_address : std_logic_vector(ADDR_WIDTH-1 downto 0);
|
|
signal source_lines : std_logic_vector (15 downto 0);
|
|
signal line_size : std_logic_vector (11 downto 0);
|
signal target_address : std_logic_vector(ADDR_WIDTH-1 downto 0);
|
signal target_address : std_logic_vector(ADDR_WIDTH-1 downto 0);
|
signal end_address : std_logic_vector(ADDR_WIDTH-1 downto 0);
|
signal blit_done : std_logic;
|
|
signal alphaOp : std_logic;
|
|
signal front_buffer : std_logic;
|
|
|
--Application Side Signals for the DualPort Controller
|
--Application Side Signals for the DualPort Controller
|
signal rst_i : std_logic; --tied reset signal
|
signal rst_i : std_logic; --tied reset signal
|
signal opBegun0, opBegun1 : std_logic; -- read/write operation started indicator
|
signal opBegun0, opBegun1 : std_logic; -- read/write operation started indicator
|
signal earlyOpBegun0, earlyOpBegun1 : std_logic; -- read/write operation started indicator
|
signal earlyOpBegun0, earlyOpBegun1 : std_logic; -- read/write operation started indicator
|
| Line 189... |
Line 212... |
done1 => done1,
|
done1 => done1,
|
hAddr1 => hAddr1,
|
hAddr1 => hAddr1,
|
hDIn1 => hDIn1,
|
hDIn1 => hDIn1,
|
hDOut1 => hDOut1,
|
hDOut1 => hDOut1,
|
status1 => open,
|
status1 => open,
|
|
|
-- connections to the SDRAM controller
|
-- connections to the SDRAM controller
|
rst => sdram_rst,
|
rst => sdram_rst,
|
rd => sdram_rd,
|
rd => sdram_rd,
|
wr => sdram_wr,
|
wr => sdram_wr,
|
rdPending => sdram_rdPending,
|
rdPending => sdram_rdPending,
|
| Line 257... |
Line 281... |
dqmh => pin_dqmh, -- SDRAM DQMH
|
dqmh => pin_dqmh, -- SDRAM DQMH
|
dqml => pin_dqml -- SDRAM DQML
|
dqml => pin_dqml -- SDRAM DQML
|
);
|
);
|
|
|
------------------------------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------------------------------
|
-- instance of vga
|
-- Instance of VGA driver, this unit generates the video signals from VRAM
|
------------------------------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------------------------------
|
|
|
|
|
u3 : vga
|
u3 : vga
|
generic map (
|
generic map (
|
| Line 286... |
Line 310... |
hsync_n => pin_hsync_n, -- horizontal sync
|
hsync_n => pin_hsync_n, -- horizontal sync
|
vsync_n => pin_vsync_n, -- vertical sync
|
vsync_n => pin_vsync_n, -- vertical sync
|
blank => open
|
blank => open
|
);
|
);
|
|
|
|
|
------------------------------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------------------------------
|
-- instance of fill-unit
|
-- instance of main blitter
|
------------------------------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------------------------------
|
|
|
-- u4: fillunit
|
u4: Blitter
|
-- generic map(
|
|
-- FREQ => FREQ,
|
|
-- DATA_WIDTH => DATA_WIDTH,
|
|
-- HADDR_WIDTH => ADDR_WIDTH
|
|
-- )
|
|
-- port map(
|
|
-- clk => sdram_clk1x, -- master clock
|
|
-- reset => sysReset, -- reset for this entity
|
|
-- rd1 => rd1, -- initiate read operation
|
|
-- wr1 => wr1, -- initiate write operation
|
|
-- opBegun => opBegun1, --operation recieved
|
|
-- done1 => done1, -- read or write operation is done
|
|
-- hAddr1 => hAddr1, -- address to SDRAM
|
|
-- hDIn1 => hDIn1, -- data to dualport to SDRAM
|
|
-- hDOut1 => hDOut1 -- data from dualport to SDRAM
|
|
-- );
|
|
--
|
|
|
|
u5: gpu_core
|
|
generic map(
|
generic map(
|
FREQ => FREQ,
|
FREQ => FREQ,
|
|
PIPE_EN => PIPE_EN,
|
DATA_WIDTH => DATA_WIDTH,
|
DATA_WIDTH => DATA_WIDTH,
|
HADDR_WIDTH => ADDR_WIDTH
|
ADDR_WIDTH => ADDR_WIDTH
|
)
|
)
|
port map (
|
port map (
|
clk =>sdram_clk1x,
|
clk =>sdram_clk1x,
|
rst =>sysReset,
|
rst =>blit_reset,
|
rd1 =>rd1,
|
rd =>rd1,
|
wr1 =>wr1,
|
wr =>wr1,
|
opBegun1 =>opBegun1,
|
opBegun =>opBegun1,
|
done1 =>done1,
|
earlyopBegun =>earlyOpBegun1,
|
rddone1 =>rddone1,
|
done =>done1,
|
rdPending1 =>rdPending1,
|
rddone =>rddone1,
|
start_read =>start_read,
|
rdPending =>rdPending1,
|
|
Addr =>hAddr1,
|
|
DIn =>hDIn1,
|
|
DOut =>hDOut1,
|
|
blit_begin =>blit_begin,
|
source_address =>source_address,
|
source_address =>source_address,
|
|
source_lines =>source_lines,
|
target_address =>target_address,
|
target_address =>target_address,
|
end_address =>end_address,
|
line_size =>line_size,
|
hAddr1 =>hAddr1,
|
alphaOp =>alphaOp,
|
hDIn1 =>hDIn1,
|
blit_done =>blit_done,
|
hDOut1 =>hDOut1
|
front_buffer =>front_buffer
|
--CacheDIn =>pin_cData,
|
|
--CacheAddr =>pin_cAddr,
|
|
--cread =>pin_cread,
|
|
--cwrite =>pin_cwrite
|
|
);
|
);
|
|
|
--------------------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------------------
|
-- End of Submodules
|
-- End of Submodules
|
--------------------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------------------
|
-- Begin Top Level Module
|
-- Begin Top Level Module
|
|
|
-- connect internal signals
|
-- connect internal signals
|
rst_i <= sysReset;
|
rst_i <= sysReset;
|
pin_ce_n <= '1'; -- disable Flash RAM
|
pin_ce_n <= '1'; -- disable Flash RAM
|
|
|
rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation
|
rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation
|
hDIn0 <= "0000000000000000"; -- don't need to write to port 0 (VGA Port)
|
hDIn0 <= "0000000000000000"; -- don't need to write to port 0 (VGA Port)
|
wr0 <= '0';
|
wr0 <= '0';
|
hAddr0 <= std_logic_vector(vga_address);
|
hAddr0 <= std_logic_vector(vga_address);
|
|
|
-- Port0 is reserved for VGA
|
blit_reset <= rst_i or reset_blitter;
|
|
|
|
-- Port0 is reserved for VGA
|
pixels <= hDOut0 when drawframe = '1' else "0000000000000000";
|
pixels <= hDOut0 when drawframe = '1' else "0000000000000000";
|
|
|
|
source_address <= source_address_r;
|
|
line_size <= line_size_r;
|
|
target_address <= target_address_r;
|
|
source_lines <= source_lines_r;
|
|
alphaOp <= alphaOp_r;
|
|
front_buffer <= YES;--front_buffer_r;
|
|
|
|
comb:process(state_r, delay_r, plane0_dest_r)
|
|
begin
|
|
blit_begin <= NO; --default operations
|
|
reset_blitter <= NO;
|
|
|
|
state_x <= state_r; --default register values
|
|
delay_x <= delay_r + 1;
|
|
source_address_x <= source_address_r;
|
|
line_size_x <= line_size_r;
|
|
target_address_x <= target_address_r;
|
|
source_lines_x <= source_lines_r;
|
|
alphaOp_x <= alphaOp_r;
|
|
plane0_dest_x <= plane0_dest_r;
|
|
plane0_ypos_x <= plane0_ypos_r;
|
|
front_buffer_x <= front_buffer_r;
|
|
|
|
case state_r is
|
|
when INIT =>
|
|
blit_begin <= NO;
|
|
reset_blitter <= YES;
|
|
state_x <= INIT_BKG;
|
|
plane0_dest_x <= x"000060";
|
|
plane0_ypos_x <= x"000";
|
|
front_buffer_x <= YES;
|
|
|
|
when INIT_BKG =>
|
|
--flip buffers
|
|
source_address_x <= x"012C00";
|
|
line_size_x <= x"0A0";
|
|
target_address_x <= x"000000";
|
|
source_lines_x <= x"00EF";
|
|
alphaOp_x <= NO;
|
|
blit_begin <= YES;
|
|
state_x <= DRAW_BKG;
|
|
|
|
when DRAW_BKG =>
|
|
blit_begin <= YES;
|
|
|
|
if (blit_done = YES) then
|
|
reset_blitter <= YES;
|
|
state_x <= BLIT_REST;
|
|
end if;
|
|
|
|
when BLIT_REST =>
|
|
source_address_x <= x"01EBE5";
|
|
line_size_x <= x"024";
|
|
target_address_x <= plane0_dest_r;
|
|
source_lines_x <= x"004E";
|
|
alphaOp_x <= YES;
|
|
|
|
reset_blitter <= YES;
|
|
state_x <= INIT_SPRITE;
|
|
|
|
when INIT_SPRITE =>
|
|
blit_begin <= YES;
|
|
|
|
state_x <= DRAW_SPRITE;
|
|
|
|
when DRAW_SPRITE =>
|
|
blit_begin <= YES;
|
|
|
|
if (blit_done = YES) then
|
|
reset_blitter <= YES;
|
|
state_x <= UPDATE;
|
|
end if;
|
|
|
|
when UPDATE =>
|
|
reset_blitter <= YES;
|
|
if (delay_r = x"FFFFF") then
|
|
plane0_dest_x <= plane0_dest_r + x"000140";
|
|
plane0_ypos_x <= plane0_ypos_r + x"001";
|
|
if (plane0_ypos_r = x"050") then
|
|
plane0_dest_x <= x"000060";
|
|
plane0_ypos_x <= x"000";
|
|
end if;
|
|
state_x <= INIT_BKG;
|
|
end if;
|
|
|
|
end case;
|
|
end process;
|
|
|
-- update the SDRAM address counter
|
-- update the SDRAM address counter
|
process(sdram_clk1x)
|
process(sdram_clk1x)
|
begin
|
begin
|
if rising_edge(sdram_clk1x) then
|
if rising_edge(sdram_clk1x) then
|
|
|
|
--VGA Related Stuff
|
if eof = YES then
|
if eof = YES then
|
drawframe <= not drawframe; -- draw every other frame
|
drawframe <= not drawframe; -- draw every other frame
|
vga_address <= "00000000000000000000000"; -- reset the address at the end of a video frame
|
|
elsif earlyOpBegun0 = YES then
|
-- reset the address at the end of a video frame depending on which buffer is the front
|
|
if (front_buffer = YES) then
|
|
vga_address <= x"000000";
|
|
else
|
|
vga_address <= x"009600";
|
|
end if;
|
|
elsif (earlyOpBegun0 = YES) then
|
vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun
|
vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun
|
elsif drawframe = '0' then
|
|
vga_address <= vga_address + 1; --if we're not drawing a frame, keep incrementing the address
|
|
end if;
|
end if;
|
|
|
|
--reset stuff
|
|
if (sysReset = YES) then
|
|
state_r <= INIT;
|
|
end if;
|
|
|
|
state_r <= state_x;
|
|
delay_r <= delay_x;
|
|
source_address_r <= source_address_x;
|
|
line_size_r <= line_size_x;
|
|
target_address_r <= target_address_x;
|
|
source_lines_r <= source_lines_x;
|
|
alphaOp_r <= alphaOp_x;
|
|
plane0_dest_r <= plane0_dest_x;
|
|
plane0_ypos_r <= plane0_ypos_x;
|
|
front_buffer_r <= front_buffer_x;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--process reset circuitry
|
--process reset circuitry
|
process(sdram_bufclk)
|
process(sdram_bufclk)
|
| Line 382... |
Line 501... |
--sysReset <= '0';
|
--sysReset <= '0';
|
sysReset <= not pin_pushbtn; -- push button will reset
|
sysReset <= not pin_pushbtn; -- push button will reset
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
end arch;
|
end arch;
|
No newline at end of file
|
No newline at end of file
|
