| Line 34... |
Line 34... |
entity gpuChip is
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entity gpuChip is
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generic(
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generic(
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FREQ : natural := 50_000; -- frequency of operation in KHz
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FREQ : natural := 50_000; -- frequency of operation in KHz
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PIPE_EN : boolean := true; -- enable fast, pipelined SDRAM operation
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PIPE_EN : boolean := true; -- enable fast, pipelined SDRAM operation
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MULTIPLE_ACTIVE_ROWS: boolean := true; -- if true, allow an active row in each bank
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MULTIPLE_ACTIVE_ROWS: boolean := false; -- if true, allow an active row in each bank
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CLK_DIV : real := 1.0; -- SDRAM Clock div
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CLK_DIV : real := 1.0; -- SDRAM Clock div
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NROWS : natural := 4096; -- number of rows in the SDRAM
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NROWS : natural := 4096; -- number of rows in the SDRAM
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NCOLS : natural := 512; -- number of columns in each SDRAM row
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NCOLS : natural := 512; -- number of columns in each SDRAM row
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SADDR_WIDTH : natural := 12;
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SADDR_WIDTH : natural := 12;
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DATA_WIDTH : natural := 16; -- SDRAM databus width
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DATA_WIDTH : natural := 16; -- SDRAM databus width
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ADDR_WIDTH : natural := 23; -- host-side address width
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ADDR_WIDTH : natural := 24; -- host-side address width
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VGA_CLK_DIV : natural := 4; -- pixel clock = FREQ / CLK_DIV
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VGA_CLK_DIV : natural := 4; -- pixel clock = FREQ / CLK_DIV
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PIXEL_WIDTH : natural := 8; -- width of a pixel in memory
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PIXEL_WIDTH : natural := 8; -- width of a pixel in memory
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NUM_RGB_BITS : natural := 2; -- #bits in each R,G,B component of a pixel
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NUM_RGB_BITS : natural := 2; -- #bits in each R,G,B component of a pixel
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PIXELS_PER_LINE : natural := 320; -- width of image in pixels
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PIXELS_PER_LINE : natural := 320; -- width of image in pixels
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LINES_PER_FRAME : natural := 240; -- height of image in scanlines
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LINES_PER_FRAME : natural := 240; -- height of image in scanlines
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| Line 55... |
Line 55... |
port(
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port(
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pin_clkin : in std_logic; -- main clock input from external clock source
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pin_clkin : in std_logic; -- main clock input from external clock source
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pin_ce_n : out std_logic; -- Flash RAM chip-enable
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pin_ce_n : out std_logic; -- Flash RAM chip-enable
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pin_pushbtn : in std_logic;
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pin_pushbtn : in std_logic;
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-- blitter port connections
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pin_port_in : in std_logic_vector (7 downto 0);
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pin_port_addr : in std_logic_vector (3 downto 0);
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pin_load : in std_logic;
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pin_start : in std_logic;
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pin_done : out std_logic;
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pin_flip_buffer: in std_logic;
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-- vga port connections
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-- vga port connections
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pin_red : out std_logic_vector(1 downto 0);
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pin_red : out std_logic_vector(1 downto 0);
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pin_green : out std_logic_vector(1 downto 0);
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pin_green : out std_logic_vector(1 downto 0);
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pin_blue : out std_logic_vector(1 downto 0);
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pin_blue : out std_logic_vector(1 downto 0);
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pin_hsync_n : out std_logic;
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pin_hsync_n : out std_logic;
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| Line 87... |
Line 96... |
constant HI: std_logic := '1';
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constant HI: std_logic := '1';
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constant LO: std_logic := '0';
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constant LO: std_logic := '0';
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type gpuState is (
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type gpuState is (
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INIT, -- init
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INIT, -- init
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INIT_BKG,
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LOAD,
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DRAW_BKG,
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DRAW,
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BLIT_REST,
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REST
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INIT_SPRITE,
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DRAW_SPRITE,
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UPDATE
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);
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);
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signal state_r, state_x : gpuState; -- state register and next state
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signal state_r, state_x : gpuState; -- state register and next state
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--registers
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--registers
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signal plane0_dest_r, plane0_dest_x : std_logic_vector (ADDR_WIDTH - 1 downto 0); -- sprite dest register
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signal source_address_x, source_address_r : std_logic_vector (ADDR_WIDTH - 1 downto 0); -- sprite dest register
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signal plane0_ypos_r, plane0_ypos_x : std_logic_vector (11 downto 0);
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signal delay_r, delay_x : std_logic_vector (19 downto 0); --20 bit counter for delay
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signal source_address_x, source_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0);
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signal target_address_x, target_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0);
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signal target_address_x, target_address_r : std_logic_vector (ADDR_WIDTH -1 downto 0);
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signal line_size_x, line_size_r : std_logic_vector (11 downto 0);
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signal source_lines_x, source_lines_r : std_logic_vector (15 downto 0);
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signal source_lines_x, source_lines_r : std_logic_vector (15 downto 0);
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signal line_size_x, line_size_r : std_logic_vector (11 downto 0);
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signal alphaOp_x, alphaOp_r : std_logic;
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signal alphaOp_x, alphaOp_r : std_logic;
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signal front_buffer_x, front_buffer_r : std_logic;
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signal front_buffer_x, front_buffer_r : std_logic;
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signal idle_x, idle_r : std_logic;
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--signal flip_buf_pend_x, flip_buf_pend_r : std_logic;
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--internal signals
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--internal signals
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signal sysReset : std_logic; -- system reset
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signal sysReset : std_logic; -- system reset
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signal blit_reset : std_logic;
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signal blit_reset : std_logic;
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signal reset_blitter : std_logic;
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signal reset_blitter : std_logic;
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| Line 123... |
Line 128... |
signal target_address : std_logic_vector(ADDR_WIDTH-1 downto 0);
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signal target_address : std_logic_vector(ADDR_WIDTH-1 downto 0);
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signal blit_done : std_logic;
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signal blit_done : std_logic;
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signal alphaOp : std_logic;
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signal alphaOp : std_logic;
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signal front_buffer : std_logic;
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signal front_buffer : std_logic;
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signal port_in : std_logic_vector (7 downto 0);
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signal port_addr : std_logic_vector (3 downto 0);
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--Application Side Signals for the DualPort Controller
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--Application Side Signals for the DualPort Controller
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signal rst_i : std_logic; --tied reset signal
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signal rst_i : std_logic; --tied reset signal
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signal opBegun0, opBegun1 : std_logic; -- read/write operation started indicator
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signal opBegun0, opBegun1 : std_logic; -- read/write operation started indicator
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signal earlyOpBegun0, earlyOpBegun1 : std_logic; -- read/write operation started indicator
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signal earlyOpBegun0, earlyOpBegun1 : std_logic; -- read/write operation started indicator
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signal rdPending0, rdPending1 : std_logic; -- read operation pending in SDRAM pipeline indicator
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signal rdPending0, rdPending1 : std_logic; -- read operation pending in SDRAM pipeline indicator
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| Line 363... |
Line 371... |
blit_reset <= rst_i or reset_blitter;
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blit_reset <= rst_i or reset_blitter;
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-- Port0 is reserved for VGA
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-- Port0 is reserved for VGA
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pixels <= hDOut0 when drawframe = '1' else "0000000000000000";
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pixels <= hDOut0 when drawframe = '1' else "0000000000000000";
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port_in <= pin_port_in;
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port_addr <= pin_port_addr;
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pin_done <= idle_r;
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source_address <= source_address_r;
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source_address <= source_address_r;
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line_size <= line_size_r;
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line_size <= line_size_r;
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target_address <= target_address_r;
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target_address <= target_address_r;
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source_lines <= source_lines_r;
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source_lines <= source_lines_r;
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alphaOp <= alphaOp_r;
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alphaOp <= alphaOp_r;
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front_buffer <= YES;--front_buffer_r;
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front_buffer <= YES;--front_buffer_r;
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comb:process(state_r, delay_r, plane0_dest_r)
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comb:process(state_r, port_in, port_addr, pin_start)
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begin
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begin
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blit_begin <= NO; --default operations
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blit_begin <= NO; --default operations
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reset_blitter <= NO;
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reset_blitter <= NO;
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state_x <= state_r; --default register values
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state_x <= state_r; --default register values
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delay_x <= delay_r + 1;
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source_address_x <= source_address_r;
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source_address_x <= source_address_r;
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line_size_x <= line_size_r;
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target_address_x <= target_address_r;
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target_address_x <= target_address_r;
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source_lines_x <= source_lines_r;
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source_lines_x <= source_lines_r;
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line_size_x <= line_size_r;
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alphaOp_x <= alphaOp_r;
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alphaOp_x <= alphaOp_r;
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plane0_dest_x <= plane0_dest_r;
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plane0_ypos_x <= plane0_ypos_r;
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front_buffer_x <= front_buffer_r;
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front_buffer_x <= front_buffer_r;
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idle_x <= idle_r;
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case state_r is
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case state_r is
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when INIT =>
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when INIT =>
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blit_begin <= NO;
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idle_x <= YES;
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reset_blitter <= YES;
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reset_blitter <= YES;
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state_x <= INIT_BKG;
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state_x <= LOAD;
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plane0_dest_x <= x"000060";
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plane0_ypos_x <= x"000";
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front_buffer_x <= YES;
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when INIT_BKG =>
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--flip buffers
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source_address_x <= x"012C00";
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line_size_x <= x"0A0";
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target_address_x <= x"000000";
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source_lines_x <= x"00EF";
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alphaOp_x <= NO;
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blit_begin <= YES;
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state_x <= DRAW_BKG;
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when DRAW_BKG =>
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when LOAD =>
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blit_begin <= YES;
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if (pin_load = YES) then
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case port_addr is
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if (blit_done = YES) then
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when "0000" => source_address_x(23 downto 16) <= port_in;
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reset_blitter <= YES;
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when "0001" => source_address_x(15 downto 8) <= port_in;
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state_x <= BLIT_REST;
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when "0010" => source_address_x(7 downto 0) <= port_in;
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when "0011" => target_address_x(23 downto 16) <= port_in;
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when "0100" => target_address_x(15 downto 8) <= port_in;
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when "0101" => target_address_x(7 downto 0) <= port_in;
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when "0110" => source_lines_x (15 downto 8) <= port_in;
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when "0111" => source_lines_x (7 downto 0) <= port_in;
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when "1000" => line_size_x (11 downto 8) <= port_in(3 downto 0);
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when "1001" => line_size_x (7 downto 0) <= port_in;
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when "1010" => alphaOp_x <= port_in(0);
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when others =>
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end case;
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end if;
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end if;
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when BLIT_REST =>
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if (pin_start = YES) then
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source_address_x <= x"01EBE5";
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idle_x <= NO;
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line_size_x <= x"024";
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state_x <= DRAW;
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target_address_x <= plane0_dest_r;
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end if;
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source_lines_x <= x"004E";
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alphaOp_x <= YES;
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reset_blitter <= YES;
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state_x <= INIT_SPRITE;
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when INIT_SPRITE =>
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blit_begin <= YES;
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state_x <= DRAW_SPRITE;
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when DRAW_SPRITE =>
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when DRAW =>
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blit_begin <= YES;
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blit_begin <= YES;
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if (blit_done = YES) then
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if (blit_done = YES) then
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reset_blitter <= YES;
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reset_blitter <= YES;
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state_x <= UPDATE;
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idle_x <= YES;
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state_x <= REST;
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end if;
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end if;
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when UPDATE =>
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when REST =>
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reset_blitter <= YES;
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reset_blitter <= YES;
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if (delay_r = x"FFFFF") then
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state_x <= LOAD;
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plane0_dest_x <= plane0_dest_r + x"000140";
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plane0_ypos_x <= plane0_ypos_r + x"001";
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if (plane0_ypos_r = x"050") then
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plane0_dest_x <= x"000060";
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plane0_ypos_x <= x"000";
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end if;
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state_x <= INIT_BKG;
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end if;
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end case;
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end case;
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end process;
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end process;
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-- update the SDRAM address counter
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-- update the SDRAM address counter
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| Line 464... |
Line 454... |
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-- reset the address at the end of a video frame depending on which buffer is the front
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-- reset the address at the end of a video frame depending on which buffer is the front
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if (front_buffer = YES) then
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if (front_buffer = YES) then
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vga_address <= x"000000";
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vga_address <= x"000000";
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else
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else
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vga_address <= x"009600";
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vga_address <= x"000000"; --temporary
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end if;
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end if;
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elsif (earlyOpBegun0 = YES) then
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elsif (earlyOpBegun0 = YES) then
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vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun
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vga_address <= vga_address + 1; -- go to the next address once the read of the current address has begun
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end if;
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end if;
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--reset stuff
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--reset stuff
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if (sysReset = YES) then
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if (sysReset = YES) then
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state_r <= INIT;
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state_r <= INIT;
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end if;
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end if;
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state_r <= state_x;
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state_r <= state_x;
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delay_r <= delay_x;
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source_address_r <= source_address_x;
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source_address_r <= source_address_x;
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line_size_r <= line_size_x;
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target_address_r <= target_address_x;
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target_address_r <= target_address_x;
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source_lines_r <= source_lines_x;
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source_lines_r <= source_lines_x;
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line_size_r <= line_size_x;
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alphaOp_r <= alphaOp_x;
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alphaOp_r <= alphaOp_x;
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plane0_dest_r <= plane0_dest_x;
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plane0_ypos_r <= plane0_ypos_x;
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front_buffer_r <= front_buffer_x;
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front_buffer_r <= front_buffer_x;
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idle_r <= idle_x;
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end if;
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end if;
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end process;
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end process;
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--process reset circuitry
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--process reset circuitry
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