| Line 29... |
Line 29... |
);
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);
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end component vga;
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end component vga;
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end package vga_pckg;
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end package vga_pckg;
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library ieee, unisim;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use unisim.vcomponents.all;
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package fifo_cc_pckg is
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component fifo_cc is
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port (
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clk : in std_logic;
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rst : in std_logic;
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rd : in std_logic;
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wr : in std_logic;
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data_in : in std_logic_vector(15 downto 0);
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data_out : out std_logic_vector(15 downto 0);
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full : out std_logic;
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empty : out std_logic;
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level : out std_logic_vector(7 downto 0)
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);
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end component fifo_cc;
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end package fifo_cc_pckg;
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library IEEE, unisim;
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library IEEE, unisim;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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| Line 40... |
Line 62... |
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entity vga is
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entity vga is
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generic (
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generic (
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FREQ : natural := 50_000; -- master clock frequency (in KHz)
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FREQ : natural := 50_000; -- master clock frequency (in KHz)
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CLK_DIV : natural := 1; -- FREQ / CLK_DIV = pixel clock
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CLK_DIV : natural := 1; -- FREQ / CLK_DIV = pixel clock
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PIXEL_WIDTH : natural := 4; -- pixel width: 1, 2, 4, 8, or 16 bits
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PIXEL_WIDTH : natural := 8; -- pixel width: 1, 2, 4, 8, or 16 bits
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PIXELS_PER_LINE : natural := 1024; -- pixels per video scan line
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PIXELS_PER_LINE : natural := 320; -- pixels per video scan line
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LINES_PER_FRAME : natural := 512; -- scan lines per video frame
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LINES_PER_FRAME : natural := 200; -- scan lines per video frame
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NUM_RGB_BITS : natural := 2; -- width of R, G and B color output buses
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NUM_RGB_BITS : natural := 2; -- width of R, G and B color output buses
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FIT_TO_SCREEN : boolean := true -- fit width x length to monitor screen
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FIT_TO_SCREEN : boolean := true -- fit width x length to monitor screen
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);
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);
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port (
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port (
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rst : in std_logic; -- reset
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rst : in std_logic; -- reset
|
