URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [Changelog.txt] - Diff between revs 7 and 9

Rev 7	Rev 9
Line 1...	Line 1...
`Changelong`	`Changelong`
`----------`	`----------`

	`06.01.14`
	`--------`

	`- decoders.v : added registered outputs for the source/destination address registers`

`05.01.14`	`05.01.14`
`--------`	`--------`

`- MC6809_cpu.v : fixed exg (wrong source), implemented SYNC`	`- MC6809_cpu.v : fixed exg (wrong source), implemented SYNC`
	`- decoders.v : fixed destination for BIT`
	`- defs.v : reduced the number of ALU opcodes`
	`- alu16.v : reduced the number of ALU opcodes, fused BIT with AND, CMP with SUB`

`01.01.14`	`01.01.14`
`--------`	`--------`

`- alu16.v : the alu has been bronken in two units`	`- alu16.v : the alu has been bronken in two units`