| Line 20... |
Line 20... |
input wire [7:0] cpu_data_i,
|
input wire [7:0] cpu_data_i,
|
output wire [7:0] cpu_data_o
|
output wire [7:0] cpu_data_o
|
);
|
);
|
|
|
wire k_reset;
|
wire k_reset;
|
wire k_clk;
|
|
assign k_clk = cpu_clk;
|
|
|
|
reg [7:0] k_opcode, k_postbyte, k_ind_ea; /* all bytes of an instruction */
|
reg [7:0] k_opcode, k_postbyte, k_ind_ea; /* all bytes of an instruction */
|
reg [7:0] k_pp_regs, k_pp_active_reg; // push/pull mask
|
reg [7:0] k_pp_regs; // push/pull registers to process
|
|
reg [3:0] k_pp_active_reg; // push/pull active register
|
reg [7:0] k_memhi, k_memlo, k_cpu_data_o; /* operand read from memory */
|
reg [7:0] k_memhi, k_memlo, k_cpu_data_o; /* operand read from memory */
|
reg [7:0] k_ofslo, k_ofshi, k_eahi, k_ealo;
|
reg [7:0] k_ofslo, k_ofshi, k_eahi, k_ealo;
|
reg [5:0] state, // state of the main state machine
|
reg [5:0] state, // state of the main state machine
|
next_state, // next state to exit to from the read from [PC] state machine
|
next_state, // next state to exit to from the read from [PC] state machine
|
next_mem_state, // next state to exit to from the read from memory state machine
|
next_mem_state, // next state to exit to from the read from memory state machine
|
| Line 36... |
Line 35... |
reg k_write_tfr, k_write_exg;
|
reg k_write_tfr, k_write_exg;
|
reg k_cpu_oe, k_cpu_we, k_inc_pc;
|
reg k_cpu_oe, k_cpu_we, k_inc_pc;
|
reg [15:0] k_cpu_addr, k_new_pc;
|
reg [15:0] k_cpu_addr, k_new_pc;
|
reg k_write_pc, k_inc_su, k_dec_su, k_set_e, k_clear_e;
|
reg k_write_pc, k_inc_su, k_dec_su, k_set_e, k_clear_e;
|
reg [1:0] k_mem_dest;
|
reg [1:0] k_mem_dest;
|
|
reg k_mul_cnt; // multiplier couner
|
reg k_write_dest; // set for 1 clock when a register has to be written, dec_o_dest_reg_addr has the register source
|
reg k_write_dest; // set for 1 clock when a register has to be written, dec_o_dest_reg_addr has the register source
|
reg k_write_post_incdec; // asserted when in the last write cycle or in write back for loads
|
reg k_write_post_incdec; // asserted when in the last write cycle or in write back for loads
|
reg k_forced_mem_size; // used to force the size of a memory read to be 16 bits, used for vector fetch
|
reg k_forced_mem_size; // used to force the size of a memory read to be 16 bits, used for vector fetch
|
/****
|
/****
|
* Decoder outputs
|
* Decoder outputs
|
| Line 59... |
Line 59... |
/* test condition */
|
/* test condition */
|
wire dec_o_cond_taken;
|
wire dec_o_cond_taken;
|
/* ALU outputs */
|
/* ALU outputs */
|
wire [15:0] alu_o_result;
|
wire [15:0] alu_o_result;
|
wire [7:0] alu_o_CCR;
|
wire [7:0] alu_o_CCR;
|
|
wire [7:0] alu8_o_result;
|
|
wire [7:0] alu8_o_CCR;
|
/* Register Module outputs */
|
/* Register Module outputs */
|
wire [15:0] regs_o_left_path_data, regs_o_right_path_data, regs_o_eamem_addr, regs_o_su;
|
wire [15:0] regs_o_left_path_data, regs_o_right_path_data, regs_o_eamem_addr, regs_o_su;
|
wire [7:0] regs_o_dp;
|
wire [7:0] regs_o_dp;
|
wire [15:0] regs_o_pc;
|
wire [15:0] regs_o_pc;
|
wire [7:0] regs_o_CCR;
|
wire [7:0] regs_o_CCR;
|
| Line 81... |
Line 83... |
|
|
assign k_nmi_req = k_reg_nmi[2] & k_reg_nmi[1];
|
assign k_nmi_req = k_reg_nmi[2] & k_reg_nmi[1];
|
assign k_firq_req = k_reg_firq[2] & k_reg_firq[1];
|
assign k_firq_req = k_reg_firq[2] & k_reg_firq[1];
|
assign k_irq_req = k_reg_irq[2] & k_reg_irq[1];
|
assign k_irq_req = k_reg_irq[2] & k_reg_irq[1];
|
|
|
alu16 alu(
|
alu alu(
|
.clk(k_clk),
|
.clk_in(cpu_clk),
|
.a_in(datamux_o_alu_in_left_path_data),
|
.a_in(datamux_o_alu_in_left_path_data),
|
.b_in(datamux_o_alu_in_right_path_data),
|
.b_in(datamux_o_alu_in_right_path_data),
|
.CCR(regs_o_CCR), /* flags */
|
.CCR(regs_o_CCR), /* flags */
|
.opcode_in(dec_o_alu_opcode), /* ALU k_opcode */
|
.opcode_in(dec_o_alu_opcode), /* ALU k_opcode */
|
.sz_in(dec_o_alu_size), /* size, low 8 bit, high 16 bit */
|
.sz_in(dec_o_alu_size),
|
.q_out(alu_o_result), /* ALU result */
|
.q_out(alu_o_result), /* ALU result */
|
.CCRo(alu_o_CCR)
|
.CCRo(alu_o_CCR)
|
);
|
);
|
|
|
|
|
regblock regs(
|
regblock regs(
|
.clk_in(k_clk),
|
.clk_in(cpu_clk),
|
.path_left_addr(datamux_o_alu_in_left_path_addr),
|
.path_left_addr(datamux_o_alu_in_left_path_addr),
|
.path_right_addr(dec_o_right_path_addr),
|
.path_right_addr(dec_o_right_path_addr),
|
.write_reg_addr(datamux_o_dest_reg_addr),
|
.write_reg_addr(datamux_o_dest_reg_addr),
|
.exg_dest_r(k_postbyte[3:0]),
|
.exg_dest_r(k_postbyte[3:0]),
|
.eapostbyte( k_ind_ea ),
|
.eapostbyte( k_ind_ea ),
|
| Line 191... |
Line 194... |
|
|
/* Left Register read mux
|
/* Left Register read mux
|
*/
|
*/
|
always @(*)
|
always @(*)
|
begin
|
begin
|
|
if (k_pp_active_reg != `RN_INV)
|
|
datamux_o_alu_in_left_path_addr = k_pp_active_reg;
|
|
else
|
datamux_o_alu_in_left_path_addr = dec_o_left_path_addr;
|
datamux_o_alu_in_left_path_addr = dec_o_left_path_addr;
|
case (k_pp_active_reg)
|
|
8'h80: datamux_o_alu_in_left_path_addr = `RN_PC;
|
/*
|
8'h40: datamux_o_alu_in_left_path_addr = (dec_o_use_s) ? `RN_U:`RN_S;
|
case (k_pp_active_reg)
|
8'h20: datamux_o_alu_in_left_path_addr = `RN_IY;
|
8'h80: datamux_o_alu_in_left_path_addr = `RN_PC;
|
8'h10: datamux_o_alu_in_left_path_addr = `RN_IX;
|
8'h40: datamux_o_alu_in_left_path_addr = (dec_o_use_s) ? `RN_U:`RN_S;
|
8'h08: datamux_o_alu_in_left_path_addr = `RN_DP;
|
8'h20: datamux_o_alu_in_left_path_addr = `RN_IY;
|
8'h04: datamux_o_alu_in_left_path_addr = `RN_ACCB;
|
8'h10: datamux_o_alu_in_left_path_addr = `RN_IX;
|
8'h02: datamux_o_alu_in_left_path_addr = `RN_ACCA;
|
8'h08: datamux_o_alu_in_left_path_addr = `RN_DP;
|
8'h01: datamux_o_alu_in_left_path_addr = `RN_CC;
|
8'h04: datamux_o_alu_in_left_path_addr = `RN_ACCB;
|
endcase
|
8'h02: datamux_o_alu_in_left_path_addr = `RN_ACCA;
|
|
8'h01: datamux_o_alu_in_left_path_addr = `RN_CC;
|
|
8'h00: datamux_o_alu_in_left_path_addr = dec_o_left_path_addr;
|
|
endcase
|
|
*/
|
end
|
end
|
|
|
/* Destination register address MUX
|
/* Destination register address MUX
|
*/
|
*/
|
always @(*)
|
always @(*)
|
begin
|
begin
|
|
if (k_pp_active_reg != `RN_INV)
|
|
datamux_o_dest_reg_addr = k_pp_active_reg;
|
|
else
|
datamux_o_dest_reg_addr = dec_o_dest_reg_addr;
|
datamux_o_dest_reg_addr = dec_o_dest_reg_addr;
|
case (k_pp_active_reg)
|
/*
|
8'h80: datamux_o_dest_reg_addr = `RN_PC;
|
case (k_pp_active_reg)
|
8'h40: datamux_o_dest_reg_addr = (dec_o_use_s) ? `RN_U:`RN_S;
|
8'h80: datamux_o_dest_reg_addr = `RN_PC;
|
8'h20: datamux_o_dest_reg_addr = `RN_IY;
|
8'h40: datamux_o_dest_reg_addr = (dec_o_use_s) ? `RN_U:`RN_S;
|
8'h10: datamux_o_dest_reg_addr = `RN_IX;
|
8'h20: datamux_o_dest_reg_addr = `RN_IY;
|
8'h08: datamux_o_dest_reg_addr = `RN_DP;
|
8'h10: datamux_o_dest_reg_addr = `RN_IX;
|
8'h04: datamux_o_dest_reg_addr = `RN_ACCB;
|
8'h08: datamux_o_dest_reg_addr = `RN_DP;
|
8'h02: datamux_o_dest_reg_addr = `RN_ACCA;
|
8'h04: datamux_o_dest_reg_addr = `RN_ACCB;
|
8'h01: datamux_o_dest_reg_addr = `RN_CC;
|
8'h02: datamux_o_dest_reg_addr = `RN_ACCA;
|
endcase
|
8'h01: datamux_o_dest_reg_addr = `RN_CC;
|
|
8'h00: datamux_o_dest_reg_addr = dec_o_dest_reg_addr;
|
|
endcase
|
|
*/
|
end
|
end
|
|
|
/* Destination register data mux
|
/* Destination register data mux
|
* selects the source to write to register. 16 bit registers have to be written at once after reading the low byte
|
* selects the source to write to register. 16 bit registers have to be written at once after reading the low byte
|
*
|
*
|
| Line 295... |
Line 311... |
`MOD_MINUS1: datamux_o_alu_in_right_path_data = 16'hffff;
|
`MOD_MINUS1: datamux_o_alu_in_right_path_data = 16'hffff;
|
endcase
|
endcase
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge k_clk or posedge k_reset)
|
always @(posedge cpu_clk or posedge k_reset)
|
begin
|
begin
|
if (k_reset == 1'b1)
|
if (k_reset == 1'b1)
|
begin
|
begin
|
state <= `SEQ_COLDRESET;
|
state <= `SEQ_COLDRESET;
|
k_reg_nmi <= 0;
|
k_reg_nmi <= 0;
|
| Line 447... |
Line 463... |
end
|
end
|
end
|
end
|
`SEQ_FETCH_1:
|
`SEQ_FETCH_1:
|
begin
|
begin
|
k_cpu_oe <= 1;
|
k_cpu_oe <= 1;
|
state <= `SEQ_FETCH_2;
|
|
k_inc_pc <= 1;
|
k_inc_pc <= 1;
|
|
k_p2_valid <= 0; // set when an k_opcode is page 2
|
|
k_p3_valid <= 0; // set when an k_opcode is page 3
|
|
k_pp_active_reg <= `RN_INV; // ensures that only push/pull control the left/dest muxes
|
|
state <= `SEQ_FETCH_2;
|
end
|
end
|
`SEQ_FETCH_2:
|
`SEQ_FETCH_2:
|
begin
|
begin
|
k_opcode <= cpu_data_i;
|
k_opcode <= cpu_data_i;
|
case (cpu_data_i[7:0]) /* page 2 & 3 opcodes are recognized here */
|
case (cpu_data_i[7:0]) /* page 2 & 3 opcodes are recognized here */
|
8'h10:
|
8'h10:
|
begin
|
begin
|
k_p2_valid <= 1;
|
k_p2_valid <= 1;
|
k_p3_valid <= 0;
|
|
state <= `SEQ_FETCH_3;
|
state <= `SEQ_FETCH_3;
|
end
|
end
|
8'h11:
|
8'h11:
|
begin
|
begin
|
k_p2_valid <= 0;
|
|
k_p3_valid <= 1;
|
k_p3_valid <= 1;
|
state <= `SEQ_FETCH_3;
|
state <= `SEQ_FETCH_3;
|
end
|
end
|
8'h1e, 8'h1f:
|
8'h1e, 8'h1f:
|
begin
|
|
state <= `SEQ_FETCH_3; // tfr, exg, treated separately
|
state <= `SEQ_FETCH_3; // tfr, exg, treated separately
|
k_p2_valid <= 0; // set when an k_opcode is page 2
|
|
k_p3_valid <= 0; // set when an k_opcode is page 3
|
|
end
|
|
default:
|
default:
|
begin
|
|
state <= `SEQ_DECODE;
|
state <= `SEQ_DECODE;
|
k_p2_valid <= 0; // set when an k_opcode is page 2
|
|
k_p3_valid <= 0; // set when an k_opcode is page 3
|
|
end
|
|
endcase
|
endcase
|
k_pp_active_reg <= 8'h00; // prevents wrong register in left/dest data muxes
|
|
end
|
end
|
`SEQ_FETCH_3:
|
`SEQ_FETCH_3:
|
begin
|
begin
|
state <= `SEQ_FETCH_4;
|
state <= `SEQ_FETCH_4;
|
k_cpu_addr <= regs_o_pc;
|
k_cpu_addr <= regs_o_pc;
|
| Line 507... |
Line 515... |
*/
|
*/
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`NONE: // unknown k_opcode or push/pull... refetch ?
|
`NONE: // unknown k_opcode or push/pull... refetch ?
|
begin
|
begin
|
casex (k_opcode)
|
casex (k_opcode)
|
|
8'h13: state <= `SEQ_SYNC;
|
8'h39: // RTS
|
8'h39: // RTS
|
begin
|
begin
|
state <= `SEQ_PREPULL;
|
state <= `SEQ_PREPULL;
|
k_pp_regs <= 8'h80; // Pull PC (RTS)all regs
|
k_pp_regs <= 8'h80; // Pull PC (RTS)all regs
|
end
|
end
|
8'h3B: // RTI
|
|
begin
|
|
state <= `SEQ_PREPULL;
|
|
k_pp_regs <= 8'hff; // all regs
|
|
end
|
|
8'b001101x0: // PUSH S&U
|
8'b001101x0: // PUSH S&U
|
begin
|
begin
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
next_state <= `SEQ_PREPUSH;
|
next_state <= `SEQ_PREPUSH;
|
next_push_state <= `SEQ_FETCH;
|
next_push_state <= `SEQ_FETCH;
|
| Line 528... |
Line 532... |
8'b001101x1: // PULL S&U
|
8'b001101x1: // PULL S&U
|
begin
|
begin
|
next_state <= `SEQ_PREPULL;
|
next_state <= `SEQ_PREPULL;
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
end
|
end
|
|
8'h3B: // RTI
|
|
begin
|
|
state <= `SEQ_PREPULL;
|
|
k_pp_regs <= 8'hff; // all regs
|
|
end
|
default: /* we ignore unknown opcodes */
|
default: /* we ignore unknown opcodes */
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
endcase
|
endcase
|
end
|
end
|
`IMMEDIATE: // 8 or 16 bits as result decides..
|
`IMMEDIATE: // 8 or 16 bits as result decides..
|
| Line 543... |
Line 552... |
next_state <= `SEQ_GRAL_ALU;
|
next_state <= `SEQ_GRAL_ALU;
|
end
|
end
|
`INHERENT:
|
`INHERENT:
|
begin
|
begin
|
case (k_opcode)
|
case (k_opcode)
|
|
8'h3d: begin k_mul_cnt <= 1'h1; state <= `SEQ_GRAL_ALU; end // counter for mul
|
8'h3f: state <= `SEQ_SWI;
|
8'h3f: state <= `SEQ_SWI;
|
default: state <= `SEQ_GRAL_ALU;
|
default: state <= `SEQ_GRAL_ALU;
|
endcase
|
endcase
|
end
|
end
|
`DIRECT:
|
`DIRECT:
|
| Line 658... |
Line 668... |
end
|
end
|
endcase
|
endcase
|
end
|
end
|
`SEQ_GRAL_ALU:
|
`SEQ_GRAL_ALU:
|
begin
|
begin
|
|
if (!k_mul_cnt)
|
|
begin
|
state <= `SEQ_GRAL_WBACK;
|
state <= `SEQ_GRAL_WBACK;
|
k_write_dest <= 1; /* write destination on wback */
|
k_write_dest <= 1; /* write destination on wback */
|
end
|
end
|
|
else
|
|
k_mul_cnt <= 1'h0;
|
|
end
|
`SEQ_GRAL_WBACK:
|
`SEQ_GRAL_WBACK:
|
begin
|
begin
|
next_mem_state <= `SEQ_FETCH;
|
next_mem_state <= `SEQ_FETCH;
|
|
casex (k_opcode)
|
|
8'h3C: state <= `SEQ_CWAI_STACK; // CWAI
|
|
default:
|
case (dec_o_dest_reg_addr)
|
case (dec_o_dest_reg_addr)
|
`RN_MEM8: state <= `SEQ_MEM_WRITE_L;
|
`RN_MEM8: state <= `SEQ_MEM_WRITE_L;
|
`RN_MEM16: state <= `SEQ_MEM_WRITE_H;
|
`RN_MEM16: state <= `SEQ_MEM_WRITE_H;
|
default:
|
default:
|
begin
|
begin
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
k_write_post_incdec <= dec_o_ea_wpost;
|
k_write_post_incdec <= dec_o_ea_wpost;
|
end
|
end
|
endcase
|
endcase
|
|
endcase
|
|
end
|
|
`SEQ_CWAI_STACK:
|
|
begin
|
|
k_pp_regs <= 8'hff;
|
|
k_set_e <= 1;
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
|
next_push_state <= `SEQ_CWAI_WAIT; // wait for interrupts
|
|
end
|
|
`SEQ_CWAI_WAIT: /* waits for an interrupt and process it */
|
|
begin
|
|
k_forced_mem_size <= 1;
|
|
next_mem_state <= `SEQ_FETCH; // then continue fetching instructions
|
|
k_eahi <= 8'hff;
|
|
k_ealo[7:4] <= 4'hf;
|
|
if (k_nmi_req)
|
|
begin
|
|
k_reg_nmi <= 2'h0;
|
|
k_ealo[3:0] <= 4'hc;
|
|
state <= `SEQ_MEM_READ_H; // load new PC
|
|
end
|
|
else
|
|
if (k_firq_req)
|
|
begin
|
|
k_reg_firq <= 2'h0;
|
|
k_ealo[3:0] <= 4'h6;
|
|
state <= `SEQ_MEM_READ_H; // load new PC
|
|
end
|
|
else
|
|
if (k_irq_req)
|
|
begin
|
|
k_reg_irq <= 2'h0;
|
|
k_ealo[3:0] <= 4'hf8;
|
|
state <= `SEQ_MEM_READ_H; // load new PC
|
|
end
|
end
|
end
|
`SEQ_INH_ALU:
|
|
state <= `SEQ_GRAL_WBACK;
|
|
`SEQ_TFREXG:
|
`SEQ_TFREXG:
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
`SEQ_IND_READ_EA: // reads EA byte
|
`SEQ_IND_READ_EA: // reads EA byte
|
begin
|
begin
|
k_cpu_addr <= regs_o_pc;
|
k_cpu_addr <= regs_o_pc;
|
| Line 749... |
Line 800... |
begin
|
begin
|
next_state <= `SEQ_PREPUSH;
|
next_state <= `SEQ_PREPUSH;
|
if (k_pp_regs > 0)
|
if (k_pp_regs > 0)
|
begin
|
begin
|
state <= `SEQ_PUSH_WRITE_L;
|
state <= `SEQ_PUSH_WRITE_L;
|
//k_dec_su <= 1;
|
|
end
|
end
|
else
|
else
|
state <= next_push_state;
|
state <= next_push_state;
|
if (k_pp_regs[7]) begin k_pp_regs[7] <= 0; k_pp_active_reg <= 8'h80; end
|
if (k_pp_regs[7]) begin k_pp_regs[7] <= 0; k_pp_active_reg <= `RN_PC; end
|
else
|
else
|
if (k_pp_regs[6]) begin k_pp_regs[6] <= 0; k_pp_active_reg <= 8'h40; end
|
if (k_pp_regs[6]) begin k_pp_regs[6] <= 0; k_pp_active_reg <= (dec_o_use_s) ? `RN_U:`RN_S; end
|
else
|
else
|
if (k_pp_regs[5]) begin k_pp_regs[5] <= 0; k_pp_active_reg <= 8'h20; end
|
if (k_pp_regs[5]) begin k_pp_regs[5] <= 0; k_pp_active_reg <= `RN_IY; end
|
else
|
else
|
if (k_pp_regs[4]) begin k_pp_regs[4] <= 0; k_pp_active_reg <= 8'h10; end
|
if (k_pp_regs[4]) begin k_pp_regs[4] <= 0; k_pp_active_reg <= `RN_IX; end
|
else
|
else
|
if (k_pp_regs[3]) begin k_pp_regs[3] <= 0; k_pp_active_reg <= 8'h08; end
|
if (k_pp_regs[3]) begin k_pp_regs[3] <= 0; k_pp_active_reg <= `RN_DP; end
|
else
|
else
|
if (k_pp_regs[2]) begin k_pp_regs[2] <= 0; k_pp_active_reg <= 8'h04; end
|
if (k_pp_regs[2]) begin k_pp_regs[2] <= 0; k_pp_active_reg <= `RN_ACCB; end
|
else
|
else
|
if (k_pp_regs[1]) begin k_pp_regs[1] <= 0; k_pp_active_reg <= 8'h02; end
|
if (k_pp_regs[1]) begin k_pp_regs[1] <= 0; k_pp_active_reg <= `RN_ACCA; end
|
else
|
else
|
if (k_pp_regs[0]) begin k_pp_regs[0] <= 0; k_pp_active_reg <= 8'h01; end
|
if (k_pp_regs[0]) begin k_pp_regs[0] <= 0; k_pp_active_reg <= `RN_CC; end
|
end
|
end
|
`SEQ_PREPULL:
|
`SEQ_PREPULL:
|
begin
|
begin
|
if (k_pp_regs != 8'h0)
|
if (k_pp_regs != 8'h0)
|
begin
|
begin
|
k_mem_dest <= `MEMDEST_MH;
|
k_mem_dest <= `MEMDEST_MH;
|
next_mem_state <= `SEQ_PREPULL;
|
next_mem_state <= `SEQ_PREPULL;
|
end
|
end
|
else
|
else
|
state <= `SEQ_FETCH; // end of sequence
|
state <= `SEQ_FETCH; // end of sequence
|
if (k_pp_regs[0]) begin k_pp_active_reg <= 8'h01; k_pp_regs[0] <= 0; state <= `SEQ_MEM_READ_L; end
|
if (k_pp_regs[0]) begin k_pp_active_reg <= `RN_CC; k_pp_regs[0] <= 0; state <= `SEQ_MEM_READ_L; end
|
else
|
else
|
if (k_pp_regs[1]) begin k_pp_active_reg <= 8'h02; k_pp_regs[1] <= 0; state <= `SEQ_MEM_READ_L; end
|
if (k_pp_regs[1]) begin k_pp_active_reg <= `RN_ACCA; k_pp_regs[1] <= 0; state <= `SEQ_MEM_READ_L; end
|
else
|
else
|
if (k_pp_regs[2]) begin k_pp_active_reg <= 8'h04; k_pp_regs[2] <= 0; state <= `SEQ_MEM_READ_L; end
|
if (k_pp_regs[2]) begin k_pp_active_reg <= `RN_ACCB; k_pp_regs[2] <= 0; state <= `SEQ_MEM_READ_L; end
|
else
|
else
|
if (k_pp_regs[3]) begin k_pp_active_reg <= 8'h08; k_pp_regs[3] <= 0; state <= `SEQ_MEM_READ_L; end
|
if (k_pp_regs[3]) begin k_pp_active_reg <= `RN_DP; k_pp_regs[3] <= 0; state <= `SEQ_MEM_READ_L; end
|
else
|
else
|
if (k_pp_regs[4]) begin k_pp_active_reg <= 8'h10; k_pp_regs[4] <= 0; state <= `SEQ_MEM_READ_H;end
|
if (k_pp_regs[4]) begin k_pp_active_reg <= `RN_IX; k_pp_regs[4] <= 0; state <= `SEQ_MEM_READ_H;end
|
else
|
else
|
if (k_pp_regs[5]) begin k_pp_active_reg <= 8'h20; k_pp_regs[5] <= 0; state <= `SEQ_MEM_READ_H;end
|
if (k_pp_regs[5]) begin k_pp_active_reg <= `RN_IY; k_pp_regs[5] <= 0; state <= `SEQ_MEM_READ_H;end
|
else
|
else
|
if (k_pp_regs[6]) begin k_pp_active_reg <= 8'h40; k_pp_regs[6] <= 0; state <= `SEQ_MEM_READ_H; end
|
if (k_pp_regs[6]) begin k_pp_active_reg <= (dec_o_use_s) ? `RN_U:`RN_S; k_pp_regs[6] <= 0; state <= `SEQ_MEM_READ_H; end
|
else
|
else
|
if (k_pp_regs[7]) begin k_pp_active_reg <= 8'h80; k_pp_regs[7] <= 0; state <= `SEQ_MEM_READ_H; end
|
if (k_pp_regs[7]) begin k_pp_active_reg <= `RN_PC; k_pp_regs[7] <= 0; state <= `SEQ_MEM_READ_H; end
|
end
|
end
|
`SEQ_PUSH_WRITE_L: // first low byte push
|
`SEQ_PUSH_WRITE_L: // first low byte push
|
begin
|
begin
|
k_cpu_data_o <= regs_o_left_path_data[7:0];
|
k_cpu_data_o <= regs_o_left_path_data[7:0];
|
state <= `SEQ_PUSH_WRITE_L_1;
|
state <= `SEQ_PUSH_WRITE_L_1;
|
| Line 804... |
Line 854... |
k_cpu_addr <= regs_o_su - 16'h1;
|
k_cpu_addr <= regs_o_su - 16'h1;
|
k_dec_su <= 1;
|
k_dec_su <= 1;
|
end
|
end
|
`SEQ_PUSH_WRITE_L_1:
|
`SEQ_PUSH_WRITE_L_1:
|
begin
|
begin
|
if (k_pp_active_reg[7:4] > 0)
|
if (k_pp_active_reg < `RN_ACCA)
|
state <= `SEQ_PUSH_WRITE_H;
|
state <= `SEQ_PUSH_WRITE_H;
|
else
|
else
|
if (k_pp_regs[3:0] > 0)
|
if (k_pp_regs[3:0] > 0)
|
state <= `SEQ_PREPUSH;
|
state <= `SEQ_PREPUSH;
|
else
|
else
|
| Line 818... |
Line 868... |
`SEQ_PUSH_WRITE_H: // reads high byte
|
`SEQ_PUSH_WRITE_H: // reads high byte
|
begin
|
begin
|
k_cpu_data_o <= regs_o_left_path_data[15:8];
|
k_cpu_data_o <= regs_o_left_path_data[15:8];
|
state <= `SEQ_PUSH_WRITE_H_1;
|
state <= `SEQ_PUSH_WRITE_H_1;
|
k_cpu_we <= 1; // write
|
k_cpu_we <= 1; // write
|
if (k_pp_active_reg[3:0] > 0)
|
if (k_pp_active_reg >= `RN_ACCA)
|
k_cpu_addr <= regs_o_su;
|
k_cpu_addr <= regs_o_su; // address for 8 bit register
|
k_dec_su <= 1; // decrement stack pointer
|
k_dec_su <= 1; // decrement stack pointer
|
end
|
end
|
`SEQ_PUSH_WRITE_H_1:
|
`SEQ_PUSH_WRITE_H_1:
|
begin
|
begin
|
if (next_state == `SEQ_JMP_LOAD_PC)
|
if (next_state == `SEQ_JMP_LOAD_PC)
|
| Line 878... |
Line 928... |
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`NONE: begin k_cpu_addr <= regs_o_su; k_inc_su <= 1; end // pull, rts, rti
|
`NONE: begin k_cpu_addr <= regs_o_su; k_inc_su <= 1; end // pull, rts, rti
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
endcase
|
endcase
|
if (k_forced_mem_size | dec_o_source_size | (k_pp_active_reg[7:4] != 0))
|
if (k_forced_mem_size | dec_o_source_size | (k_pp_active_reg < `RN_ACCA))
|
state <= `SEQ_MEM_READ_H_1;
|
state <= `SEQ_MEM_READ_H_1;
|
else
|
else
|
state <= `SEQ_MEM_READ_L_1;
|
state <= `SEQ_MEM_READ_L_1;
|
k_forced_mem_size <= 0; // used for vector fetch
|
k_forced_mem_size <= 0; // used for vector fetch
|
end
|
end
|
| Line 971... |
Line 1021... |
k_cpu_we = 0;
|
k_cpu_we = 0;
|
k_mem_dest = 0;
|
k_mem_dest = 0;
|
k_new_pc = 16'hffff;
|
k_new_pc = 16'hffff;
|
k_write_tfr = 0;
|
k_write_tfr = 0;
|
k_write_exg = 0;
|
k_write_exg = 0;
|
|
k_mul_cnt = 0;
|
end
|
end
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
