| Line 121... |
Line 121... |
.set_e(k_set_e),
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.set_e(k_set_e),
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.clear_e(k_clear_e),
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.clear_e(k_clear_e),
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.CCR_o(regs_o_CCR),
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.CCR_o(regs_o_CCR),
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.path_left_data(regs_o_left_path_data),
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.path_left_data(regs_o_left_path_data),
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.path_right_data(regs_o_right_path_data),
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.path_right_data(regs_o_right_path_data),
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.eamem_addr(regs_o_eamem_addr),
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.eamem_addr_o(regs_o_eamem_addr),
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.reg_pc(regs_o_pc),
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.reg_pc(regs_o_pc),
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.reg_dp(regs_o_dp),
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.reg_dp(regs_o_dp),
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.reg_su(regs_o_su)
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.reg_su(regs_o_su)
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);
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);
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|
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decode_regs dec_regs(
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decode_regs dec_regs(
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.cpu_clk(cpu_clk),
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.opcode(k_opcode),
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.opcode(k_opcode),
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.postbyte0(k_postbyte),
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.postbyte0(k_postbyte),
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.page2_valid(k_p2_valid),
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.page2_valid(k_p2_valid),
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.page3_valid(k_p3_valid),
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.page3_valid(k_p3_valid),
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.path_left_addr(dec_o_left_path_addr),
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.path_left_addr_o(dec_o_left_path_addr),
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.path_right_addr(dec_o_right_path_addr),
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.path_right_addr_o(dec_o_right_path_addr),
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.dest_reg(dec_o_dest_reg_addr),
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.dest_reg_o(dec_o_dest_reg_addr),
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.write_dest(dec_o_wdest),
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.write_dest(dec_o_wdest),
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.source_size(dec_o_source_size),
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.source_size(dec_o_source_size),
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.result_size(dec_o_alu_size)
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.result_size(dec_o_alu_size)
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);
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);
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|
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| Line 806... |
Line 807... |
begin
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begin
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state <= `SEQ_FETCH;
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state <= `SEQ_FETCH;
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end
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end
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`SEQ_JSR_PUSH:
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`SEQ_JSR_PUSH:
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begin
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begin
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k_pp_active_reg <= 8'h80; // push PC
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k_pp_active_reg <= `RN_PC; // push PC
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state <= `SEQ_PUSH_WRITE_L;
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state <= `SEQ_PUSH_WRITE_L;
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next_state <= `SEQ_JMP_LOAD_PC;
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next_state <= `SEQ_JMP_LOAD_PC;
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end
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end
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`SEQ_PREPUSH:
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`SEQ_PREPUSH:
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begin
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begin
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| Line 846... |
Line 847... |
end
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end
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else
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else
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state <= `SEQ_FETCH; // end of sequence
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state <= `SEQ_FETCH; // end of sequence
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if (k_pp_regs[0]) begin k_pp_active_reg <= `RN_CC; k_pp_regs[0] <= 0; state <= `SEQ_MEM_READ_L; end
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if (k_pp_regs[0]) begin k_pp_active_reg <= `RN_CC; k_pp_regs[0] <= 0; state <= `SEQ_MEM_READ_L; end
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else
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else
|
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if ((k_opcode == 8'h3B) && (!`FLAGE)) // not all registers have to be pulled
|
|
begin
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|
k_pp_active_reg <= `RN_PC; k_pp_regs <= 0; state <= `SEQ_MEM_READ_H;
|
|
end
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else
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if (k_pp_regs[1]) begin k_pp_active_reg <= `RN_ACCA; k_pp_regs[1] <= 0; state <= `SEQ_MEM_READ_L; end
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if (k_pp_regs[1]) begin k_pp_active_reg <= `RN_ACCA; k_pp_regs[1] <= 0; state <= `SEQ_MEM_READ_L; end
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else
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else
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if (k_pp_regs[2]) begin k_pp_active_reg <= `RN_ACCB; k_pp_regs[2] <= 0; state <= `SEQ_MEM_READ_L; end
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if (k_pp_regs[2]) begin k_pp_active_reg <= `RN_ACCB; k_pp_regs[2] <= 0; state <= `SEQ_MEM_READ_L; end
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else
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else
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if (k_pp_regs[3]) begin k_pp_active_reg <= `RN_DP; k_pp_regs[3] <= 0; state <= `SEQ_MEM_READ_L; end
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if (k_pp_regs[3]) begin k_pp_active_reg <= `RN_DP; k_pp_regs[3] <= 0; state <= `SEQ_MEM_READ_L; end
|
