| Line 28... |
Line 28... |
wire [3:0] ccr16_out;
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wire [3:0] ccr16_out;
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wire [15:0] q16_mul;
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wire [15:0] q16_mul;
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reg [15:0] ra_in, rb_in;
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reg [15:0] ra_in, rb_in;
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reg [4:0] rop_in;
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reg [4:0] rop_in;
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mul8x8 mulu(clk_in, a_in[7:0], b_in[7:0], q16_mul);
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mul8x8 mulu(clk_in, a_in[7:0], b_in[7:0], q16_mul);
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alu8 alu8(clk_in, ra_in[7:0], rb_in[7:0], CCR, rop_in, q8_out, ccr8_out);
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alu8 alu8(clk_in, ra_in[7:0], rb_in[7:0], CCR, rop_in, q8_out, ccr8_out);
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alu16 alu16(clk_in, ra_in, rb_in, CCR, rop_in, q16_mul, q16_out, ccr16_out);
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alu16 alu16(clk_in, ra_in, rb_in, CCR, rop_in, q16_mul, q16_out, ccr16_out);
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always @(posedge clk_in)
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always @(posedge clk_in)
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begin
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begin
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ra_in <= a_in;
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ra_in <= a_in;
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rb_in <= b_in;
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rb_in <= b_in;
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rop_in <= opcode_in;
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rop_in <= opcode_in;
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| Line 242... |
Line 240... |
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wire [7:0] logic_q, arith_q, shift_q;
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wire [7:0] logic_q, arith_q, shift_q;
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wire arith_c, arith_v, arith_h;
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wire arith_c, arith_v, arith_h;
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wire shift_c, shift_v;
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wire shift_c, shift_v;
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reg [7:0] alu8_b_in;
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always @(*)
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begin
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alu8_b_in = b_in[7:0];
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case (opcode_in)
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`INC, `DEC: alu8_b_in = 8'h01;
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`CLR: alu8_b_in = 8'h0;
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endcase
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end
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logic8 l8(a_in, b_in, opcode_in[1:0], logic_q);
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logic8 l8(a_in, b_in, opcode_in[1:0], logic_q);
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arith8 a8(a_in, b_in, c_in, h_in, opcode_in[1:0], arith_q, arith_c, arith_v, arith_h);
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arith8 a8(a_in, alu8_b_in, c_in, h_in, opcode_in[1:0], arith_q, arith_c, arith_v, arith_h);
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shift8 s8(a_in, b_in, c_in, v_in, opcode_in[2:0], shift_q, shift_c, shift_v);
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shift8 s8(a_in, b_in, c_in, v_in, opcode_in[2:0], shift_q, shift_c, shift_v);
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// DAA
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// DAA
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assign daa_p0_r = ((a_in[3:0] > 4'h9) | h_in ) ? a_in[7:0] + 8'h6:a_in[7:0];
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assign daa_p0_r = ((a_in[3:0] > 4'h9) | h_in ) ? a_in[7:0] + 8'h6:a_in[7:0];
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assign { cdaa8_r, daa8h_r } = ((daa_p0_r[7:4] > 9) || (c_in == 1'b1)) ? { 1'b0, daa_p0_r[7:4] } + 5'h6:{ 1'b0, daa_p0_r[7:4] };
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assign { cdaa8_r, daa8h_r } = ((daa_p0_r[7:4] > 9) || (c_in == 1'b1)) ? { 1'b0, daa_p0_r[7:4] } + 5'h6:{ 1'b0, daa_p0_r[7:4] };
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| Line 295... |
Line 304... |
`AND, `OR, `EOR, `LD:
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`AND, `OR, `EOR, `LD:
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begin
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begin
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q8 = logic_q;
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q8 = logic_q;
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v8 = 1'b0;
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v8 = 1'b0;
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end
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end
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`TST:
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begin
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q8 = a_in;
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v8 = 1'b0;
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end
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`DAA:
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`DAA:
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begin // V is undefined, so we don't touch it
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begin // V is undefined, so we don't touch it
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q8 = { daa8h_r, daa_p0_r[3:0] };
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q8 = { daa8h_r, daa_p0_r[3:0] };
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c8 = cdaa8_r;
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c8 = cdaa8_r;
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end
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end
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