| Line 41... |
Line 41... |
casex (postbyte0) // right arm
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casex (postbyte0) // right arm
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8'h83, 8'h8c, 8'h8e, 8'hce: path_right_addr = `RN_IMM16;
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8'h83, 8'h8c, 8'h8e, 8'hce: path_right_addr = `RN_IMM16;
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8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
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8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
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8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
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8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
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8'h9e, 8'hae, 8'hbe: path_right_addr = `RN_MEM16;
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8'h9e, 8'hae, 8'hbe: path_right_addr = `RN_MEM16;
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8'h9f, 8'haf, 8'hbf: path_right_addr = `RN_MEM16;
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8'h9f, 8'haf, 8'hbf: path_right_addr = `RN_MEM16; // STY
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8'hde, 8'hee, 8'hfe: path_right_addr = `RN_MEM16; // lds
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8'hde, 8'hee, 8'hfe: path_right_addr = `RN_MEM16; // lds
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endcase
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endcase
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casex(postbyte0) // dest
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casex(postbyte0) // dest
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8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpu/cmpd
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8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpd
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8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmpy/cmps
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8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmpy
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8'h8e, 8'h9e, 8'hae, 8'hbe: dest_reg = `RN_IY;
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8'h8e, 8'h9e, 8'hae, 8'hbe: dest_reg = `RN_IY; // LDY
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8'hce, 8'hde, 8'hee, 8'hfe: dest_reg = `RN_S; // LDS
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8'hce, 8'hde, 8'hee, 8'hfe: dest_reg = `RN_S; // LDS
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8'h8f, 8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16; // STY
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8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16; // STY
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8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16; // STS
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8'hdf, 8'hef, 8'hff: dest_reg = `RN_MEM16; // STS
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endcase
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endcase
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end
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end
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if (page3_valid)
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if (page3_valid)
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begin
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begin
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casex(postbyte0)
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casex(postbyte0)
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8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_U; // CMPU
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8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_U; // CMPU
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8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_S; // CMPS
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8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_S; // CMPS
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endcase
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endcase
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casex (postbyte0) // right arm
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casex (postbyte0) // right arm
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8'h83, 8'h8c: path_right_addr = `RN_IMM16;
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8'h83, 8'h8c: path_right_addr = `RN_IMM16; // CMPU, CMPS
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8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
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8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16; // CMPU
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8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
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8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16; // CMPS
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endcase
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endcase
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casex(postbyte0) // dest
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casex(postbyte0) // dest
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8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpu
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8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpu
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8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmps
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8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmps
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endcase
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endcase
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| Line 86... |
Line 86... |
8'h6x:
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8'h6x:
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case (opcode[3:0])
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case (opcode[3:0])
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4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
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4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
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default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
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default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
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endcase
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endcase
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8'h4x, 8'h8x, 8'h9x, 8'hax, 8'hbx:
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8'h8x, 8'h9x, 8'hax, 8'hbx:
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case (opcode[3:0])
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case (opcode[3:0]) // default A->A
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4'h1, 4'h5: path_left_addr = `RN_ACCA; // CMP, BIT
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4'h1, 4'h5: path_left_addr = `RN_ACCA; // CMP, BIT
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4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end
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4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end // sta
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4'hc: path_left_addr = `RN_IX; // cmpx
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4'hc: path_left_addr = `RN_IX; // cmpx
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4'he, 4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end
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4'hd: begin end // nothing active, jsr
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4'hd: begin end // nothing active, jsr
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4'he: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end // ldx
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4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_MEM16; end // stx
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default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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endcase
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endcase
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8'h5x, 8'hcx, 8'hdx, 8'hex, 8'hfx:
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8'hcx, 8'hdx, 8'hex, 8'hfx:
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case (opcode[3:0])
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case (opcode[3:0])
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4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT
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4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT
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4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem
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4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem
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4'he: begin path_left_addr = `RN_U; dest_reg = `RN_IX; end
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4'hd: begin path_left_addr = `RN_ACCD; end // LDD
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4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end
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4'he: begin path_left_addr = `RN_U; dest_reg = `RN_U; end // LDU
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4'hd: begin path_left_addr = `RN_ACCD; end
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4'hf: begin path_left_addr = `RN_U; dest_reg = `RN_MEM16; end // STU
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default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
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default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
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endcase
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endcase
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endcase
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endcase
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casex (opcode) // right arm
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casex (opcode) // right arm
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// 8x and Cx
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// 8x and Cx
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8'b1x00_000x, 8'b1x00_0010: path_right_addr = `RN_IMM8;
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8'b1x00_000x, 8'b1x00_0010: path_right_addr = `RN_IMM8; // sub, cmp, scb
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8'b1x00_0011, 8'b1x00_11x0, 8'b1x00_1111: path_right_addr = `RN_IMM16;
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8'b1x00_0011, 8'b1x00_11x0: path_right_addr = `RN_IMM16; // cmpd, cmpx, ldx
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8'b1x00_010x, 8'b1x00_0110,
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8'b1x00_010x, 8'b1x00_0110, 8'b1x00_10xx: path_right_addr = `RN_IMM8;
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8'b1x00_10xx: path_right_addr = `RN_IMM8;
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// 9, A, B, D, E, F
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// 9, A, B, D, E, F
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8'b1x01_000x, 8'b1x01_0010: path_right_addr = `RN_MEM8;
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8'b1x01_000x, 8'b1x01_0010: path_right_addr = `RN_MEM8;
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8'b1x01_0011, 8'b1x01_11x0, 8'b1x01_1111: path_right_addr = `RN_MEM16;
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8'b1x01_0011, 8'b1x01_11x0: path_right_addr = `RN_MEM16; // cmpd, cmpx, ldx
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8'b1x01_010x, 8'b1x01_0110,
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8'b1x01_010x, 8'b1x01_0110, 8'b1x01_10xx: path_right_addr = `RN_MEM8;
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8'b1x01_10xx: path_right_addr = `RN_MEM8;
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8'b1x1x_000x, 8'b1x1x_0010: path_right_addr = `RN_MEM8;
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8'b1x1x_000x, 8'b1x1x_0010: path_right_addr = `RN_MEM8;
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8'b1x1x_0011, 8'b1x1x_11x0, 8'b1x1x_1111: path_right_addr = `RN_MEM16;
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8'b1x1x_0011, 8'b1x1x_11x0: path_right_addr = `RN_MEM16;
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8'b1x1x_010x, 8'b1x1x_0110,
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8'b1x1x_010x, 8'b1x1x_0110, 8'b1x1x_10xx: path_right_addr = `RN_MEM8;
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8'b1x1x_10xx: path_right_addr = `RN_MEM8;
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endcase
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endcase
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end
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end
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always @(posedge cpu_clk)
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always @(posedge cpu_clk)
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begin
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begin
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path_right_addr_o <= path_right_addr;
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path_right_addr_o <= path_right_addr;
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| Line 205... |
Line 203... |
8'b1xxx0110: optype = `OP_LD;
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8'b1xxx0110: optype = `OP_LD;
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8'b1xxx0111: optype = `OP_ST;
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8'b1xxx0111: optype = `OP_ST;
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8'b11xx1100: optype = `OP_LD; // LDD
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8'b11xx1100: optype = `OP_LD; // LDD
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8'b10xx1101: begin optype = `OP_JSR; end// bsr & jsr
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8'b10xx1101: begin optype = `OP_JSR; end// bsr & jsr
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8'b1xxx1110: optype = `OP_LD; // LDX, LDU
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8'b1xxx1110: optype = `OP_LD; // LDX, LDU
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8'b1xxx1111, 8'b1xxx1101: optype = `OP_ST;
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8'b1xxx1111, 8'b11xx1101: optype = `OP_ST;
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endcase
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endcase
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if (page2_valid == 1'b1)
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if (page2_valid == 1'b1)
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begin
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begin
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casex(postbyte0)
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casex(postbyte0)
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8'h1x: mode = `REL16;
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8'h1x: mode = `REL16;
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