| Line 7... |
Line 7... |
module regblock(
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module regblock(
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input wire clk_in,
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input wire clk_in,
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input wire [3:0] path_left_addr,
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input wire [3:0] path_left_addr,
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input wire [3:0] path_right_addr,
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input wire [3:0] path_right_addr,
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input wire [3:0] write_reg_addr,
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input wire [3:0] write_reg_addr,
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input wire [3:0] exg_dest_r,
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input wire [7:0] eapostbyte, // effective address post byte
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input wire [7:0] eapostbyte, // effective address post byte
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input wire [15:0] offset16, // up to 16 bit offset for effective address calculation
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input wire [15:0] offset16, // up to 16 bit offset for effective address calculation
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input wire write_reg,
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input wire write_reg,
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input wire write_post,
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input wire write_post,
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input wire write_pc,
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input wire write_pc,
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input wire write_tfr,
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input wire write_exg,
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input wire inc_pc,
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input wire inc_pc,
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input wire inc_su, /* increments S or U */
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input wire inc_su, /* increments S or U */
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input wire dec_su, /* decrements s or u */
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input wire dec_su, /* decrements s or u */
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input wire use_s, /* increments S or U */
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input wire use_s, /* increments S or U */
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input wire [15:0] data_w,
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input wire [15:0] data_w,
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| Line 55... |
Line 58... |
assign reg_su = (use_s) ? SS:SU; /* stack pointer */
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assign reg_su = (use_s) ? SS:SU; /* stack pointer */
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// left path output, always 16 bits
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// left path output, always 16 bits
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always @(*)
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always @(*)
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begin
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begin
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case (path_left_addr)
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case (path_left_addr)
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`RN_ACCA: path_left_data = { 8'h0, ACCA };
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`RN_ACCA: path_left_data = { 8'hff, ACCA };
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`RN_ACCB: path_left_data = { 8'h0, ACCB };
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`RN_ACCB: path_left_data = { 8'hff, ACCB };
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`RN_ACCD: path_left_data = `ACCD;
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`RN_ACCD: path_left_data = `ACCD;
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`RN_IX: path_left_data = IX;
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`RN_IX: path_left_data = IX;
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`RN_IY: path_left_data = IY;
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`RN_IY: path_left_data = IY;
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`RN_U: path_left_data = SU;
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`RN_U: path_left_data = SU;
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`RN_S: path_left_data = SS;
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`RN_S: path_left_data = SS;
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`RN_PC: path_left_data = PC;
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`RN_PC: path_left_data = PC;
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`RN_DP: path_left_data = { 8'h0, DP };
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`RN_DP: path_left_data = { DP, DP };
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`RN_CC: path_left_data = { `CCR, `CCR };
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default:
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default:
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path_left_data = 16'hBEEF;
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path_left_data = 16'hFFFF;
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endcase
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endcase
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end
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end
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// right path output, always 16 bits
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// right path output, always 16 bits
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always @(*)
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always @(*)
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begin
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begin
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case (path_right_addr)
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case (path_right_addr)
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`RN_ACCA: path_right_data = { 8'h0, ACCA };
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`RN_ACCA: path_right_data = { 8'hff, ACCA };
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`RN_ACCB: path_right_data = { 8'h0, ACCB };
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`RN_ACCB: path_right_data = { 8'hff, ACCB };
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`RN_ACCD: path_right_data = `ACCD;
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`RN_ACCD: path_right_data = `ACCD;
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`RN_IX: path_right_data = IX;
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`RN_IX: path_right_data = IX;
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`RN_IY: path_right_data = IY;
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`RN_IY: path_right_data = IY;
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`RN_U: path_right_data = SU;
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`RN_U: path_right_data = SU;
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`RN_S: path_right_data = SS;
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`RN_S: path_right_data = SS;
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`RN_DP: path_right_data = { 8'h0, DP };
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`RN_DP: path_right_data = { DP, DP };
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`RN_CC: path_right_data = { `CCR, `CCR };
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default:
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default:
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path_right_data = 16'hBEEF;
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path_right_data = 16'hFFFF;
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endcase
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endcase
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end
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end
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always @(*)
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always @(*)
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begin
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begin
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| Line 163... |
Line 168... |
8'b1xx_x_1101: // n,PC
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8'b1xx_x_1101: // n,PC
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eamem_addr = PC + offset16;
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eamem_addr = PC + offset16;
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endcase
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endcase
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end
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end
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wire [15:0] left;
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assign left = (write_tfr | write_exg) ? path_left_data:data_w;
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wire [15:0] new_su, old_su;
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assign old_su = (use_s) ? SS:SU;
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assign new_su = (inc_su) ? old_su + 16'h1:(dec_su) ? old_su - 16'h1:old_su;
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always @(posedge clk_in)
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always @(posedge clk_in)
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begin
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begin
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if (write_reg)
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if (write_exg)
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case (exg_dest_r)
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0: `ACCD <= path_right_data;
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1: IX <= path_right_data;
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2: IY <= path_right_data;
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3: SU <= path_right_data;
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4: SS <= path_right_data;
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5: PC <= path_right_data;
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8: ACCA <= path_right_data[7:0];
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9: ACCB <= path_right_data[7:0];
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10: `CCR <= path_right_data[7:0];
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11: DP <= path_right_data[7:0];
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endcase
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if (write_tfr | write_exg | write_reg)
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case (write_reg_addr)
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case (write_reg_addr)
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0: `ACCD <= data_w;
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0: `ACCD <= left;
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1: IX <= data_w;
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1: IX <= left;
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2: IY <= data_w;
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2: IY <= left;
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3: SU <= data_w;
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3: SU <= left;
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4: SS <= data_w;
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4: SS <= left;
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5: PC <= data_w;
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5: PC <= left;
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8: ACCA <= data_w[7:0];
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8: ACCA <= left[7:0];
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9: ACCB <= data_w[7:0];
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9: ACCB <= left[7:0];
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10: `CCR <= data_w[7:0];
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10: `CCR <= left[7:0];
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11: DP <= data_w[7:0];
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11: DP <= left[7:0];
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endcase
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endcase
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if (write_post) // write back predecrement/postincremented values
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if (write_post) // write back predecrement/postincremented values
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begin
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begin
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case (eapostbyte[6:5])
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case (eapostbyte[6:5])
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2'b00: IX <= ea_reg_post;
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2'b00: IX <= ea_reg_post;
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| Line 191... |
Line 218... |
end
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end
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if (write_flags)
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if (write_flags)
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begin
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begin
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`CCR <= CCR_in;
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`CCR <= CCR_in;
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end
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end
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if (set_e)
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if (set_e) eflag <= 1;
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eflag <= 1;
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if (clear_e) eflag <= 0;
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if (clear_e)
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eflag <= 0;
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if (write_pc) PC <= new_pc;
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if (write_pc) PC <= new_pc;
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if (inc_pc) PC <= PC + 16'h1;
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if (inc_pc) PC <= PC + 16'h1;
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if (inc_su)
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if (use_s) SS <= SS + 16'h1;
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if (inc_su | dec_su)
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else SU <= SU + 16'h1;
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begin
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if (dec_su)
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if (use_s) SS <= new_su;
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if (use_s) SS <= SS - 16'h1;
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else SU <= new_su;
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else SU <= SU - 16'h1;
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end
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/*
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if (inc_su)
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if (use_s) SS <= SS + 16'h1;
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else SU <= SU + 16'h1;
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if (dec_su)
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if (use_s) SS <= SS - 16'h1;
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else SU <= SU - 16'h1;
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*/
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end
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end
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`ifdef SIMULATION
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`ifdef SIMULATION
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initial
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initial
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begin
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begin
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