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https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
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| Rev 5 |
Rev 6 |
| Line 172... |
Line 172... |
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wire [15:0] left;
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wire [15:0] left;
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assign left = (write_tfr | write_exg) ? path_left_data:data_w;
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assign left = (write_tfr | write_exg) ? path_left_data:data_w;
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wire [15:0] new_su, old_su;
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//wire [15:0] new_su, old_su;
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assign old_su = (use_s) ? SS:SU;
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//assign old_su = (use_s) ? SS:SU;
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assign new_su = (inc_su) ? old_su + 16'h1:(dec_su) ? old_su - 16'h1:old_su;
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//assign new_su = (inc_su) ? old_su + 16'h1:(dec_su) ? old_su - 16'h1:old_su;
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always @(posedge clk_in)
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always @(posedge clk_in)
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begin
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begin
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if (write_exg)
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if (write_exg)
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case (exg_dest_r)
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case (exg_dest_r)
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| Line 222... |
Line 222... |
end
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end
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if (set_e) eflag <= 1;
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if (set_e) eflag <= 1;
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if (clear_e) eflag <= 0;
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if (clear_e) eflag <= 0;
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if (write_pc) PC <= new_pc;
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if (write_pc) PC <= new_pc;
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if (inc_pc) PC <= PC + 16'h1;
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if (inc_pc) PC <= PC + 16'h1;
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if (inc_su | dec_su)
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begin
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if (use_s) SS <= new_su;
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else SU <= new_su;
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end
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/*
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/*
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if (inc_su)
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if (inc_su | dec_su)
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if (use_s) SS <= SS + 16'h1;
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begin
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else SU <= SU + 16'h1;
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if (use_s) SS <= new_su;
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if (dec_su)
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else SU <= new_su;
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if (use_s) SS <= SS - 16'h1;
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end
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else SU <= SU - 16'h1;
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*/
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*/
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if (inc_su)
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if (use_s) SS <= SS + 16'h1;
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else SU <= SU + 16'h1;
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if (dec_su)
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if (use_s) SS <= SS - 16'h1;
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else SU <= SU - 16'h1;
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end
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end
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`ifdef SIMULATION
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`ifdef SIMULATION
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initial
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initial
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begin
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begin
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