| Line 1... |
Line 1... |
[*]
|
[*]
|
[*] GTKWave Analyzer v3.3.48 (w)1999-2013 BSI
|
[*] GTKWave Analyzer v3.3.48 (w)1999-2013 BSI
|
[*] Wed Jul 02 10:38:28 2014
|
[*] Tue Jul 08 07:11:08 2014
|
[*]
|
[*]
|
[dumpfile] "C:\02_Elektronik\020_V6809\trunk\sim\dump.vcd"
|
[dumpfile] "C:\02_Elektronik\020_V6809\trunk\sim\dump.vcd"
|
[dumpfile_mtime] "Wed Jul 02 10:37:24 2014"
|
[dumpfile_mtime] "Mon Jul 07 03:55:38 2014"
|
[dumpfile_size] 142348
|
[dumpfile_size] 3515157
|
[savefile] "C:\02_Elektronik\020_V6809\trunk\sim\debug_ea.gtkw"
|
[savefile] "C:\02_Elektronik\020_V6809\trunk\sim\debug_ea.gtkw"
|
[timestart] 922
|
[timestart] 110525
|
[size] 1920 1018
|
[size] 1920 1018
|
[pos] -1 -1
|
[pos] -1 -1
|
*-6.000000 775 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
*-6.000000 110405 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
[treeopen] tb.
|
[treeopen] tb.
|
[treeopen] tb.cpu.
|
[treeopen] tb.cpu.
|
|
[treeopen] tb.cpu.alu.
|
|
[treeopen] tb.cpu.alu.alu16.
|
[sst_width] 219
|
[sst_width] 219
|
[signals_width] 334
|
[signals_width] 334
|
[sst_expanded] 1
|
[sst_expanded] 1
|
[sst_vpaned_height] 634
|
[sst_vpaned_height] 443
|
@28
|
@28
|
tb.cpu.cpu_clk
|
tb.cpu.cpu_clk
|
@22
|
@22
|
tb.cpu.state[5:0]
|
tb.cpu.state[5:0]
|
tb.cpu.cpu_addr_o[15:0]
|
tb.cpu.cpu_addr_o[15:0]
|
| Line 38... |
Line 40... |
tb.cpu.k_new_pc[15:0]
|
tb.cpu.k_new_pc[15:0]
|
tb.cpu.datamux_o_alu_in_left_path_addr[3:0]
|
tb.cpu.datamux_o_alu_in_left_path_addr[3:0]
|
tb.cpu.datamux_o_alu_in_left_path_data[15:0]
|
tb.cpu.datamux_o_alu_in_left_path_data[15:0]
|
tb.cpu.datamux_o_alu_in_right_path_data[15:0]
|
tb.cpu.datamux_o_alu_in_right_path_data[15:0]
|
tb.cpu.datamux_o_dest_reg_addr[3:0]
|
tb.cpu.datamux_o_dest_reg_addr[3:0]
|
@23
|
|
tb.cpu.dec_o_dest_reg_addr[3:0]
|
tb.cpu.dec_o_dest_reg_addr[3:0]
|
@22
|
|
tb.cpu.dec_o_left_path_addr[3:0]
|
tb.cpu.dec_o_left_path_addr[3:0]
|
tb.cpu.dec_o_right_path_addr[3:0]
|
tb.cpu.dec_o_right_path_addr[3:0]
|
tb.cpu.regs.ACCA[7:0]
|
tb.cpu.regs.ACCA[7:0]
|
tb.cpu.regs.ACCB[7:0]
|
tb.cpu.regs.ACCB[7:0]
|
tb.cpu.regs.IX[15:0]
|
tb.cpu.regs.IX[15:0]
|
tb.cpu.regs.IY[15:0]
|
tb.cpu.regs.IY[15:0]
|
tb.cpu.regs.SU[15:0]
|
tb.cpu.regs.SU[15:0]
|
tb.cpu.regs.PC[15:0]
|
tb.cpu.regs.PC[15:0]
|
@28
|
@28
|
tb.cpu.k_write_dest
|
tb.cpu.k_write_dest
|
|
tb.cpu.regs.write_flags
|
|
tb.cpu.k_write_pc
|
|
tb.cpu.regs.write_post
|
tb.cpu.test_cond.cond_taken
|
tb.cpu.test_cond.cond_taken
|
@22
|
@22
|
tb.cpu.test_cond.CCR[7:0]
|
tb.cpu.test_cond.CCR[7:0]
|
tb.cpu.regs.SS[15:0]
|
tb.cpu.regs.SS[15:0]
|
tb.cpu.k_pp_regs[7:0]
|
tb.cpu.k_pp_regs[7:0]
|
| Line 62... |
Line 65... |
tb.cpu.k_inc_su
|
tb.cpu.k_inc_su
|
tb.cpu.k_dec_su
|
tb.cpu.k_dec_su
|
@22
|
@22
|
tb.cpu.next_state[5:0]
|
tb.cpu.next_state[5:0]
|
tb.cpu.next_mem_state[5:0]
|
tb.cpu.next_mem_state[5:0]
|
|
tb.cpu.k_new_pc[15:0]
|
|
@28
|
|
tb.cpu.dec_op.optype[2:0]
|
|
tb.cpu.dec_op.page2_valid
|
|
tb.cpu.dec_op.page3_valid
|
|
tb.cpu.dec_op.mode[2:0]
|
|
tb.cpu.dec_o_alu_size
|
|
@22
|
|
tb.cpu.alu.alu16.a16.q_out[15:0]
|
|
tb.cpu.alu.alu16.q16[15:0]
|
|
tb.cpu.alu.alu8.CCRo[7:0]
|
|
tb.cpu.k_memhi[7:0]
|
|
tb.cpu.k_memlo[7:0]
|
[pattern_trace] 1
|
[pattern_trace] 1
|
[pattern_trace] 0
|
[pattern_trace] 0
|
