OpenCores
URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [sim/] [instructions_test.asm] - Diff between revs 6 and 7

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 6 Rev 7
Line 3... Line 3...
 
 
                ldd     #$AABB
                ldd     #$AABB
                mul
                mul
                ldx     #$1234
                ldx     #$1234
                ldy     #$5678
                ldy     #$5678
 
                exg     a,b
 
                ;exg    a,x
 
                exg     y,x
                tfr     x,u     ; 16 bit transfer
                tfr     x,u     ; 16 bit transfer
                tfr     a,u     ; high to high
                tfr     a,u     ; high to high
                tfr     b,u
                tfr     b,u
                tfr     x,a     ; gets high byte
                tfr     x,a     ; gets high byte
                tfr     x,b     ; gets low byte
                tfr     x,b     ; gets low byte
 
                bra     eatests
 
addr:           fcb     0, 4    ; an address
 
 
 
eatests:        lda     #$02
                lda     #$02
 
                ldb     #$00
                ldb     #$00
                sta     $0
                sta     $0
                stb     $1
                stb     $1
                ldx     $0      ; load saved value
                ldx     $0      ; load saved value
                ldy     #$0
                ldy     #$0
Line 41... Line 45...
                rts
                rts
 
 
test_lea:       leau    1,y
test_lea:       leau    1,y
                leay    0,y
                leay    0,y
                rts
                rts
 
 
 
_boot:          ldx     #100
 
_loop0:         ldd     #$4100
 
_loop1:         sta     b,x
 
                incb
 
                cmpb    #16
 
                bne     _loop1
 
                inca
 
_loop2:         incb
 
                bne     _loop2  ; delay
 
                cmpa    #128
 
                beq     _loop1  ; another row of characters
 
                bra     _loop0
 
 
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.