Subversion Repositories 6809_6309_compatible_core

#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013

#Build: Synplify Pro I-2013.09L , Build 064R, Nov 15 2013

#install: /usr/local/diamond/2.2_x64/synpbase

#install: C:\lscc\diamond\3.1_x64\synpbase

#OS: Linux

#OS: Windows 7 6.1

#Hostname: node01.pacito.sys

#Hostname: ALE-PC

#Sun Jun 22 08:17:19 2014

#Wed Jul 02 14:52:21 2014

Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013

Synopsys Verilog Compiler, version comp201309rc, Build 136R, built Nov 18 2013

Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"

@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v"

@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"

@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\pmi_def.v"

@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"

@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\umr_capim.v"

@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"

@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_objects.v"

@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"

@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_pipes.svh"

@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"

@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\hypermods.v"

@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"

@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v"

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"

@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v"

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"

@I:"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\defs.v"

@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"

@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v"

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"

@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v"

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"

@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v"

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"

@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v"

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"

@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v"

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"

@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v"

@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"

@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v"

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":62:7:62:12|Synthesizing module logic8

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":62:7:62:12|Synthesizing module logic8

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:7:85:12|Synthesizing module arith8

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":85:7:85:12|Synthesizing module arith8

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":158:7:158:12|Synthesizing module shift8

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":158:7:158:12|Synthesizing module shift8

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":198:7:198:10|Synthesizing module alu8

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":198:7:198:10|Synthesizing module alu8

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":320:0:320:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":320:0:320:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:12:241:13|No assignment to n8

@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":241:12:241:13|No assignment to n8

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:20:241:21|No assignment to z8

@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":241:20:241:21|No assignment to z8

@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":302:0:302:5|Pruning register regq8[7:0]

@W: CL169 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":302:0:302:5|Pruning register regq8[7:0]

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":604:7:604:12|Synthesizing module mul8x8

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":604:7:604:12|Synthesizing module mul8x8

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":129:7:129:13|Synthesizing module arith16

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":129:7:129:13|Synthesizing module arith16

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":326:7:326:11|Synthesizing module alu16

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":326:7:326:11|Synthesizing module alu16

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":412:23:412:29|No assignment to wire arith_h

@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":412:23:412:29|No assignment to wire arith_h

@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":518:0:518:5|Pruning register regq16[15:0]

@W: CL169 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":518:0:518:5|Pruning register regq16[15:0]

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":15:7:15:9|Synthesizing module alu

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":191:7:191:13|Synthesizing module calc_ea

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":191:7:191:13|Synthesizing module calc_ea

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":7:7:7:14|Synthesizing module regblock

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":9:7:9:17|Synthesizing module decode_regs

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":136:7:136:15|Synthesizing module decode_op

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":147:7:147:15|Synthesizing module decode_op

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":264:7:264:15|Synthesizing module decode_ea

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":275:7:275:15|Synthesizing module decode_ea

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":290:7:290:16|Synthesizing module decode_alu

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":301:7:301:16|Synthesizing module decode_alu

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":363:7:363:20|Synthesizing module test_condition

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":374:7:374:20|Synthesizing module test_condition

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu

@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":450:6:450:13|Ignoring system task $display

@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":455:6:455:13|Ignoring system task $display

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1099:0:1099:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":1104:0:1104:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":67:11:67:23|No assignment to wire alu8_o_result

@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":69:11:69:23|No assignment to wire alu8_o_result

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":68:11:68:20|No assignment to wire alu8_o_CCR

@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":70:11:70:20|No assignment to wire alu8_o_CCR

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit k_mem_dest[1] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Register bit k_mem_dest[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[1] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Register bit next_mem_state[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[2] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Register bit next_mem_state[2] is always 0, optimizing ...

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bits 2 to 1 of next_mem_state[5:0]

@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Pruning register bits 2 to 1 of next_mem_state[5:0]

@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bit 1 of k_mem_dest[1:0]

@W: CL260 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Pruning register bit 1 of k_mem_dest[1:0]

@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI

@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI

@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC

@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1291:7:1291:11|Synthesizing module DP8KC

@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO

@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v":8:7:8:12|Synthesizing module bios2k

@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...

@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v":8:7:8:13|Synthesizing module fontrom

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v":8:7:8:13|Synthesizing module fontrom

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":8:7:8:15|Synthesizing module textmem4k

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":8:7:8:15|Synthesizing module textmem4k

@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...

@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":2:7:2:13|Synthesizing module vgatext

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":2:7:2:13|Synthesizing module vgatext

@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":133:4:133:11|Ignoring system task $display

@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":133:4:133:11|Ignoring system task $display

@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":167:6:167:11|System task $write is not supported yet

@N: CG512 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":167:6:167:11|System task $write is not supported yet

@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":174:6:174:11|System task $write is not supported yet

@N: CG512 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":174:6:174:11|System task $write is not supported yet

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG781 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0

@W: CG781 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0

@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...

@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...

@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...

@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...

@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...

@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...

@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element redr.

@N: CL177 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Sharing sequential element redr.

@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element greenr.

@N: CL177 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Sharing sequential element greenr.

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top

@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":10:7:10:13|Synthesizing module CC3_top

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:14:37:21|No assignment to clk_div2

@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":37:14:37:21|No assignment to clk_div2

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":42:25:42:35|No assignment to wire cpu1_addr_o

@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":42:25:42:35|No assignment to wire cpu1_addr_o

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:40:43:51|No assignment to wire cpu1_data_in

@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:40:43:51|No assignment to wire cpu1_data_in

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out

@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":44:23:44:29|No assignment to wire cpu1_we

@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":44:23:44:29|No assignment to wire cpu1_we

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":44:32:44:38|No assignment to wire cpu1_oe

@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":44:32:44:38|No assignment to wire cpu1_oe

@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bits 5 to 3 of next_push_state[5:0]

@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Pruning register bits 5 to 3 of next_push_state[5:0]

@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":22:12:22:20|Input debug_clk is unused

@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":22:12:22:20|Input debug_clk is unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":367:18:367:20|Input port bits 7 to 4 of CCR[7:0] are unused

@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":378:18:378:20|Input port bits 7 to 4 of CCR[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":292:18:292:26|Input port bits 5 to 4 of postbyte0[7:0] are unused

@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":303:18:303:26|Input port bits 5 to 4 of postbyte0[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":265:18:265:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused

@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":276:18:276:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":330:18:330:20|Input port bits 7 to 4 of CCR[7:0] are unused

@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":330:18:330:20|Input port bits 7 to 4 of CCR[7:0] are unused

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]

@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...

@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...

@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]

@W: CL260 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]

@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":199:12:199:17|Input clk_in is unused

@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":199:12:199:17|Input clk_in is unused

@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":160:18:160:21|Input b_in is unused

@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":160:18:160:21|Input b_in is unused

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

# Sun Jun 22 08:17:21 2014

At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 87MB peak: 100MB)

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 800R, Built Nov 18 2013 10:58:25

Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

Product Version G-2012.09L-SP1

Product Version I-2013.09L

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_scck.rpt

@L: C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_scck.rpt

Printing clock  summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_scck.rpt" file

Printing clock  summary report in "C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_scck.rpt" file

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)

Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)

Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB)

Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB)

@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 95 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.

@W: MT529 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 95 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.

syn_allowed_resources : blockrams=26  set on top level netlist CC3_top

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 137MB)

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 146MB)

# Sun Jun 22 08:17:24 2014

# Wed Jul 02 14:52:26 2014

Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46

Synopsys Lattice Technology Mapper, Version maplat, Build 800R, Built Nov 18 2013 10:58:25

Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

Product Version G-2012.09L-SP1

Product Version I-2013.09L

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)

Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)

Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)

Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)

Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)

Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]

@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]

@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]

@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]

@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]

@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]

@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]

@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]

@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 170MB peak: 171MB)

Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 176MB peak: 176MB)

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 164MB peak: 174MB)

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 171MB peak: 179MB)

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 174MB)

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 165MB peak: 183MB)

@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":222:2:222:5|Pipelining module ea_reg_post_o[15:0]

@N: FA113 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":222:2:222:5|Pipelining module ea_reg_post_o[15:0]

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IX[15:0] pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register IY[15:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IY[15:0] pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register IX[15:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_ind_ea[7:0] pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register DP[7:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register DP[7:0] pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register ACCB[7:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register ACCB[7:0] pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register eflag pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register eflag pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register fflag pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register fflag pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register hflag pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register hflag pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register intff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register intff pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register nff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register nff pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register zff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register zff pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register vff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register vff pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register cff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register cff pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register PC[15:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register PC[15:0] pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register ACCA[7:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register ACCA[7:0] pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Register k_write_pc pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_write_pc pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Register k_inc_pc pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_inc_pc pushed in.

@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":35:0:35:5|Register ra_in[15:0] pushed in.

@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]

@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]

Starting Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 174MB)

Starting Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 167MB peak: 183MB)

Finished Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 163MB peak: 174MB)

Finished Early Timing Optimization (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 168MB peak: 183MB)

Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 162MB peak: 174MB)

Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 167MB peak: 183MB)

Finished preparing to map (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 162MB peak: 174MB)

Finished preparing to map (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 167MB peak: 183MB)

Finished technology mapping (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 207MB peak: 228MB)

Finished technology mapping (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 211MB peak: 241MB)

   1            0h:00m:15s                  -5.66ns             2142 /       580

   1            0h:00m:16s                  -5.65ns             2081 /       584

   2            0h:00m:15s                  -5.55ns             2137 /       580

   2            0h:00m:16s                  -5.65ns             2081 /       584

   3            0h:00m:15s                  -5.55ns             2137 /       580

   3            0h:00m:16s                  -5.65ns             2081 /       584

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_postbyte[5]" with 23 loads replicated 2 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[3]" with 66 loads replicated 3 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_postbyte[4]" with 19 loads replicated 1 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[2]" with 58 loads replicated 2 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_opcode[3]" with 57 loads replicated 3 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[7]" with 27 loads replicated 2 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_opcode[1]" with 53 loads replicated 2 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[4]" with 19 loads replicated 2 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_opcode[2]" with 53 loads replicated 2 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[3]" with 19 loads replicated 2 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_opcode[0]" with 49 loads replicated 2 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[2]" with 17 loads replicated 2 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_postbyte[7]" with 28 loads replicated 2 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[0]" with 53 loads replicated 2 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_postbyte[3]" with 20 loads replicated 1 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[6]" with 49 loads replicated 3 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_postbyte[2]" with 18 loads replicated 1 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[7]" with 40 loads replicated 2 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_postbyte[1]" with 16 loads replicated 2 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[4]" with 37 loads replicated 2 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_ind_ea[7]" with 32 loads replicated 2 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[5]" with 36 loads replicated 2 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_ind_ea[1]" with 30 loads replicated 2 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[5]" with 25 loads replicated 2 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_postbyte[6]" with 22 loads replicated 2 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[6]" with 22 loads replicated 2 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_opcode[6]" with 54 loads replicated 3 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[1]" with 53 loads replicated 3 times to improve timing

Added 38 Registers via timing driven replication

Added 31 Registers via timing driven replication

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.k_ind_ea[2]" with 22 loads replicated 2 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[3]" with 9 loads replicated 1 times to improve timing

@N: FX271 :|Instance "cpu0.regs.IY_pipe_14" with 16 loads replicated 2 times to improve timing

@N: FX271 :|Instance "cpu0.regs.IX_pipe_1" with 16 loads replicated 2 times to improve timing

@N: FX271 :|Instance "cpu0.regs.IX_pipe_14" with 16 loads replicated 2 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.state[3]" with 61 loads replicated 2 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.state[3]" with 59 loads replicated 3 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[6]" with 37 loads replicated 3 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Instance "cpu0.state[2]" with 60 loads replicated 3 times to improve timing

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":35:0:35:5|Instance "cpu0.alu.rop_in[1]" with 59 loads replicated 2 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":35:0:35:5|Instance "cpu0.alu.rop_in[1]" with 60 loads replicated 2 times to improve timing

Added 10 Registers via timing driven replication

Added 14 Registers via timing driven replication

Added 2 LUTs via timing driven replication

   1            0h:00m:16s                  -3.72ns             2176 /       632

   1            0h:00m:18s                  -2.91ns             2131 /       637

@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":64:10:64:33|Instance "textctrl.vsync_cnt_2_sqmuxa_i_0_o3" with 44 loads replicated 1 times to improve timing

@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":64:10:64:33|Instance "textctrl.vsync_cnt_2_sqmuxa_i_0_o3" with 58 loads replicated 1 times to improve timing

Added 0 Registers via timing driven replication

   1            0h:00m:16s                  -4.00ns             2185 /       635

   1            0h:00m:18s                  -2.95ns             2131 /       637

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 169MB peak: 228MB)

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 183MB peak: 241MB)

Finished restoring hierarchy (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 171MB peak: 228MB)

Finished restoring hierarchy (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:19s; Memory used current: 185MB peak: 241MB)

1 non-gated/non-generated clock tree(s) driving 651 clock pin(s) of sequential element(s)

1 non-gated/non-generated clock tree(s) driving 653 clock pin(s) of sequential element(s)

315 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks

310 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks

@K:CKID0001       clk40_i             port                   651        div

@K:CKID0001       clk40_i             port                   653        cpu_clk

Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809.srm

Writing Analyst data base C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 173MB peak: 228MB)

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:20s; Memory used current: 186MB peak: 241MB)

G-2012.09L-SP1

@W: MT558 |Unable to locate source for clock CC3_top|div_derived_clock. Clock will not be forward annotated

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:18s; Memory used current: 178MB peak: 228MB)

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:21s; Memory used current: 191MB peak: 241MB)

@W: MT420 |Found inferred clock CC3_top|clk40_i with period 13.45ns. Please declare a user-defined clock on object "p:clk40_i"

@W: MT420 |Found inferred clock CC3_top|clk40_i with period 13.64ns. Please declare a user-defined clock on object "p:clk40_i"

# Timing Report written on Sun Jun 22 08:17:43 2014

# Timing Report written on Wed Jul 02 14:52:48 2014

Requested Frequency:    74.3 MHz

Requested Frequency:    73.3 MHz

Worst slack in design: -2.030

Worst slack in design: -2.407

CC3_top|clk40_i     74.3 MHz      64.6 MHz      13.451        15.482        -2.030     inferred     Autoconstr_clkgroup_0

CC3_top|clk40_i     73.3 MHz      62.3 MHz      13.639        16.046        -2.407     inferred     Autoconstr_clkgroup_0

CC3_top|clk40_i  CC3_top|clk40_i  |  13.452      -2.030  |  No paths    -      |  No paths    -      |  No paths    -

CC3_top|clk40_i  CC3_top|clk40_i  |  13.639      -2.407  |  No paths    -      |  No paths    -      |  No paths    -

--------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------

cpu0.regs.IX_pipe_14_fast     CC3_top|clk40_i     FD1P3AX     Q       IX_0_sqmuxaf_fast     1.044       -2.030

cpu0.regs.IX_pipe_4_fast     CC3_top|clk40_i     FD1P3AX     Q       IX_0_sqmuxaf_fast     1.108       -2.407

cpu0.regs.IY_pipe_14_fast     CC3_top|clk40_i     FD1P3AX     Q       IY_1_sqmuxaf_fast     1.044       -2.030

cpu0.regs.IX_pipe_77         CC3_top|clk40_i     FD1P3AX     Q       left_1f_0[0]          0.972       -2.271

cpu0.regs.IX_pipe_77          CC3_top|clk40_i     FD1P3AX     Q       left_1f_0[0]          0.972       -1.958

cpu0.regs.IX_pipe_78         CC3_top|clk40_i     FD1P3AX     Q       ea_reg_postf_0[0]     0.972       -2.271

cpu0.regs.IX_pipe_78          CC3_top|clk40_i     FD1P3AX     Q       ea_reg_postf_0[0]     0.972       -1.958

cpu0.k_ind_ea_fast[1]        CC3_top|clk40_i     FD1P3AX     Q       k_ind_ea_fast[1]      1.180       -2.166

cpu0.regs.IY_pipe_77          CC3_top|clk40_i     FD1P3AX     Q       left_1f[0]            0.972       -1.958

cpu0.k_ind_ea_fast[0]        CC3_top|clk40_i     FD1P3AX     Q       k_ind_ea_fast[0]      1.148       -2.134

cpu0.regs.IY_pipe_78          CC3_top|clk40_i     FD1P3AX     Q       ea_reg_postf[0]       0.972       -1.958

cpu0.regs.IY_pipe_4_fast     CC3_top|clk40_i     FD1P3AX     Q       IY_1_sqmuxaf_fast     1.148       -2.096

cpu0.regs.IX_pipe_14_rep1     CC3_top|clk40_i     FD1P3AX     Q       IX_0_sqmuxaf_rep1     1.180       -1.816

cpu0.k_ind_ea_fast[2]        CC3_top|clk40_i     FD1P3AX     Q       k_ind_ea_fast[2]      1.044       -2.030

cpu0.regs.IY_pipe_14_rep1     CC3_top|clk40_i     FD1P3AX     Q       IY_1_sqmuxaf_rep1     1.180       -1.816

cpu0.regs.IX_pipe_4_rep1     CC3_top|clk40_i     FD1P3AX     Q       IX_0_sqmuxaf_rep1     1.180       -1.985

cpu0.k_ind_ea_fast[1]         CC3_top|clk40_i     FD1P3AX     Q       k_ind_ea_fast[1]      1.180       -1.721

cpu0.regs.IY_pipe_4_rep1     CC3_top|clk40_i     FD1P3AX     Q       IY_1_sqmuxaf_rep1     1.180       -1.985

cpu0.regs.IX_pipe_67          CC3_top|clk40_i     FD1P3AX     Q       left_1f_0[2]          0.972       -1.608

cpu0.regs.IX_pipe_67         CC3_top|clk40_i     FD1P3AX     Q       left_1f_0[2]          0.972       -1.920

==============================================================================================================

=============================================================================================================

---------------------------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------

cpu0.regs.SS[10]        CC3_top|clk40_i     FD1P3AX     D       SS_lm[10]             13.540       -2.030

cpu0.regs.SS[13]     CC3_top|clk40_i     FD1P3AX     D       SS_lm[13]     13.728       -2.407

cpu0.regs.SU[10]        CC3_top|clk40_i     FD1P3AX     D       SU_lm[10]             13.540       -2.030

cpu0.regs.SU[13]     CC3_top|clk40_i     FD1P3AX     D       SU_lm[13]     13.728       -2.407

cpu0.regs.SS[13]        CC3_top|clk40_i     FD1P3AX     D       SS_lm[13]             13.540       -1.513

cpu0.regs.SS[7]      CC3_top|clk40_i     FD1P3AX     D       SS_lm[7]      13.728       -1.555

cpu0.regs.SU[13]        CC3_top|clk40_i     FD1P3AX     D       SU_lm[13]             13.540       -1.513

cpu0.regs.SU[7]      CC3_top|clk40_i     FD1P3AX     D       SU_lm[7]      13.728       -1.555

cpu0.regs.SS[11]        CC3_top|clk40_i     FD1P3AX     D       SS_lm[11]             13.540       -1.343

cpu0.regs.SS[10]     CC3_top|clk40_i     FD1P3AX     D       SS_lm[10]     13.728       -1.553

cpu0.regs.SU[11]        CC3_top|clk40_i     FD1P3AX     D       SU_lm[11]             13.540       -1.343

cpu0.regs.SU[10]     CC3_top|clk40_i     FD1P3AX     D       SU_lm[10]     13.728       -1.553

cpu0.regs.SS[9]         CC3_top|clk40_i     FD1P3AX     D       SS_lm[9]              13.540       -1.246

cpu0.regs.SS[9]      CC3_top|clk40_i     FD1P3AX     D       SS_lm[9]      13.728       -1.299

cpu0.regs.SU[9]         CC3_top|clk40_i     FD1P3AX     D       SU_lm[9]              13.540       -1.246

cpu0.regs.SU[9]      CC3_top|clk40_i     FD1P3AX     D       SU_lm[9]      13.728       -1.299

cpu0.k_cpu_addr[15]     CC3_top|clk40_i     FD1P3AX     D       k_cpu_addr_28[15]     13.540       -0.944

cpu0.regs.SS[6]      CC3_top|clk40_i     FD1P3AX     D       SS_lm[6]      13.728       -1.204

cpu0.regs.SS[4]         CC3_top|clk40_i     FD1P3AX     D       SS_lm[4]              13.540       -0.839

cpu0.regs.SU[6]      CC3_top|clk40_i     FD1P3AX     D       SU_lm[6]      13.728       -1.204

=========================================================================================================

==============================================================================================

      Requested Period:                      13.451

      Requested Period:                      13.639

    = Required time:                         13.540

    = Required time:                         13.728

    - Propagation time:                      15.571

    - Propagation time:                      16.134

    = Slack (critical) :                     -2.030

    = Slack (critical) :                     -2.407

    Number of logic level(s):                17

    Number of logic level(s):                20

    Starting point:                          cpu0.regs.IX_pipe_14_fast / Q

    Starting point:                          cpu0.regs.IX_pipe_4_fast / Q

    Ending point:                            cpu0.regs.SS[10] / D

    Ending point:                            cpu0.regs.SS[13] / D

cpu0.regs.IX_pipe_14_fast                 FD1P3AX      Q        Out     1.044     1.044       -

cpu0.regs.IX_pipe_4_fast                  FD1P3AX      Q        Out     1.108     1.108       -

IX_0_sqmuxaf_fast                         Net          -        -       -         -           2

IX_0_sqmuxaf_fast                         Net          -        -       -         -           3

cpu0.regs.IX_10_0[0]                      ORCALUT4     A        In      0.000     1.044       -

cpu0.regs.IX_10_0[0]                      ORCALUT4     A        In      0.000     1.108       -

cpu0.regs.IX_10_0[0]                      ORCALUT4     Z        Out     1.017     2.061       -

cpu0.regs.IX_10_0[0]                      ORCALUT4     Z        Out     1.017     2.125       -

N_629                                     Net          -        -       -         -           1

N_631                                     Net          -        -       -         -           1

cpu0.regs.IX_10[0]                        ORCALUT4     B        In      0.000     2.061       -

cpu0.regs.IX_10[0]                        ORCALUT4     B        In      0.000     2.125       -

cpu0.regs.IX_10[0]                        ORCALUT4     Z        Out     1.153     3.213       -

cpu0.regs.IX_10[0]                        ORCALUT4     Z        Out     1.153     3.277       -

cpu0.regs.ea.ea_reg_3_am[0]               ORCALUT4     B        In      0.000     3.213       -

cpu0.regs.ea.ea_reg_3_am[0]               ORCALUT4     B        In      0.000     3.277       -

cpu0.regs.ea.ea_reg_3_am[0]               ORCALUT4     Z        Out     1.017     4.230       -

cpu0.regs.ea.ea_reg_3_am[0]               ORCALUT4     Z        Out     1.017     4.294       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        BLUT     In      0.000     4.230       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        BLUT     In      0.000     4.294       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        Z        Out     0.422     4.652       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        Z        Out     0.422     4.716       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     C        In      0.000     4.652       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     A        In      0.000     4.716       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     Z        Out     1.089     5.741       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     Z        Out     1.089     5.805       -

N_72_0                                    Net          -        -       -         -           2

N_72                                      Net          -        -       -         -           2

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        C1       In      0.000     5.741       -

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        C1       In      0.000     5.805       -

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        COUT     Out     1.544     7.286       -

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        COUT     Out     1.545     7.350       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        CIN      In      0.000     7.286       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        CIN      In      0.000     7.350       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        COUT     Out     0.143     7.428       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        COUT     Out     0.143     7.492       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        CIN      In      0.000     7.428       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        CIN      In      0.000     7.492       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        COUT     Out     0.143     7.571       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        COUT     Out     0.143     7.635       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        CIN      In      0.000     7.571       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        CIN      In      0.000     7.635       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        COUT     Out     0.143     7.714       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        COUT     Out     0.143     7.778       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        CIN      In      0.000     7.714       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        CIN      In      0.000     7.778       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        COUT     Out     0.143     7.857       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        COUT     Out     0.143     7.921       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        CIN      In      0.000     7.857       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        CIN      In      0.000     7.921       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        S1       Out     1.725     9.582       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        COUT     Out     0.143     8.064       -

regs_o_eamem_addr[10]                     Net          -        -       -         -           4

eamem_addr_o_cry_10                       Net          -        -       -         -           1

cpu0.regs.datamux_o_dest_0[10]            ORCALUT4     D        In      0.000     9.582       -

cpu0.regs.ea.eamem_addr_o_cry_11_0        CCU2D        CIN      In      0.000     8.064       -

cpu0.regs.datamux_o_dest_0[10]            ORCALUT4     Z        Out     1.017     10.599      -

cpu0.regs.ea.eamem_addr_o_cry_11_0        CCU2D        COUT     Out     0.143     8.207       -

N_1475                                    Net          -        -       -         -           1

eamem_addr_o_cry_12                       Net          -        -       -         -           1

cpu0.regs.datamux_o_dest[10]              ORCALUT4     A        In      0.000     10.599      -

cpu0.regs.ea.eamem_addr_o_cry_13_0        CCU2D        CIN      In      0.000     8.207       -

cpu0.regs.datamux_o_dest[10]              ORCALUT4     Z        Out     1.089     11.688      -

cpu0.regs.ea.eamem_addr_o_cry_13_0        CCU2D        S0       Out     1.725     9.931       -

datamux_o_dest[10]                        Net          -        -       -         -           2

regs_o_eamem_addr[13]                     Net          -        -       -         -           4

cpu0.regs.path_left_data_RNI19RA1[10]     ORCALUT4     B        In      0.000     11.688      -

cpu0.regs.ea.datamux_o_dest_6[13]         ORCALUT4     D        In      0.000     9.931       -

cpu0.regs.path_left_data_RNI19RA1[10]     ORCALUT4     Z        Out     1.233     12.920      -

cpu0.regs.ea.datamux_o_dest_6[13]         ORCALUT4     Z        Out     1.017     10.948      -

left_1[10]                                Net          -        -       -         -           6

datamux_o_dest_6[13]                      Net          -        -       -         -           1

cpu0.regs.SS_16_0[10]                     ORCALUT4     B        In      0.000     12.920      -

cpu0.regs.ea.datamux_o_dest_am[13]        ORCALUT4     B        In      0.000     10.948      -

cpu0.regs.SS_16_0[10]                     ORCALUT4     Z        Out     1.017     13.937      -

cpu0.regs.ea.datamux_o_dest_am[13]        ORCALUT4     Z        Out     1.017     11.965      -

N_253                                     Net          -        -       -         -           1

datamux_o_dest_am[13]                     Net          -        -       -         -           1

cpu0.regs.SS_16[10]                       ORCALUT4     A        In      0.000     13.937      -

cpu0.regs.ea.datamux_o_dest[13]           PFUMX        BLUT     In      0.000     11.965      -

cpu0.regs.SS_16[10]                       ORCALUT4     Z        Out     1.017     14.954      -

cpu0.regs.ea.datamux_o_dest[13]           PFUMX        Z        Out     0.286     12.251      -

SS_16[10]                                 Net          -        -       -         -           1

datamux_o_dest[13]                        Net          -        -       -         -           2

cpu0.regs.SS_lm_0[10]                     ORCALUT4     A        In      0.000     14.954      -

cpu0.regs.path_left_data_RNIRO271[13]     ORCALUT4     B        In      0.000     12.251      -

cpu0.regs.SS_lm_0[10]                     ORCALUT4     Z        Out     0.617     15.571      -

cpu0.regs.path_left_data_RNIRO271[13]     ORCALUT4     Z        Out     1.233     13.484      -

SS_lm[10]                                 Net          -        -       -         -           1

left_1[13]                                Net          -        -       -         -           6

cpu0.regs.SS[10]                          FD1P3AX      D        In      0.000     15.571      -

cpu0.regs.SS_16_0[13]                     ORCALUT4     B        In      0.000     13.484      -

      Requested Period:                      13.451

      Requested Period:                      13.639

    = Required time:                         13.540

    = Required time:                         13.728

    - Propagation time:                      15.571

    - Propagation time:                      16.134

    = Slack (critical) :                     -2.030

    = Slack (critical) :                     -2.407

    Number of logic level(s):                17

    Number of logic level(s):                20

    Starting point:                          cpu0.regs.IY_pipe_14_fast / Q

    Starting point:                          cpu0.regs.IX_pipe_4_fast / Q

    Ending point:                            cpu0.regs.SS[10] / D

    Ending point:                            cpu0.regs.SU[13] / D

cpu0.regs.IY_pipe_14_fast                 FD1P3AX      Q        Out     1.044     1.044       -

cpu0.regs.IX_pipe_4_fast                  FD1P3AX      Q        Out     1.108     1.108       -

IY_1_sqmuxaf_fast                         Net          -        -       -         -           2

IX_0_sqmuxaf_fast                         Net          -        -       -         -           3

cpu0.regs.IY_10_0[0]                      ORCALUT4     A        In      0.000     1.044       -

cpu0.regs.IX_10_0[0]                      ORCALUT4     A        In      0.000     1.108       -

cpu0.regs.IY_10_0[0]                      ORCALUT4     Z        Out     1.017     2.061       -

cpu0.regs.IX_10_0[0]                      ORCALUT4     Z        Out     1.017     2.125       -

N_665                                     Net          -        -       -         -           1

N_631                                     Net          -        -       -         -           1

cpu0.regs.IY_10[0]                        ORCALUT4     B        In      0.000     2.061       -

cpu0.regs.IX_10[0]                        ORCALUT4     B        In      0.000     2.125       -

cpu0.regs.IY_10[0]                        ORCALUT4     Z        Out     1.153     3.213       -

cpu0.regs.IX_10[0]                        ORCALUT4     Z        Out     1.153     3.277       -

IY[0]                                     Net          -        -       -         -           3

IX[0]                                     Net          -        -       -         -           3

cpu0.regs.ea.ea_reg_3_bm[0]               ORCALUT4     B        In      0.000     3.213       -

cpu0.regs.ea.ea_reg_3_am[0]               ORCALUT4     B        In      0.000     3.277       -

cpu0.regs.ea.ea_reg_3_bm[0]               ORCALUT4     Z        Out     1.017     4.230       -

cpu0.regs.ea.ea_reg_3_am[0]               ORCALUT4     Z        Out     1.017     4.294       -

ea_reg_3_bm[0]                            Net          -        -       -         -           1

ea_reg_3_am[0]                            Net          -        -       -         -           1

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        ALUT     In      0.000     4.230       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        BLUT     In      0.000     4.294       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        Z        Out     0.422     4.652       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        Z        Out     0.422     4.716       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     C        In      0.000     4.652       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     A        In      0.000     4.716       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     Z        Out     1.089     5.741       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     Z        Out     1.089     5.805       -

N_72_0                                    Net          -        -       -         -           2

N_72                                      Net          -        -       -         -           2

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        C1       In      0.000     5.741       -

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        C1       In      0.000     5.805       -

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        COUT     Out     1.544     7.286       -

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        COUT     Out     1.545     7.350       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        CIN      In      0.000     7.286       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        CIN      In      0.000     7.350       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        COUT     Out     0.143     7.428       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        COUT     Out     0.143     7.492       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        CIN      In      0.000     7.428       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        CIN      In      0.000     7.492       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        COUT     Out     0.143     7.571       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        COUT     Out     0.143     7.635       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        CIN      In      0.000     7.571       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        CIN      In      0.000     7.635       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        COUT     Out     0.143     7.714       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        COUT     Out     0.143     7.778       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        CIN      In      0.000     7.714       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        CIN      In      0.000     7.778       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        COUT     Out     0.143     7.857       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        COUT     Out     0.143     7.921       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        CIN      In      0.000     7.857       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        CIN      In      0.000     7.921       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        S1       Out     1.725     9.582       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        COUT     Out     0.143     8.064       -

regs_o_eamem_addr[10]                     Net          -        -       -         -           4

eamem_addr_o_cry_10                       Net          -        -       -         -           1

cpu0.regs.datamux_o_dest_0[10]            ORCALUT4     D        In      0.000     9.582       -

cpu0.regs.ea.eamem_addr_o_cry_11_0        CCU2D        CIN      In      0.000     8.064       -

cpu0.regs.datamux_o_dest_0[10]            ORCALUT4     Z        Out     1.017     10.599      -

cpu0.regs.ea.eamem_addr_o_cry_11_0        CCU2D        COUT     Out     0.143     8.207       -

N_1475                                    Net          -        -       -         -           1

eamem_addr_o_cry_12                       Net          -        -       -         -           1

cpu0.regs.datamux_o_dest[10]              ORCALUT4     A        In      0.000     10.599      -

cpu0.regs.ea.eamem_addr_o_cry_13_0        CCU2D        CIN      In      0.000     8.207       -

cpu0.regs.datamux_o_dest[10]              ORCALUT4     Z        Out     1.089     11.688      -

cpu0.regs.ea.eamem_addr_o_cry_13_0        CCU2D        S0       Out     1.725     9.931       -

datamux_o_dest[10]                        Net          -        -       -         -           2

regs_o_eamem_addr[13]                     Net          -        -       -         -           4

cpu0.regs.path_left_data_RNI19RA1[10]     ORCALUT4     B        In      0.000     11.688      -

cpu0.regs.ea.datamux_o_dest_6[13]         ORCALUT4     D        In      0.000     9.931       -

cpu0.regs.path_left_data_RNI19RA1[10]     ORCALUT4     Z        Out     1.233     12.920      -

cpu0.regs.ea.datamux_o_dest_6[13]         ORCALUT4     Z        Out     1.017     10.948      -

left_1[10]                                Net          -        -       -         -           6

datamux_o_dest_6[13]                      Net          -        -       -         -           1

cpu0.regs.SS_16_0[10]                     ORCALUT4     B        In      0.000     12.920      -

cpu0.regs.ea.datamux_o_dest_am[13]        ORCALUT4     B        In      0.000     10.948      -

cpu0.regs.SS_16_0[10]                     ORCALUT4     Z        Out     1.017     13.937      -

cpu0.regs.ea.datamux_o_dest_am[13]        ORCALUT4     Z        Out     1.017     11.965      -

N_253                                     Net          -        -       -         -           1

datamux_o_dest_am[13]                     Net          -        -       -         -           1

cpu0.regs.SS_16[10]                       ORCALUT4     A        In      0.000     13.937      -

cpu0.regs.ea.datamux_o_dest[13]           PFUMX        BLUT     In      0.000     11.965      -

cpu0.regs.SS_16[10]                       ORCALUT4     Z        Out     1.017     14.954      -

cpu0.regs.ea.datamux_o_dest[13]           PFUMX        Z        Out     0.286     12.251      -

SS_16[10]                                 Net          -        -       -         -           1

datamux_o_dest[13]                        Net          -        -       -         -           2

cpu0.regs.SS_lm_0[10]                     ORCALUT4     A        In      0.000     14.954      -

cpu0.regs.path_left_data_RNIRO271[13]     ORCALUT4     B        In      0.000     12.251      -

cpu0.regs.SS_lm_0[10]                     ORCALUT4     Z        Out     0.617     15.571      -

cpu0.regs.path_left_data_RNIRO271[13]     ORCALUT4     Z        Out     1.233     13.484      -

SS_lm[10]                                 Net          -        -       -         -           1

left_1[13]                                Net          -        -       -         -           6

cpu0.regs.SS[10]                          FD1P3AX      D        In      0.000     15.571      -

cpu0.regs.SU_16_0[13]                     ORCALUT4     B        In      0.000     13.484      -

      Requested Period:                      13.451

      Requested Period:                      13.639

    = Required time:                         13.540

    = Required time:                         13.728

    - Propagation time:                      15.571

    - Propagation time:                      15.999

    = Slack (critical) :                     -2.030

    = Slack (non-critical) :                 -2.271

    Number of logic level(s):                17

    Number of logic level(s):                20

    Starting point:                          cpu0.regs.IX_pipe_14_fast / Q

    Starting point:                          cpu0.regs.IX_pipe_77 / Q

    Ending point:                            cpu0.regs.SU[10] / D

    Ending point:                            cpu0.regs.SS[13] / D

cpu0.regs.IX_pipe_14_fast                 FD1P3AX      Q        Out     1.044     1.044       -

cpu0.regs.IX_pipe_77                      FD1P3AX      Q        Out     0.972     0.972       -

IX_0_sqmuxaf_fast                         Net          -        -       -         -           2

left_1f_0[0]                              Net          -        -       -         -           1

cpu0.regs.IX_10_0[0]                      ORCALUT4     A        In      0.000     1.044       -

cpu0.regs.IX_10_0[0]                      ORCALUT4     C        In      0.000     0.972       -

cpu0.regs.IX_10_0[0]                      ORCALUT4     Z        Out     1.017     2.061       -

cpu0.regs.IX_10_0[0]                      ORCALUT4     Z        Out     1.017     1.989       -

N_629                                     Net          -        -       -         -           1

N_631                                     Net          -        -       -         -           1

cpu0.regs.IX_10[0]                        ORCALUT4     B        In      0.000     2.061       -

cpu0.regs.IX_10[0]                        ORCALUT4     B        In      0.000     1.989       -

cpu0.regs.IX_10[0]                        ORCALUT4     Z        Out     1.153     3.213       -

cpu0.regs.IX_10[0]                        ORCALUT4     Z        Out     1.153     3.141       -

cpu0.regs.ea.ea_reg_3_am[0]               ORCALUT4     B        In      0.000     3.213       -

cpu0.regs.ea.ea_reg_3_am[0]               ORCALUT4     B        In      0.000     3.141       -

cpu0.regs.ea.ea_reg_3_am[0]               ORCALUT4     Z        Out     1.017     4.230       -

cpu0.regs.ea.ea_reg_3_am[0]               ORCALUT4     Z        Out     1.017     4.158       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        BLUT     In      0.000     4.230       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        BLUT     In      0.000     4.158       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        Z        Out     0.422     4.652       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        Z        Out     0.422     4.580       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     C        In      0.000     4.652       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     A        In      0.000     4.580       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     Z        Out     1.089     5.741       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     Z        Out     1.089     5.669       -

N_72_0                                    Net          -        -       -         -           2

N_72                                      Net          -        -       -         -           2

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        C1       In      0.000     5.741       -

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        C1       In      0.000     5.669       -

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        COUT     Out     1.544     7.286       -

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        COUT     Out     1.545     7.214       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        CIN      In      0.000     7.286       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        CIN      In      0.000     7.214       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        COUT     Out     0.143     7.428       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        COUT     Out     0.143     7.356       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        CIN      In      0.000     7.428       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        CIN      In      0.000     7.356       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        COUT     Out     0.143     7.571       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        COUT     Out     0.143     7.499       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        CIN      In      0.000     7.571       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        CIN      In      0.000     7.499       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        COUT     Out     0.143     7.714       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        COUT     Out     0.143     7.642       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        CIN      In      0.000     7.714       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        CIN      In      0.000     7.642       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        COUT     Out     0.143     7.857       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        COUT     Out     0.143     7.785       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        CIN      In      0.000     7.857       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        CIN      In      0.000     7.785       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        S1       Out     1.725     9.582       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        COUT     Out     0.143     7.928       -

regs_o_eamem_addr[10]                     Net          -        -       -         -           4

eamem_addr_o_cry_10                       Net          -        -       -         -           1

cpu0.regs.datamux_o_dest_0[10]            ORCALUT4     D        In      0.000     9.582       -

cpu0.regs.ea.eamem_addr_o_cry_11_0        CCU2D        CIN      In      0.000     7.928       -

cpu0.regs.datamux_o_dest_0[10]            ORCALUT4     Z        Out     1.017     10.599      -

cpu0.regs.ea.eamem_addr_o_cry_11_0        CCU2D        COUT     Out     0.143     8.070       -

N_1475                                    Net          -        -       -         -           1

eamem_addr_o_cry_12                       Net          -        -       -         -           1

cpu0.regs.datamux_o_dest[10]              ORCALUT4     A        In      0.000     10.599      -

cpu0.regs.ea.eamem_addr_o_cry_13_0        CCU2D        CIN      In      0.000     8.070       -

cpu0.regs.datamux_o_dest[10]              ORCALUT4     Z        Out     1.089     11.688      -

cpu0.regs.ea.eamem_addr_o_cry_13_0        CCU2D        S0       Out     1.725     9.796       -

datamux_o_dest[10]                        Net          -        -       -         -           2

regs_o_eamem_addr[13]                     Net          -        -       -         -           4

cpu0.regs.path_left_data_RNI19RA1[10]     ORCALUT4     B        In      0.000     11.688      -

cpu0.regs.ea.datamux_o_dest_6[13]         ORCALUT4     D        In      0.000     9.796       -

cpu0.regs.path_left_data_RNI19RA1[10]     ORCALUT4     Z        Out     1.233     12.920      -

cpu0.regs.ea.datamux_o_dest_6[13]         ORCALUT4     Z        Out     1.017     10.812      -

left_1[10]                                Net          -        -       -         -           6

datamux_o_dest_6[13]                      Net          -        -       -         -           1

cpu0.regs.SU_16_0[10]                     ORCALUT4     B        In      0.000     12.920      -

cpu0.regs.ea.datamux_o_dest_am[13]        ORCALUT4     B        In      0.000     10.812      -

cpu0.regs.SU_16_0[10]                     ORCALUT4     Z        Out     1.017     13.937      -

cpu0.regs.ea.datamux_o_dest_am[13]        ORCALUT4     Z        Out     1.017     11.829      -

N_289                                     Net          -        -       -         -           1

datamux_o_dest_am[13]                     Net          -        -       -         -           1

cpu0.regs.SU_16[10]                       ORCALUT4     A        In      0.000     13.937      -

cpu0.regs.ea.datamux_o_dest[13]           PFUMX        BLUT     In      0.000     11.829      -

cpu0.regs.SU_16[10]                       ORCALUT4     Z        Out     1.017     14.954      -

cpu0.regs.ea.datamux_o_dest[13]           PFUMX        Z        Out     0.286     12.115      -

SU_16[10]                                 Net          -        -       -         -           1

datamux_o_dest[13]                        Net          -        -       -         -           2

cpu0.regs.SU_lm_0[10]                     ORCALUT4     A        In      0.000     14.954      -

cpu0.regs.path_left_data_RNIRO271[13]     ORCALUT4     B        In      0.000     12.115      -

cpu0.regs.SU_lm_0[10]                     ORCALUT4     Z        Out     0.617     15.571      -

cpu0.regs.path_left_data_RNIRO271[13]     ORCALUT4     Z        Out     1.233     13.348      -

SU_lm[10]                                 Net          -        -       -         -           1

left_1[13]                                Net          -        -       -         -           6

cpu0.regs.SU[10]                          FD1P3AX      D        In      0.000     15.571      -

cpu0.regs.SS_16_0[13]                     ORCALUT4     B        In      0.000     13.348      -

      Requested Period:                      13.451

      Requested Period:                      13.639

    = Required time:                         13.540

    = Required time:                         13.728

    - Propagation time:                      15.571

    - Propagation time:                      15.999

    = Slack (critical) :                     -2.030

    = Slack (non-critical) :                 -2.271

    Number of logic level(s):                17

    Number of logic level(s):                20

    Starting point:                          cpu0.regs.IY_pipe_14_fast / Q

    Starting point:                          cpu0.regs.IX_pipe_78 / Q

    Ending point:                            cpu0.regs.SU[10] / D

    Ending point:                            cpu0.regs.SS[13] / D

cpu0.regs.IY_pipe_14_fast                 FD1P3AX      Q        Out     1.044     1.044       -

cpu0.regs.IX_pipe_78                      FD1P3AX      Q        Out     0.972     0.972       -

IY_1_sqmuxaf_fast                         Net          -        -       -         -           2

ea_reg_postf_0[0]                         Net          -        -       -         -           1

cpu0.regs.IY_10_0[0]                      ORCALUT4     A        In      0.000     1.044       -

cpu0.regs.IX_10_0[0]                      ORCALUT4     B        In      0.000     0.972       -

cpu0.regs.IY_10_0[0]                      ORCALUT4     Z        Out     1.017     2.061       -

cpu0.regs.IX_10_0[0]                      ORCALUT4     Z        Out     1.017     1.989       -

N_665                                     Net          -        -       -         -           1

N_631                                     Net          -        -       -         -           1

cpu0.regs.IY_10[0]                        ORCALUT4     B        In      0.000     2.061       -

cpu0.regs.IX_10[0]                        ORCALUT4     B        In      0.000     1.989       -

cpu0.regs.IY_10[0]                        ORCALUT4     Z        Out     1.153     3.213       -

cpu0.regs.IX_10[0]                        ORCALUT4     Z        Out     1.153     3.141       -

IY[0]                                     Net          -        -       -         -           3

IX[0]                                     Net          -        -       -         -           3

cpu0.regs.ea.ea_reg_3_bm[0]               ORCALUT4     B        In      0.000     3.213       -

cpu0.regs.ea.ea_reg_3_am[0]               ORCALUT4     B        In      0.000     3.141       -

cpu0.regs.ea.ea_reg_3_bm[0]               ORCALUT4     Z        Out     1.017     4.230       -

cpu0.regs.ea.ea_reg_3_am[0]               ORCALUT4     Z        Out     1.017     4.158       -

ea_reg_3_bm[0]                            Net          -        -       -         -           1

ea_reg_3_am[0]                            Net          -        -       -         -           1

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        ALUT     In      0.000     4.230       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        BLUT     In      0.000     4.158       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        Z        Out     0.422     4.652       -

cpu0.regs.ea.ea_reg_3[0]                  PFUMX        Z        Out     0.422     4.580       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     C        In      0.000     4.652       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     A        In      0.000     4.580       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     Z        Out     1.089     5.741       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     Z        Out     1.089     5.669       -

N_72_0                                    Net          -        -       -         -           2

N_72                                      Net          -        -       -         -           2

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        C1       In      0.000     5.741       -

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        C1       In      0.000     5.669       -

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        COUT     Out     1.544     7.286       -

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        COUT     Out     1.545     7.214       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        CIN      In      0.000     7.286       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        CIN      In      0.000     7.214       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        COUT     Out     0.143     7.428       -

cpu0.regs.ea.eamem_addr_o_cry_1_0         CCU2D        COUT     Out     0.143     7.356       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        CIN      In      0.000     7.428       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        CIN      In      0.000     7.356       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        COUT     Out     0.143     7.571       -

cpu0.regs.ea.eamem_addr_o_cry_3_0         CCU2D        COUT     Out     0.143     7.499       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        CIN      In      0.000     7.571       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        CIN      In      0.000     7.499       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        COUT     Out     0.143     7.714       -

cpu0.regs.ea.eamem_addr_o_cry_5_0         CCU2D        COUT     Out     0.143     7.642       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        CIN      In      0.000     7.714       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        CIN      In      0.000     7.642       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        COUT     Out     0.143     7.857       -

cpu0.regs.ea.eamem_addr_o_cry_7_0         CCU2D        COUT     Out     0.143     7.785       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        CIN      In      0.000     7.857       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        CIN      In      0.000     7.785       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        S1       Out     1.725     9.582       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        COUT     Out     0.143     7.928       -

regs_o_eamem_addr[10]                     Net          -        -       -         -           4

eamem_addr_o_cry_10                       Net          -        -       -         -           1

cpu0.regs.datamux_o_dest_0[10]            ORCALUT4     D        In      0.000     9.582       -

cpu0.regs.ea.eamem_addr_o_cry_11_0        CCU2D        CIN      In      0.000     7.928       -

cpu0.regs.datamux_o_dest_0[10]            ORCALUT4     Z        Out     1.017     10.599      -

cpu0.regs.ea.eamem_addr_o_cry_11_0        CCU2D        COUT     Out     0.143     8.070       -

N_1475                                    Net          -        -       -         -           1

eamem_addr_o_cry_12                       Net          -        -       -         -           1

cpu0.regs.datamux_o_dest[10]              ORCALUT4     A        In      0.000     10.599      -

cpu0.regs.ea.eamem_addr_o_cry_13_0        CCU2D        CIN      In      0.000     8.070       -

cpu0.regs.datamux_o_dest[10]              ORCALUT4     Z        Out     1.089     11.688      -

cpu0.regs.ea.eamem_addr_o_cry_13_0        CCU2D        S0       Out     1.725     9.796       -

datamux_o_dest[10]                        Net          -        -       -         -           2

regs_o_eamem_addr[13]                     Net          -        -       -         -           4

cpu0.regs.path_left_data_RNI19RA1[10]     ORCALUT4     B        In      0.000     11.688      -

cpu0.regs.ea.datamux_o_dest_6[13]         ORCALUT4     D        In      0.000     9.796       -

cpu0.regs.path_left_data_RNI19RA1[10]     ORCALUT4     Z        Out     1.233     12.920      -

cpu0.regs.ea.datamux_o_dest_6[13]         ORCALUT4     Z        Out     1.017     10.812      -

left_1[10]                                Net          -        -       -         -           6

datamux_o_dest_6[13]                      Net          -        -       -         -           1

cpu0.regs.SU_16_0[10]                     ORCALUT4     B        In      0.000     12.920      -

cpu0.regs.ea.datamux_o_dest_am[13]        ORCALUT4     B        In      0.000     10.812      -

cpu0.regs.SU_16_0[10]                     ORCALUT4     Z        Out     1.017     13.937      -

cpu0.regs.ea.datamux_o_dest_am[13]        ORCALUT4     Z        Out     1.017     11.829      -

N_289                                     Net          -        -       -         -           1

datamux_o_dest_am[13]                     Net          -        -       -         -           1

cpu0.regs.SU_16[10]                       ORCALUT4     A        In      0.000     13.937      -

cpu0.regs.ea.datamux_o_dest[13]           PFUMX        BLUT     In      0.000     11.829      -

cpu0.regs.SU_16[10]                       ORCALUT4     Z        Out     1.017     14.954      -

cpu0.regs.ea.datamux_o_dest[13]           PFUMX        Z        Out     0.286     12.115      -

SU_16[10]                                 Net          -        -       -         -           1

datamux_o_dest[13]                        Net          -        -       -         -           2

cpu0.regs.SU_lm_0[10]                     ORCALUT4     A        In      0.000     14.954      -

cpu0.regs.path_left_data_RNIRO271[13]     ORCALUT4     B        In      0.000     12.115      -

cpu0.regs.SU_lm_0[10]                     ORCALUT4     Z        Out     0.617     15.571      -

cpu0.regs.path_left_data_RNIRO271[13]     ORCALUT4     Z        Out     1.233     13.348      -

SU_lm[10]                                 Net          -        -       -         -           1

left_1[13]                                Net          -        -       -         -           6

cpu0.regs.SU[10]                          FD1P3AX      D        In      0.000     15.571      -

cpu0.regs.SS_16_0[13]                     ORCALUT4     B        In      0.000     13.348      -

      Requested Period:                      13.451

      Requested Period:                      13.639

    = Required time:                         13.540

    = Required time:                         13.728

    - Propagation time:                      15.499

    - Propagation time:                      15.999

    = Slack (non-critical) :                 -1.958

    = Slack (non-critical) :                 -2.271

    Number of logic level(s):                17

    Number of logic level(s):                20

    Ending point:                            cpu0.regs.SS[10] / D

    Ending point:                            cpu0.regs.SU[13] / D

N_629                                     Net          -        -       -         -           1

N_631                                     Net          -        -       -         -           1

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     C        In      0.000     4.580       -

cpu0.regs.ea.un1_pc_0[0]                  ORCALUT4     A        In      0.000     4.580       -

N_72_0                                    Net          -        -       -         -           2

N_72                                      Net          -        -       -         -           2

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        COUT     Out     1.544     7.214       -

cpu0.regs.ea.eamem_addr_o_cry_0_0         CCU2D        COUT     Out     1.545     7.214       -

cpu0.regs.ea.eamem_addr_o_cry_9_0         CCU2D        S1       Out     1.725     9.510       -