| Line 11... |
Line 11... |
Performance Hardware Data Status: Final) Version 23.4
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Performance Hardware Data Status: Final) Version 23.4
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Setup and Hold Report
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Setup and Hold Report
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
|
Mon Jan 6 06:55:04 2014
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Thu Feb 6 15:36:11 2014
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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| Line 40... |
Line 40... |
Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
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Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
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4096 items scored, 0 timing errors detected.
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4096 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 1.054ns
|
Passed: The following path meets requirements by 0.251ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q cpu0/alu/rb_in[1] (from cpu_clkgen +)
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Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
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Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
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Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
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|
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Delay: 23.780ns (42.8% logic, 57.2% route), 19 logic levels.
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Delay: 24.583ns (36.2% logic, 63.8% route), 18 logic levels.
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Constraint Details:
|
Constraint Details:
|
|
|
23.780ns physical path delay cpu0/SLICE_229 to cpu0/regs/SLICE_64 meets
|
24.583ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
25.000ns delay constraint less
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25.000ns delay constraint less
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0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 1.054ns
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0.166ns DIN_SET requirement (totaling 24.834ns) by 0.251ns
|
|
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Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_229 to cpu0/regs/SLICE_64:
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
|
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Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R12C13B.CLK to R12C13B.Q1 cpu0/SLICE_229 (from cpu_clkgen)
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
ROUTE 26 1.735 R12C13B.Q1 to R10C14B.A0 cpu0/alu/rb_in[1]
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ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
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C0TOFCO_DE --- 1.023 R10C14B.A0 to R10C14B.FCO cpu0/alu/alu16/a16/SLICE_98
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CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
ROUTE 1 0.000 R10C14B.FCO to R10C14C.FCI cpu0/alu/alu16/a16/un8_q_out_cry_2
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ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
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FCITOF1_DE --- 0.643 R10C14C.FCI to R10C14C.F1 cpu0/alu/alu16/a16/SLICE_97
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CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
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ROUTE 1 1.385 R10C14C.F1 to R11C17C.D0 cpu0/alu/alu16/a16/un8_q_out[4]
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
CTOF_DEL --- 0.495 R11C17C.D0 to R11C17C.F0 cpu0/alu/SLICE_1151
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
ROUTE 1 1.675 R11C17C.F0 to R11C21C.C1 cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO_0_0
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
C1TOFCO_DE --- 0.889 R11C21C.C1 to R11C21C.FCO cpu0/alu/alu16/a16/SLICE_115
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
ROUTE 1 0.000 R11C21C.FCO to R11C21D.FCI cpu0/alu/alu16/a16/q_out_2_cry_4
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
FCITOF0_DE --- 0.585 R11C21D.FCI to R11C21D.F0 cpu0/alu/alu16/a16/SLICE_114
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
ROUTE 1 1.705 R11C21D.F0 to R7C15D.C0 cpu0/alu/alu16/a16/N_2261
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
CTOF_DEL --- 0.495 R7C15D.C0 to R7C15D.F0 cpu0/alu/alu16/SLICE_1209
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
ROUTE 1 0.958 R7C15D.F0 to R9C15A.D1 cpu0/alu/alu16/arith_q[5]
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
CTOOFX_DEL --- 0.721 R9C15A.D1 to R9C15A.OFX0 cpu0/alu/alu16/q_out[5]/SLICE_537
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
ROUTE 2 1.285 R9C15A.OFX0 to R9C22B.C1 cpu0/alu/q16_out[5]
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
CTOOFX_DEL --- 0.721 R9C22B.C1 to R9C22B.OFX0 cpu0/alu/alu16/datamux_o_dest[5]/SLICE_540
|
FCITOF1_DE --- 0.643 R19C19B.FCI to R19C19B.F1 cpu0/regs/ea/SLICE_40
|
ROUTE 2 1.392 R9C22B.OFX0 to R11C20D.D0 cpu0/datamux_o_dest[5]
|
ROUTE 4 2.307 R19C19B.F1 to R16C30C.C1 cpu0/regs_o_eamem_addr[10]
|
CTOF_DEL --- 0.495 R11C20D.D0 to R11C20D.F0 cpu0/regs/SLICE_890
|
CTOF_DEL --- 0.495 R16C30C.C1 to R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
|
ROUTE 9 0.798 R11C20D.F0 to R9C20D.C1 cpu0/regs/left_1[5]
|
ROUTE 1 1.023 R16C30C.F1 to R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
|
CTOF_DEL --- 0.495 R9C20D.C1 to R9C20D.F1 cpu0/regs/SLICE_1124
|
CTOF_DEL --- 0.495 R14C30D.B0 to R14C30D.F0 cpu0/alu/alu16/SLICE_1054
|
ROUTE 1 0.958 R9C20D.F1 to R8C18A.D1 cpu0/regs/N_284
|
ROUTE 2 1.640 R14C30D.F0 to R12C24A.A0 cpu0/datamux_o_dest[10]
|
CTOF_DEL --- 0.495 R8C18A.D1 to R8C18A.F1 cpu0/regs/SLICE_900
|
CTOF_DEL --- 0.495 R12C24A.A0 to R12C24A.F0 cpu0/regs/SLICE_362
|
ROUTE 1 0.626 R8C18A.F1 to R8C18A.D0 cpu0/regs/SU_16[5]
|
ROUTE 6 0.780 R12C24A.F0 to R11C24B.C0 cpu0/regs/left_1[10]
|
CTOF_DEL --- 0.495 R8C18A.D0 to R8C18A.F0 cpu0/regs/SLICE_900
|
CTOF_DEL --- 0.495 R11C24B.C0 to R11C24B.F0 cpu0/regs/SLICE_1191
|
ROUTE 1 1.079 R8C18A.F0 to R10C18D.C1 cpu0/regs/SU_210_i1_mux
|
ROUTE 1 0.958 R11C24B.F0 to R10C23D.D1 cpu0/regs/N_289
|
C1TOFCO_DE --- 0.889 R10C18D.C1 to R10C18D.FCO cpu0/regs/SLICE_69
|
CTOF_DEL --- 0.495 R10C23D.D1 to R10C23D.F1 cpu0/regs/SLICE_949
|
ROUTE 1 0.000 R10C18D.FCO to R10C19A.FCI cpu0/regs/SU_cry[5]
|
ROUTE 1 0.436 R10C23D.F1 to R10C23D.C0 cpu0/regs/SU_16[10]
|
FCITOFCO_D --- 0.162 R10C19A.FCI to R10C19A.FCO cpu0/regs/SLICE_68
|
CTOF_DEL --- 0.495 R10C23D.C0 to R10C23D.F0 cpu0/regs/SLICE_949
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ROUTE 1 0.000 R10C19A.FCO to R10C19B.FCI cpu0/regs/SU_cry[7]
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ROUTE 1 1.506 R10C23D.F0 to R11C23C.C0 cpu0/regs/SU_217_i1_mux
|
FCITOFCO_D --- 0.162 R10C19B.FCI to R10C19B.FCO cpu0/regs/SLICE_67
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C0TOFCO_DE --- 1.023 R11C23C.C0 to R11C23C.FCO cpu0/regs/SLICE_57
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ROUTE 1 0.000 R10C19B.FCO to R10C19C.FCI cpu0/regs/SU_cry[9]
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ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
FCITOFCO_D --- 0.162 R10C19C.FCI to R10C19C.FCO cpu0/regs/SLICE_66
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
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ROUTE 1 0.000 R10C19C.FCO to R10C19D.FCI cpu0/regs/SU_cry[11]
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ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
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FCITOFCO_D --- 0.162 R10C19D.FCI to R10C19D.FCO cpu0/regs/SLICE_65
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FCITOF1_DE --- 0.643 R11C24A.FCI to R11C24A.F1 cpu0/regs/SLICE_55
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ROUTE 1 0.000 R10C19D.FCO to R10C20A.FCI cpu0/regs/SU_cry[13]
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ROUTE 1 0.000 R11C24A.F1 to R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
|
FCITOF1_DE --- 0.643 R10C20A.FCI to R10C20A.F1 cpu0/regs/SLICE_64
|
|
ROUTE 1 0.000 R10C20A.F1 to R10C20A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
|
|
--------
|
--------
|
23.780 (42.8% logic, 57.2% route), 19 logic levels.
|
24.583 (36.2% logic, 63.8% route), 18 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_229:
|
Source Clock Path clk40_i to SLICE_260:
|
|
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Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R12C13B.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R10C20A.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 1.057ns
|
Passed: The following path meets requirements by 0.309ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
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Source: FF Q cpu0/alu/rb_in[8] (from cpu_clkgen +)
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Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
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Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
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Destination: FF Data in cpu0/regs/SU[14] (to cpu_clkgen +)
|
|
|
Delay: 23.777ns (42.5% logic, 57.5% route), 18 logic levels.
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Delay: 24.525ns (36.0% logic, 64.0% route), 18 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
23.777ns physical path delay cpu0/SLICE_232 to cpu0/regs/SLICE_64 meets
|
24.525ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
25.000ns delay constraint less
|
25.000ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 1.057ns
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.309ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_232 to cpu0/regs/SLICE_64:
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
|
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Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R14C16C.CLK to R14C16C.Q0 cpu0/SLICE_232 (from cpu_clkgen)
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REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
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ROUTE 6 1.156 R14C16C.Q0 to R12C15A.C1 cpu0/alu/rb_in[8]
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ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
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CTOF_DEL --- 0.495 R12C15A.C1 to R12C15A.F1 SLICE_394
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
ROUTE 1 1.299 R12C15A.F1 to R10C15A.A1 cpu0/alu/alu16/a16/rb_in_i[8]
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ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
C1TOFCO_DE --- 0.889 R10C15A.A1 to R10C15A.FCO cpu0/alu/alu16/a16/SLICE_95
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
ROUTE 1 0.000 R10C15A.FCO to R10C15B.FCI cpu0/alu/alu16/a16/un8_q_out_cry_8
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
FCITOF1_DE --- 0.643 R10C15B.FCI to R10C15B.F1 cpu0/alu/alu16/a16/SLICE_94
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
ROUTE 1 0.986 R10C15B.F1 to R11C15D.A0 cpu0/alu/alu16/a16/un8_q_out[10]
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
CTOF_DEL --- 0.495 R11C15D.A0 to R11C15D.F0 cpu0/alu/SLICE_1213
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
ROUTE 1 1.675 R11C15D.F0 to R11C22B.C1 cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO_0
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
C1TOFCO_DE --- 0.889 R11C22B.C1 to R11C22B.FCO cpu0/alu/alu16/a16/SLICE_112
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
ROUTE 1 0.000 R11C22B.FCO to R11C22C.FCI cpu0/alu/alu16/a16/q_out_2_cry_10
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
FCITOF0_DE --- 0.585 R11C22C.FCI to R11C22C.F0 cpu0/alu/alu16/a16/SLICE_111
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
ROUTE 1 1.072 R11C22C.F0 to R7C22D.D0 cpu0/alu/alu16/a16/N_2324
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
CTOF_DEL --- 0.495 R7C22D.D0 to R7C22D.F0 cpu0/alu/alu16/SLICE_986
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
ROUTE 1 0.436 R7C22D.F0 to R7C22D.C1 cpu0/alu/alu16/arith_q[11]
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
CTOF_DEL --- 0.495 R7C22D.C1 to R7C22D.F1 cpu0/alu/alu16/SLICE_986
|
FCITOF1_DE --- 0.643 R19C19B.FCI to R19C19B.F1 cpu0/regs/ea/SLICE_40
|
ROUTE 1 0.958 R7C22D.F1 to R10C22C.D1 cpu0/alu/alu16/N_2298
|
ROUTE 4 2.307 R19C19B.F1 to R16C30C.C1 cpu0/regs_o_eamem_addr[10]
|
CTOF_DEL --- 0.495 R10C22C.D1 to R10C22C.F1 cpu0/alu/alu16/SLICE_1001
|
CTOF_DEL --- 0.495 R16C30C.C1 to R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
|
ROUTE 2 1.032 R10C22C.F1 to R12C22D.B1 cpu0/alu/q16_out[11]
|
ROUTE 1 1.023 R16C30C.F1 to R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
|
CTOF_DEL --- 0.495 R12C22D.B1 to R12C22D.F1 cpu0/alu/SLICE_1236
|
CTOF_DEL --- 0.495 R14C30D.B0 to R14C30D.F0 cpu0/alu/alu16/SLICE_1054
|
ROUTE 2 0.635 R12C22D.F1 to R12C22A.D1 cpu0/datamux_o_dest[11]
|
ROUTE 2 1.640 R14C30D.F0 to R12C24A.A0 cpu0/datamux_o_dest[10]
|
CTOF_DEL --- 0.495 R12C22A.D1 to R12C22A.F1 cpu0/regs/SLICE_941
|
CTOF_DEL --- 0.495 R12C24A.A0 to R12C24A.F0 cpu0/regs/SLICE_362
|
ROUTE 6 1.479 R12C22A.F1 to R14C19C.D0 cpu0/regs/left_1[11]
|
ROUTE 6 0.780 R12C24A.F0 to R11C24B.C0 cpu0/regs/left_1[10]
|
CTOF_DEL --- 0.495 R14C19C.D0 to R14C19C.F0 cpu0/regs/SLICE_1193
|
CTOF_DEL --- 0.495 R11C24B.C0 to R11C24B.F0 cpu0/regs/SLICE_1191
|
ROUTE 1 1.035 R14C19C.F0 to R12C19D.D1 cpu0/regs/N_290
|
ROUTE 1 0.958 R11C24B.F0 to R10C23D.D1 cpu0/regs/N_289
|
CTOF_DEL --- 0.495 R12C19D.D1 to R12C19D.F1 cpu0/regs/SLICE_914
|
CTOF_DEL --- 0.495 R10C23D.D1 to R10C23D.F1 cpu0/regs/SLICE_949
|
ROUTE 1 0.436 R12C19D.F1 to R12C19D.C0 cpu0/regs/SU_16[11]
|
ROUTE 1 0.436 R10C23D.F1 to R10C23D.C0 cpu0/regs/SU_16[10]
|
CTOF_DEL --- 0.495 R12C19D.C0 to R12C19D.F0 cpu0/regs/SLICE_914
|
CTOF_DEL --- 0.495 R10C23D.C0 to R10C23D.F0 cpu0/regs/SLICE_949
|
ROUTE 1 1.476 R12C19D.F0 to R10C19C.C1 cpu0/regs/SU_216_i1_mux
|
ROUTE 1 1.506 R10C23D.F0 to R11C23C.C0 cpu0/regs/SU_217_i1_mux
|
C1TOFCO_DE --- 0.889 R10C19C.C1 to R10C19C.FCO cpu0/regs/SLICE_66
|
C0TOFCO_DE --- 1.023 R11C23C.C0 to R11C23C.FCO cpu0/regs/SLICE_57
|
ROUTE 1 0.000 R10C19C.FCO to R10C19D.FCI cpu0/regs/SU_cry[11]
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
FCITOFCO_D --- 0.162 R10C19D.FCI to R10C19D.FCO cpu0/regs/SLICE_65
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
ROUTE 1 0.000 R10C19D.FCO to R10C20A.FCI cpu0/regs/SU_cry[13]
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
FCITOF1_DE --- 0.643 R10C20A.FCI to R10C20A.F1 cpu0/regs/SLICE_64
|
FCITOF0_DE --- 0.585 R11C24A.FCI to R11C24A.F0 cpu0/regs/SLICE_55
|
ROUTE 1 0.000 R10C20A.F1 to R10C20A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
|
ROUTE 1 0.000 R11C24A.F0 to R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
|
--------
|
--------
|
23.777 (42.5% logic, 57.5% route), 18 logic levels.
|
24.525 (36.0% logic, 64.0% route), 18 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_232:
|
Source Clock Path clk40_i to SLICE_260:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R14C16C.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R10C20A.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 1.091ns
|
Passed: The following path meets requirements by 0.324ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_postbyte[4] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Destination: FF Data in cpu0/k_cpu_addr[10] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
|
|
|
Delay: 23.743ns (33.5% logic, 66.5% route), 18 logic levels.
|
Delay: 24.510ns (36.1% logic, 63.9% route), 19 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
23.743ns physical path delay cpu0/SLICE_1133 to cpu0/SLICE_201 meets
|
24.510ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
25.000ns delay constraint less
|
25.000ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 1.091ns
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.324ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_1133 to cpu0/SLICE_201:
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R14C26D.CLK to R14C26D.Q0 cpu0/SLICE_1133 (from cpu_clkgen)
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
ROUTE 21 1.473 R14C26D.Q0 to R14C25D.B1 cpu0/k_postbyte[4]
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
CTOF_DEL --- 0.495 R14C25D.B1 to R14C25D.F1 cpu0/dec_op/SLICE_1032
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
ROUTE 1 1.525 R14C25D.F1 to R12C26B.A1 cpu0/dec_op/mode76_0
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
CTOF_DEL --- 0.495 R12C26B.A1 to R12C26B.F1 cpu0/dec_op/SLICE_743
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
ROUTE 3 0.984 R12C26B.F1 to R12C26B.A0 cpu0/dec_op/mode76
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
CTOF_DEL --- 0.495 R12C26B.A0 to R12C26B.F0 cpu0/dec_op/SLICE_743
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
ROUTE 1 1.022 R12C26B.F0 to R14C26C.D0 cpu0/dec_op/mode_8_sqmuxa_1_93_2
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
CTOF_DEL --- 0.495 R14C26C.D0 to R14C26C.F0 cpu0/dec_op/SLICE_739
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
ROUTE 2 0.632 R14C26C.F0 to R14C27B.D1 cpu0/dec_op/N_290
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
CTOF_DEL --- 0.495 R14C27B.D1 to R14C27B.F1 cpu0/dec_op/SLICE_700
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
ROUTE 3 2.174 R14C27B.F1 to R15C27B.M0 cpu0/dec_op/un1_mode93
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
MTOOFX_DEL --- 0.376 R15C27B.M0 to R15C27B.OFX0 cpu0/dec_op/un1_mode93_RNIMJAL1/SLICE_420
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
ROUTE 5 2.393 R15C27B.OFX0 to R14C23C.B0 cpu0/mode_7[2]
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
CTOF_DEL --- 0.495 R14C23C.B0 to R14C23C.F0 cpu0/SLICE_592
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
ROUTE 11 0.635 R14C23C.F0 to R14C23D.D0 cpu0/state81
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
CTOF_DEL --- 0.495 R14C23D.D0 to R14C23D.F0 cpu0/dec_op/SLICE_718
|
FCITOFCO_D --- 0.162 R19C19B.FCI to R19C19B.FCO cpu0/regs/ea/SLICE_40
|
ROUTE 3 1.153 R14C23D.F0 to R12C24B.D0 cpu0/un1_cpu_reset_11
|
ROUTE 1 0.000 R19C19B.FCO to R19C19C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
|
CTOF_DEL --- 0.495 R12C24B.D0 to R12C24B.F0 cpu0/SLICE_593
|
FCITOF0_DE --- 0.585 R19C19C.FCI to R19C19C.F0 cpu0/regs/ea/SLICE_39
|
ROUTE 33 1.338 R12C24B.F0 to R10C24A.A1 cpu0/un1_state_122
|
ROUTE 4 2.187 R19C19C.F0 to R16C33D.D0 cpu0/regs_o_eamem_addr[11]
|
C1TOFCO_DE --- 0.889 R10C24A.A1 to R10C24A.FCO cpu0/SLICE_36
|
CTOF_DEL --- 0.495 R16C33D.D0 to R16C33D.F0 cpu0/regs/SLICE_1180
|
ROUTE 1 0.000 R10C24A.FCO to R10C24B.FCI cpu0/un1_k_cpu_addr_1_cry_0
|
ROUTE 1 1.004 R16C33D.F0 to R16C33B.B0 cpu0/regs/ea/N_1415
|
FCITOFCO_D --- 0.162 R10C24B.FCI to R10C24B.FCO cpu0/SLICE_195
|
CTOF_DEL --- 0.495 R16C33B.B0 to R16C33B.F0 cpu0/SLICE_901
|
ROUTE 1 0.000 R10C24B.FCO to R10C24C.FCI cpu0/un1_k_cpu_addr_1_cry_2
|
ROUTE 2 2.179 R16C33B.F0 to R12C24A.D1 cpu0/datamux_o_dest[11]
|
FCITOFCO_D --- 0.162 R10C24C.FCI to R10C24C.FCO cpu0/SLICE_194
|
CTOF_DEL --- 0.495 R12C24A.D1 to R12C24A.F1 cpu0/regs/SLICE_362
|
ROUTE 1 0.000 R10C24C.FCO to R10C24D.FCI cpu0/un1_k_cpu_addr_1_cry_4
|
ROUTE 6 0.790 R12C24A.F1 to R12C26C.C0 cpu0/regs/left_1[11]
|
FCITOFCO_D --- 0.162 R10C24D.FCI to R10C24D.FCO cpu0/SLICE_193
|
CTOF_DEL --- 0.495 R12C26C.C0 to R12C26C.F0 cpu0/regs/SLICE_1192
|
ROUTE 1 0.000 R10C24D.FCO to R10C25A.FCI cpu0/un1_k_cpu_addr_1_cry_6
|
ROUTE 1 0.315 R12C26C.F0 to R12C26A.D1 cpu0/regs/N_290
|
FCITOFCO_D --- 0.162 R10C25A.FCI to R10C25A.FCO cpu0/SLICE_192
|
CTOF_DEL --- 0.495 R12C26A.D1 to R12C26A.F1 cpu0/regs/SLICE_950
|
ROUTE 1 0.000 R10C25A.FCO to R10C25B.FCI cpu0/un1_k_cpu_addr_1_cry_8
|
ROUTE 1 0.626 R12C26A.F1 to R12C26A.D0 cpu0/regs/SU_16[11]
|
FCITOF1_DE --- 0.643 R10C25B.FCI to R10C25B.F1 cpu0/SLICE_191
|
CTOF_DEL --- 0.495 R12C26A.D0 to R12C26A.F0 cpu0/regs/SLICE_950
|
ROUTE 1 1.498 R10C25B.F1 to R12C28C.A0 cpu0/un1_k_cpu_addr_1_cry_9_0_S1
|
ROUTE 1 1.506 R12C26A.F0 to R11C23C.C1 cpu0/regs/SU_218_i1_mux
|
CTOF_DEL --- 0.495 R12C28C.A0 to R12C28C.F0 cpu0/SLICE_1059
|
C1TOFCO_DE --- 0.889 R11C23C.C1 to R11C23C.FCO cpu0/regs/SLICE_57
|
ROUTE 1 0.958 R12C28C.F0 to R11C26A.D0 cpu0/regs/ea/un1_k_cpu_addr_1_m[10]
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
CTOF_DEL --- 0.495 R11C26A.D0 to R11C26A.F0 cpu0/SLICE_201
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
ROUTE 1 0.000 R11C26A.F0 to R11C26A.DI0 cpu0/k_cpu_addr_28[10] (to cpu_clkgen)
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
|
FCITOF1_DE --- 0.643 R11C24A.FCI to R11C24A.F1 cpu0/regs/SLICE_55
|
|
ROUTE 1 0.000 R11C24A.F1 to R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
|
--------
|
--------
|
23.743 (33.5% logic, 66.5% route), 18 logic levels.
|
24.510 (36.1% logic, 63.9% route), 19 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_1133:
|
Source Clock Path clk40_i to SLICE_260:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R14C26D.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/SLICE_201:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R11C26A.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 1.094ns
|
Passed: The following path meets requirements by 0.351ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_postbyte[4] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Destination: FF Data in cpu0/k_cpu_addr[14] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
|
|
|
Delay: 23.740ns (34.9% logic, 65.1% route), 20 logic levels.
|
Delay: 24.483ns (36.2% logic, 63.8% route), 19 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
23.740ns physical path delay cpu0/SLICE_1133 to cpu0/SLICE_203 meets
|
24.483ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
25.000ns delay constraint less
|
25.000ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 1.094ns
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.351ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_1133 to cpu0/SLICE_203:
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R14C26D.CLK to R14C26D.Q0 cpu0/SLICE_1133 (from cpu_clkgen)
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
ROUTE 21 1.473 R14C26D.Q0 to R14C25D.B1 cpu0/k_postbyte[4]
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
CTOF_DEL --- 0.495 R14C25D.B1 to R14C25D.F1 cpu0/dec_op/SLICE_1032
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
ROUTE 1 1.525 R14C25D.F1 to R12C26B.A1 cpu0/dec_op/mode76_0
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
CTOF_DEL --- 0.495 R12C26B.A1 to R12C26B.F1 cpu0/dec_op/SLICE_743
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
ROUTE 3 0.984 R12C26B.F1 to R12C26B.A0 cpu0/dec_op/mode76
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
CTOF_DEL --- 0.495 R12C26B.A0 to R12C26B.F0 cpu0/dec_op/SLICE_743
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
ROUTE 1 1.022 R12C26B.F0 to R14C26C.D0 cpu0/dec_op/mode_8_sqmuxa_1_93_2
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
CTOF_DEL --- 0.495 R14C26C.D0 to R14C26C.F0 cpu0/dec_op/SLICE_739
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
ROUTE 2 0.632 R14C26C.F0 to R14C27B.D1 cpu0/dec_op/N_290
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
CTOF_DEL --- 0.495 R14C27B.D1 to R14C27B.F1 cpu0/dec_op/SLICE_700
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
ROUTE 3 2.174 R14C27B.F1 to R15C27B.M0 cpu0/dec_op/un1_mode93
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
MTOOFX_DEL --- 0.376 R15C27B.M0 to R15C27B.OFX0 cpu0/dec_op/un1_mode93_RNIMJAL1/SLICE_420
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
ROUTE 5 2.393 R15C27B.OFX0 to R14C23C.B0 cpu0/mode_7[2]
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
CTOF_DEL --- 0.495 R14C23C.B0 to R14C23C.F0 cpu0/SLICE_592
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
ROUTE 11 0.635 R14C23C.F0 to R14C23D.D0 cpu0/state81
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
CTOF_DEL --- 0.495 R14C23D.D0 to R14C23D.F0 cpu0/dec_op/SLICE_718
|
FCITOF0_DE --- 0.585 R19C19B.FCI to R19C19B.F0 cpu0/regs/ea/SLICE_40
|
ROUTE 3 1.153 R14C23D.F0 to R12C24B.D0 cpu0/un1_cpu_reset_11
|
ROUTE 4 2.326 R19C19B.F0 to R16C33D.C1 cpu0/regs/regs_o_eamem_addr[9]
|
CTOF_DEL --- 0.495 R12C24B.D0 to R12C24B.F0 cpu0/SLICE_593
|
CTOF_DEL --- 0.495 R16C33D.C1 to R16C33D.F1 cpu0/regs/SLICE_1180
|
ROUTE 33 1.338 R12C24B.F0 to R10C24A.A1 cpu0/un1_state_122
|
ROUTE 1 1.023 R16C33D.F1 to R14C33A.B0 cpu0/regs/N_1413
|
C1TOFCO_DE --- 0.889 R10C24A.A1 to R10C24A.FCO cpu0/SLICE_36
|
CTOF_DEL --- 0.495 R14C33A.B0 to R14C33A.F0 cpu0/SLICE_974
|
ROUTE 1 0.000 R10C24A.FCO to R10C24B.FCI cpu0/un1_k_cpu_addr_1_cry_0
|
ROUTE 2 1.971 R14C33A.F0 to R12C25C.D1 cpu0/datamux_o_dest[9]
|
FCITOFCO_D --- 0.162 R10C24B.FCI to R10C24B.FCO cpu0/SLICE_195
|
CTOF_DEL --- 0.495 R12C25C.D1 to R12C25C.F1 cpu0/regs/SLICE_361
|
ROUTE 1 0.000 R10C24B.FCO to R10C24C.FCI cpu0/un1_k_cpu_addr_1_cry_2
|
ROUTE 6 0.675 R12C25C.F1 to R12C24B.D0 cpu0/regs/left_1[9]
|
FCITOFCO_D --- 0.162 R10C24C.FCI to R10C24C.FCO cpu0/SLICE_194
|
CTOF_DEL --- 0.495 R12C24B.D0 to R12C24B.F0 cpu0/regs/SLICE_1190
|
ROUTE 1 0.000 R10C24C.FCO to R10C24D.FCI cpu0/un1_k_cpu_addr_1_cry_4
|
ROUTE 1 0.986 R12C24B.F0 to R11C24D.A1 cpu0/regs/N_288
|
FCITOFCO_D --- 0.162 R10C24D.FCI to R10C24D.FCO cpu0/SLICE_193
|
CTOF_DEL --- 0.495 R11C24D.A1 to R11C24D.F1 cpu0/regs/SLICE_948
|
ROUTE 1 0.000 R10C24D.FCO to R10C25A.FCI cpu0/un1_k_cpu_addr_1_cry_6
|
ROUTE 1 0.436 R11C24D.F1 to R11C24D.C0 cpu0/regs/SU_16[9]
|
FCITOFCO_D --- 0.162 R10C25A.FCI to R10C25A.FCO cpu0/SLICE_192
|
CTOF_DEL --- 0.495 R11C24D.C0 to R11C24D.F0 cpu0/regs/SLICE_948
|
ROUTE 1 0.000 R10C25A.FCO to R10C25B.FCI cpu0/un1_k_cpu_addr_1_cry_8
|
ROUTE 1 1.163 R11C24D.F0 to R11C23B.C1 cpu0/regs/SU_216_i1_mux
|
FCITOFCO_D --- 0.162 R10C25B.FCI to R10C25B.FCO cpu0/SLICE_191
|
C1TOFCO_DE --- 0.889 R11C23B.C1 to R11C23B.FCO cpu0/regs/SLICE_58
|
ROUTE 1 0.000 R10C25B.FCO to R10C25C.FCI cpu0/un1_k_cpu_addr_1_cry_10
|
ROUTE 1 0.000 R11C23B.FCO to R11C23C.FCI cpu0/regs/SU_cry[9]
|
FCITOFCO_D --- 0.162 R10C25C.FCI to R10C25C.FCO cpu0/SLICE_190
|
FCITOFCO_D --- 0.162 R11C23C.FCI to R11C23C.FCO cpu0/regs/SLICE_57
|
ROUTE 1 0.000 R10C25C.FCO to R10C25D.FCI cpu0/un1_k_cpu_addr_1_cry_12
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
FCITOF1_DE --- 0.643 R10C25D.FCI to R10C25D.F1 cpu0/SLICE_189
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
ROUTE 1 1.385 R10C25D.F1 to R12C28A.D0 cpu0/un1_k_cpu_addr_1_cry_13_0_S1
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
CTOF_DEL --- 0.495 R12C28A.D0 to R12C28A.F0 cpu0/SLICE_1246
|
FCITOF1_DE --- 0.643 R11C24A.FCI to R11C24A.F1 cpu0/regs/SLICE_55
|
ROUTE 1 0.744 R12C28A.F0 to R12C27A.C0 cpu0/alu/un1_k_cpu_addr_1_m[14]
|
ROUTE 1 0.000 R11C24A.F1 to R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
|
CTOF_DEL --- 0.495 R12C27A.C0 to R12C27A.F0 cpu0/SLICE_203
|
|
ROUTE 1 0.000 R12C27A.F0 to R12C27A.DI0 cpu0/k_cpu_addr_28[14] (to cpu_clkgen)
|
|
--------
|
--------
|
23.740 (34.9% logic, 65.1% route), 20 logic levels.
|
24.483 (36.2% logic, 63.8% route), 19 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_1133:
|
Source Clock Path clk40_i to SLICE_260:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R14C26D.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/SLICE_203:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R12C27A.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 1.111ns
|
Passed: The following path meets requirements by 0.362ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/alu/ra_in[0] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_ind_ea[1] (from cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
|
|
|
Delay: 23.723ns (42.1% logic, 57.9% route), 19 logic levels.
|
Delay: 24.472ns (36.3% logic, 63.7% route), 18 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
23.723ns physical path delay cpu0/SLICE_217 to cpu0/regs/SLICE_64 meets
|
24.472ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
25.000ns delay constraint less
|
25.000ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 1.111ns
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.362ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_217 to cpu0/regs/SLICE_64:
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R12C15D.CLK to R12C15D.Q0 cpu0/SLICE_217 (from cpu_clkgen)
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q1 SLICE_260 (from cpu_clkgen)
|
ROUTE 27 2.790 R12C15D.Q0 to R6C24A.A1 cpu0/alu/ra_in[0]
|
ROUTE 30 1.613 R18C14A.Q1 to R18C24D.D1 cpu0/k_ind_ea[1]
|
C1TOFCO_DE --- 0.889 R6C24A.A1 to R6C24A.FCO cpu0/alu/alu8/a8/SLICE_172
|
CTOF_DEL --- 0.495 R18C24D.D1 to R18C24D.F1 cpu0/SLICE_337
|
ROUTE 1 0.000 R6C24A.FCO to R6C24B.FCI cpu0/alu/alu8/a8/q_out_1_cry_0
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
FCITOF1_DE --- 0.643 R6C24B.FCI to R6C24B.F1 cpu0/alu/alu8/a8/SLICE_171
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
ROUTE 1 1.506 R6C24B.F1 to R6C22B.C1 cpu0/alu/alu8/a8/q_out_1[2]
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
C1TOFCO_DE --- 0.889 R6C22B.C1 to R6C22B.FCO cpu0/alu/alu8/a8/SLICE_181
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
ROUTE 1 0.000 R6C22B.FCO to R6C22C.FCI cpu0/alu/alu8/a8/q_out_1_0_cry_2
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
FCITOFCO_D --- 0.162 R6C22C.FCI to R6C22C.FCO cpu0/alu/alu8/a8/SLICE_180
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
ROUTE 1 0.000 R6C22C.FCO to R6C22D.FCI cpu0/alu/alu8/a8/q_out_1_0_cry_4
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
FCITOF1_DE --- 0.643 R6C22D.FCI to R6C22D.F1 cpu0/alu/alu8/a8/SLICE_179
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
ROUTE 1 2.080 R6C22D.F1 to R11C17B.C1 cpu0/alu/alu8/a8/N_2393
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
CTOF_DEL --- 0.495 R11C17B.C1 to R11C17B.F1 cpu0/alu/SLICE_1204
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
ROUTE 1 1.385 R11C17B.F1 to R12C14C.D0 cpu0/alu/alu8/arith_q[6]
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
CTOOFX_DEL --- 0.721 R12C14C.D0 to R12C14C.OFX0 cpu0/alu/alu8/q_out_4[6]/SLICE_560
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
ROUTE 1 0.000 R12C14C.OFX0 to R12C14C.FXB cpu0/alu/alu8/N_159
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
FXTOOFX_DE --- 0.241 R12C14C.FXB to R12C14C.OFX1 cpu0/alu/alu8/q_out_4[6]/SLICE_560
|
FCITOF1_DE --- 0.643 R19C19B.FCI to R19C19B.F1 cpu0/regs/ea/SLICE_40
|
ROUTE 2 1.505 R12C14C.OFX1 to R12C22C.A1 cpu0/alu/q8_out[6]
|
ROUTE 4 2.307 R19C19B.F1 to R16C30C.C1 cpu0/regs_o_eamem_addr[10]
|
CTOOFX_DEL --- 0.721 R12C22C.A1 to R12C22C.OFX0 cpu0/alu/alu16/datamux_o_dest[6]/SLICE_541
|
CTOF_DEL --- 0.495 R16C30C.C1 to R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
|
ROUTE 2 0.772 R12C22C.OFX0 to R12C21A.C0 cpu0/datamux_o_dest[6]
|
ROUTE 1 1.023 R16C30C.F1 to R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
|
CTOF_DEL --- 0.495 R12C21A.C0 to R12C21A.F0 cpu0/regs/SLICE_889
|
CTOF_DEL --- 0.495 R14C30D.B0 to R14C30D.F0 cpu0/alu/alu16/SLICE_1054
|
ROUTE 9 1.224 R12C21A.F0 to R12C17A.C1 cpu0/regs/left_1[6]
|
ROUTE 2 1.640 R14C30D.F0 to R12C24A.A0 cpu0/datamux_o_dest[10]
|
CTOF_DEL --- 0.495 R12C17A.C1 to R12C17A.F1 cpu0/regs/SLICE_1125
|
CTOF_DEL --- 0.495 R12C24A.A0 to R12C24A.F0 cpu0/regs/SLICE_362
|
ROUTE 1 0.958 R12C17A.F1 to R10C17B.D1 cpu0/regs/N_285
|
ROUTE 6 0.780 R12C24A.F0 to R11C24B.C0 cpu0/regs/left_1[10]
|
CTOF_DEL --- 0.495 R10C17B.D1 to R10C17B.F1 cpu0/regs/SLICE_901
|
CTOF_DEL --- 0.495 R11C24B.C0 to R11C24B.F0 cpu0/regs/SLICE_1191
|
ROUTE 1 0.436 R10C17B.F1 to R10C17B.C0 cpu0/regs/SU_16[6]
|
ROUTE 1 0.958 R11C24B.F0 to R10C23D.D1 cpu0/regs/N_289
|
CTOF_DEL --- 0.495 R10C17B.C0 to R10C17B.F0 cpu0/regs/SLICE_901
|
CTOF_DEL --- 0.495 R10C23D.D1 to R10C23D.F1 cpu0/regs/SLICE_949
|
ROUTE 1 1.079 R10C17B.F0 to R10C19A.C0 cpu0/regs/SU_211_i1_mux
|
ROUTE 1 0.436 R10C23D.F1 to R10C23D.C0 cpu0/regs/SU_16[10]
|
C0TOFCO_DE --- 1.023 R10C19A.C0 to R10C19A.FCO cpu0/regs/SLICE_68
|
CTOF_DEL --- 0.495 R10C23D.C0 to R10C23D.F0 cpu0/regs/SLICE_949
|
ROUTE 1 0.000 R10C19A.FCO to R10C19B.FCI cpu0/regs/SU_cry[7]
|
ROUTE 1 1.506 R10C23D.F0 to R11C23C.C0 cpu0/regs/SU_217_i1_mux
|
FCITOFCO_D --- 0.162 R10C19B.FCI to R10C19B.FCO cpu0/regs/SLICE_67
|
C0TOFCO_DE --- 1.023 R11C23C.C0 to R11C23C.FCO cpu0/regs/SLICE_57
|
ROUTE 1 0.000 R10C19B.FCO to R10C19C.FCI cpu0/regs/SU_cry[9]
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
FCITOFCO_D --- 0.162 R10C19C.FCI to R10C19C.FCO cpu0/regs/SLICE_66
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
ROUTE 1 0.000 R10C19C.FCO to R10C19D.FCI cpu0/regs/SU_cry[11]
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
FCITOFCO_D --- 0.162 R10C19D.FCI to R10C19D.FCO cpu0/regs/SLICE_65
|
FCITOF1_DE --- 0.643 R11C24A.FCI to R11C24A.F1 cpu0/regs/SLICE_55
|
ROUTE 1 0.000 R10C19D.FCO to R10C20A.FCI cpu0/regs/SU_cry[13]
|
ROUTE 1 0.000 R11C24A.F1 to R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
|
FCITOF1_DE --- 0.643 R10C20A.FCI to R10C20A.F1 cpu0/regs/SLICE_64
|
|
ROUTE 1 0.000 R10C20A.F1 to R10C20A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
|
|
--------
|
--------
|
23.723 (42.1% logic, 57.9% route), 19 logic levels.
|
24.472 (36.3% logic, 63.7% route), 18 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_217:
|
Source Clock Path clk40_i to SLICE_260:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R12C15D.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R10C20A.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 1.112ns
|
Passed: The following path meets requirements by 0.382ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/alu/rb_in[1] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SU[14] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SU[14] (to cpu_clkgen +)
|
|
|
Delay: 23.722ns (42.7% logic, 57.3% route), 19 logic levels.
|
Delay: 24.452ns (36.0% logic, 64.0% route), 19 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
23.722ns physical path delay cpu0/SLICE_229 to cpu0/regs/SLICE_64 meets
|
24.452ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
25.000ns delay constraint less
|
25.000ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 1.112ns
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.382ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_229 to cpu0/regs/SLICE_64:
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R12C13B.CLK to R12C13B.Q1 cpu0/SLICE_229 (from cpu_clkgen)
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
ROUTE 26 1.735 R12C13B.Q1 to R10C14B.A0 cpu0/alu/rb_in[1]
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
C0TOFCO_DE --- 1.023 R10C14B.A0 to R10C14B.FCO cpu0/alu/alu16/a16/SLICE_98
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
ROUTE 1 0.000 R10C14B.FCO to R10C14C.FCI cpu0/alu/alu16/a16/un8_q_out_cry_2
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
FCITOF1_DE --- 0.643 R10C14C.FCI to R10C14C.F1 cpu0/alu/alu16/a16/SLICE_97
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
ROUTE 1 1.385 R10C14C.F1 to R11C17C.D0 cpu0/alu/alu16/a16/un8_q_out[4]
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
CTOF_DEL --- 0.495 R11C17C.D0 to R11C17C.F0 cpu0/alu/SLICE_1151
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
ROUTE 1 1.675 R11C17C.F0 to R11C21C.C1 cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO_0_0
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
C1TOFCO_DE --- 0.889 R11C21C.C1 to R11C21C.FCO cpu0/alu/alu16/a16/SLICE_115
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
ROUTE 1 0.000 R11C21C.FCO to R11C21D.FCI cpu0/alu/alu16/a16/q_out_2_cry_4
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
FCITOF0_DE --- 0.585 R11C21D.FCI to R11C21D.F0 cpu0/alu/alu16/a16/SLICE_114
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
ROUTE 1 1.705 R11C21D.F0 to R7C15D.C0 cpu0/alu/alu16/a16/N_2261
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
CTOF_DEL --- 0.495 R7C15D.C0 to R7C15D.F0 cpu0/alu/alu16/SLICE_1209
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
ROUTE 1 0.958 R7C15D.F0 to R9C15A.D1 cpu0/alu/alu16/arith_q[5]
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
CTOOFX_DEL --- 0.721 R9C15A.D1 to R9C15A.OFX0 cpu0/alu/alu16/q_out[5]/SLICE_537
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
ROUTE 2 1.285 R9C15A.OFX0 to R9C22B.C1 cpu0/alu/q16_out[5]
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
CTOOFX_DEL --- 0.721 R9C22B.C1 to R9C22B.OFX0 cpu0/alu/alu16/datamux_o_dest[5]/SLICE_540
|
FCITOFCO_D --- 0.162 R19C19B.FCI to R19C19B.FCO cpu0/regs/ea/SLICE_40
|
ROUTE 2 1.392 R9C22B.OFX0 to R11C20D.D0 cpu0/datamux_o_dest[5]
|
ROUTE 1 0.000 R19C19B.FCO to R19C19C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
|
CTOF_DEL --- 0.495 R11C20D.D0 to R11C20D.F0 cpu0/regs/SLICE_890
|
FCITOF0_DE --- 0.585 R19C19C.FCI to R19C19C.F0 cpu0/regs/ea/SLICE_39
|
ROUTE 9 0.798 R11C20D.F0 to R9C20D.C1 cpu0/regs/left_1[5]
|
ROUTE 4 2.187 R19C19C.F0 to R16C33D.D0 cpu0/regs_o_eamem_addr[11]
|
CTOF_DEL --- 0.495 R9C20D.C1 to R9C20D.F1 cpu0/regs/SLICE_1124
|
CTOF_DEL --- 0.495 R16C33D.D0 to R16C33D.F0 cpu0/regs/SLICE_1180
|
ROUTE 1 0.958 R9C20D.F1 to R8C18A.D1 cpu0/regs/N_284
|
ROUTE 1 1.004 R16C33D.F0 to R16C33B.B0 cpu0/regs/ea/N_1415
|
CTOF_DEL --- 0.495 R8C18A.D1 to R8C18A.F1 cpu0/regs/SLICE_900
|
CTOF_DEL --- 0.495 R16C33B.B0 to R16C33B.F0 cpu0/SLICE_901
|
ROUTE 1 0.626 R8C18A.F1 to R8C18A.D0 cpu0/regs/SU_16[5]
|
ROUTE 2 2.179 R16C33B.F0 to R12C24A.D1 cpu0/datamux_o_dest[11]
|
CTOF_DEL --- 0.495 R8C18A.D0 to R8C18A.F0 cpu0/regs/SLICE_900
|
CTOF_DEL --- 0.495 R12C24A.D1 to R12C24A.F1 cpu0/regs/SLICE_362
|
ROUTE 1 1.079 R8C18A.F0 to R10C18D.C1 cpu0/regs/SU_210_i1_mux
|
ROUTE 6 0.790 R12C24A.F1 to R12C26C.C0 cpu0/regs/left_1[11]
|
C1TOFCO_DE --- 0.889 R10C18D.C1 to R10C18D.FCO cpu0/regs/SLICE_69
|
CTOF_DEL --- 0.495 R12C26C.C0 to R12C26C.F0 cpu0/regs/SLICE_1192
|
ROUTE 1 0.000 R10C18D.FCO to R10C19A.FCI cpu0/regs/SU_cry[5]
|
ROUTE 1 0.315 R12C26C.F0 to R12C26A.D1 cpu0/regs/N_290
|
FCITOFCO_D --- 0.162 R10C19A.FCI to R10C19A.FCO cpu0/regs/SLICE_68
|
CTOF_DEL --- 0.495 R12C26A.D1 to R12C26A.F1 cpu0/regs/SLICE_950
|
ROUTE 1 0.000 R10C19A.FCO to R10C19B.FCI cpu0/regs/SU_cry[7]
|
ROUTE 1 0.626 R12C26A.F1 to R12C26A.D0 cpu0/regs/SU_16[11]
|
FCITOFCO_D --- 0.162 R10C19B.FCI to R10C19B.FCO cpu0/regs/SLICE_67
|
CTOF_DEL --- 0.495 R12C26A.D0 to R12C26A.F0 cpu0/regs/SLICE_950
|
ROUTE 1 0.000 R10C19B.FCO to R10C19C.FCI cpu0/regs/SU_cry[9]
|
ROUTE 1 1.506 R12C26A.F0 to R11C23C.C1 cpu0/regs/SU_218_i1_mux
|
FCITOFCO_D --- 0.162 R10C19C.FCI to R10C19C.FCO cpu0/regs/SLICE_66
|
C1TOFCO_DE --- 0.889 R11C23C.C1 to R11C23C.FCO cpu0/regs/SLICE_57
|
ROUTE 1 0.000 R10C19C.FCO to R10C19D.FCI cpu0/regs/SU_cry[11]
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
FCITOFCO_D --- 0.162 R10C19D.FCI to R10C19D.FCO cpu0/regs/SLICE_65
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
ROUTE 1 0.000 R10C19D.FCO to R10C20A.FCI cpu0/regs/SU_cry[13]
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
FCITOF0_DE --- 0.585 R10C20A.FCI to R10C20A.F0 cpu0/regs/SLICE_64
|
FCITOF0_DE --- 0.585 R11C24A.FCI to R11C24A.F0 cpu0/regs/SLICE_55
|
ROUTE 1 0.000 R10C20A.F0 to R10C20A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
|
ROUTE 1 0.000 R11C24A.F0 to R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
|
--------
|
--------
|
23.722 (42.7% logic, 57.3% route), 19 logic levels.
|
24.452 (36.0% logic, 64.0% route), 19 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_229:
|
Source Clock Path clk40_i to SLICE_260:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R12C13B.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R10C20A.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 1.112ns
|
Passed: The following path meets requirements by 0.391ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_postbyte[4] (from cpu_clkgen +)
|
Source: FF Q cpu0/regs/IY_pipe_14 (from cpu_clkgen +)
|
Destination: FF Data in cpu0/k_cpu_addr[10] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
|
|
|
Delay: 23.722ns (33.4% logic, 66.6% route), 17 logic levels.
|
Delay: 24.443ns (39.4% logic, 60.6% route), 20 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
23.722ns physical path delay cpu0/SLICE_1133 to cpu0/SLICE_201 meets
|
24.443ns physical path delay cpu0/regs/SLICE_323 to cpu0/regs/SLICE_55 meets
|
25.000ns delay constraint less
|
25.000ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 1.112ns
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.391ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_1133 to cpu0/SLICE_201:
|
Data path cpu0/regs/SLICE_323 to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R14C26D.CLK to R14C26D.Q0 cpu0/SLICE_1133 (from cpu_clkgen)
|
REG_DEL --- 0.452 R16C22A.CLK to R16C22A.Q0 cpu0/regs/SLICE_323 (from cpu_clkgen)
|
ROUTE 21 1.473 R14C26D.Q0 to R14C25D.B1 cpu0/k_postbyte[4]
|
ROUTE 16 1.390 R16C22A.Q0 to R16C25A.A1 cpu0/regs/IY_1_sqmuxaf
|
CTOF_DEL --- 0.495 R14C25D.B1 to R14C25D.F1 cpu0/dec_op/SLICE_1032
|
CTOF_DEL --- 0.495 R16C25A.A1 to R16C25A.F1 cpu0/regs/SLICE_1012
|
ROUTE 1 1.525 R14C25D.F1 to R12C26B.A1 cpu0/dec_op/mode76_0
|
ROUTE 1 0.693 R16C25A.F1 to R16C25A.B0 cpu0/regs/N_665
|
CTOF_DEL --- 0.495 R12C26B.A1 to R12C26B.F1 cpu0/dec_op/SLICE_743
|
CTOF_DEL --- 0.495 R16C25A.B0 to R16C25A.F0 cpu0/regs/SLICE_1012
|
ROUTE 3 0.984 R12C26B.F1 to R12C26B.A0 cpu0/dec_op/mode76
|
ROUTE 3 1.435 R16C25A.F0 to R21C25B.C1 cpu0/regs/IY[0]
|
CTOF_DEL --- 0.495 R12C26B.A0 to R12C26B.F0 cpu0/dec_op/SLICE_743
|
CTOOFX_DEL --- 0.721 R21C25B.C1 to R21C25B.OFX0 cpu0/regs/ea/ea_reg_3[0]/SLICE_511
|
ROUTE 1 1.022 R12C26B.F0 to R14C26C.D0 cpu0/dec_op/mode_8_sqmuxa_1_93_2
|
ROUTE 5 1.487 R21C25B.OFX0 to R21C19D.D0 cpu0/regs/ea_reg[0]
|
CTOF_DEL --- 0.495 R14C26C.D0 to R14C26C.F0 cpu0/dec_op/SLICE_739
|
CTOF_DEL --- 0.495 R21C19D.D0 to R21C19D.F0 cpu0/regs/SLICE_917
|
ROUTE 2 0.632 R14C26C.F0 to R14C27B.D1 cpu0/dec_op/N_290
|
ROUTE 2 1.152 R21C19D.F0 to R19C18A.C1 cpu0/regs/ea/N_72
|
CTOF_DEL --- 0.495 R14C27B.D1 to R14C27B.F1 cpu0/dec_op/SLICE_700
|
C1TOFCO_DE --- 0.889 R19C18A.C1 to R19C18A.FCO cpu0/regs/ea/SLICE_45
|
ROUTE 3 2.174 R14C27B.F1 to R15C27B.M0 cpu0/dec_op/un1_mode93
|
ROUTE 1 0.000 R19C18A.FCO to R19C18B.FCI cpu0/regs/ea/eamem_addr_o_cry_0
|
MTOOFX_DEL --- 0.376 R15C27B.M0 to R15C27B.OFX0 cpu0/dec_op/un1_mode93_RNIMJAL1/SLICE_420
|
FCITOFCO_D --- 0.162 R19C18B.FCI to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
ROUTE 5 2.393 R15C27B.OFX0 to R14C23C.B0 cpu0/mode_7[2]
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
CTOF_DEL --- 0.495 R14C23C.B0 to R14C23C.F0 cpu0/SLICE_592
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
ROUTE 11 0.635 R14C23C.F0 to R14C23D.D0 cpu0/state81
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
CTOF_DEL --- 0.495 R14C23D.D0 to R14C23D.F0 cpu0/dec_op/SLICE_718
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
ROUTE 3 1.153 R14C23D.F0 to R12C24B.D0 cpu0/un1_cpu_reset_11
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
CTOF_DEL --- 0.495 R12C24B.D0 to R12C24B.F0 cpu0/SLICE_593
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
ROUTE 33 1.345 R12C24B.F0 to R10C24B.A0 cpu0/un1_state_122
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
C0TOFCO_DE --- 1.023 R10C24B.A0 to R10C24B.FCO cpu0/SLICE_195
|
FCITOF1_DE --- 0.643 R19C19B.FCI to R19C19B.F1 cpu0/regs/ea/SLICE_40
|
ROUTE 1 0.000 R10C24B.FCO to R10C24C.FCI cpu0/un1_k_cpu_addr_1_cry_2
|
ROUTE 4 2.307 R19C19B.F1 to R16C30C.C1 cpu0/regs_o_eamem_addr[10]
|
FCITOFCO_D --- 0.162 R10C24C.FCI to R10C24C.FCO cpu0/SLICE_194
|
CTOF_DEL --- 0.495 R16C30C.C1 to R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
|
ROUTE 1 0.000 R10C24C.FCO to R10C24D.FCI cpu0/un1_k_cpu_addr_1_cry_4
|
ROUTE 1 1.023 R16C30C.F1 to R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
|
FCITOFCO_D --- 0.162 R10C24D.FCI to R10C24D.FCO cpu0/SLICE_193
|
CTOF_DEL --- 0.495 R14C30D.B0 to R14C30D.F0 cpu0/alu/alu16/SLICE_1054
|
ROUTE 1 0.000 R10C24D.FCO to R10C25A.FCI cpu0/un1_k_cpu_addr_1_cry_6
|
ROUTE 2 1.640 R14C30D.F0 to R12C24A.A0 cpu0/datamux_o_dest[10]
|
FCITOFCO_D --- 0.162 R10C25A.FCI to R10C25A.FCO cpu0/SLICE_192
|
CTOF_DEL --- 0.495 R12C24A.A0 to R12C24A.F0 cpu0/regs/SLICE_362
|
ROUTE 1 0.000 R10C25A.FCO to R10C25B.FCI cpu0/un1_k_cpu_addr_1_cry_8
|
ROUTE 6 0.780 R12C24A.F0 to R11C24B.C0 cpu0/regs/left_1[10]
|
FCITOF1_DE --- 0.643 R10C25B.FCI to R10C25B.F1 cpu0/SLICE_191
|
CTOF_DEL --- 0.495 R11C24B.C0 to R11C24B.F0 cpu0/regs/SLICE_1191
|
ROUTE 1 1.498 R10C25B.F1 to R12C28C.A0 cpu0/un1_k_cpu_addr_1_cry_9_0_S1
|
ROUTE 1 0.958 R11C24B.F0 to R10C23D.D1 cpu0/regs/N_289
|
CTOF_DEL --- 0.495 R12C28C.A0 to R12C28C.F0 cpu0/SLICE_1059
|
CTOF_DEL --- 0.495 R10C23D.D1 to R10C23D.F1 cpu0/regs/SLICE_949
|
ROUTE 1 0.958 R12C28C.F0 to R11C26A.D0 cpu0/regs/ea/un1_k_cpu_addr_1_m[10]
|
ROUTE 1 0.436 R10C23D.F1 to R10C23D.C0 cpu0/regs/SU_16[10]
|
CTOF_DEL --- 0.495 R11C26A.D0 to R11C26A.F0 cpu0/SLICE_201
|
CTOF_DEL --- 0.495 R10C23D.C0 to R10C23D.F0 cpu0/regs/SLICE_949
|
ROUTE 1 0.000 R11C26A.F0 to R11C26A.DI0 cpu0/k_cpu_addr_28[10] (to cpu_clkgen)
|
ROUTE 1 1.506 R10C23D.F0 to R11C23C.C0 cpu0/regs/SU_217_i1_mux
|
|
C0TOFCO_DE --- 1.023 R11C23C.C0 to R11C23C.FCO cpu0/regs/SLICE_57
|
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
|
FCITOF1_DE --- 0.643 R11C24A.FCI to R11C24A.F1 cpu0/regs/SLICE_55
|
|
ROUTE 1 0.000 R11C24A.F1 to R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
|
--------
|
--------
|
23.722 (33.4% logic, 66.6% route), 17 logic levels.
|
24.443 (39.4% logic, 60.6% route), 20 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_1133:
|
Source Clock Path clk40_i to cpu0/regs/SLICE_323:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R14C26D.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R16C22A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/SLICE_201:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R11C26A.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 1.115ns
|
Passed: The following path meets requirements by 0.396ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/alu/rb_in[8] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SU[14] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SS[15] (to cpu_clkgen +)
|
|
|
Delay: 23.719ns (42.3% logic, 57.7% route), 18 logic levels.
|
Delay: 24.438ns (36.4% logic, 63.6% route), 18 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
23.719ns physical path delay cpu0/SLICE_232 to cpu0/regs/SLICE_64 meets
|
24.438ns physical path delay SLICE_260 to cpu0/regs/SLICE_64 meets
|
25.000ns delay constraint less
|
25.000ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 1.115ns
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.396ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_232 to cpu0/regs/SLICE_64:
|
Data path SLICE_260 to cpu0/regs/SLICE_64:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R14C16C.CLK to R14C16C.Q0 cpu0/SLICE_232 (from cpu_clkgen)
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
ROUTE 6 1.156 R14C16C.Q0 to R12C15A.C1 cpu0/alu/rb_in[8]
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
CTOF_DEL --- 0.495 R12C15A.C1 to R12C15A.F1 SLICE_394
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
ROUTE 1 1.299 R12C15A.F1 to R10C15A.A1 cpu0/alu/alu16/a16/rb_in_i[8]
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
C1TOFCO_DE --- 0.889 R10C15A.A1 to R10C15A.FCO cpu0/alu/alu16/a16/SLICE_95
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
ROUTE 1 0.000 R10C15A.FCO to R10C15B.FCI cpu0/alu/alu16/a16/un8_q_out_cry_8
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
FCITOF1_DE --- 0.643 R10C15B.FCI to R10C15B.F1 cpu0/alu/alu16/a16/SLICE_94
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
ROUTE 1 0.986 R10C15B.F1 to R11C15D.A0 cpu0/alu/alu16/a16/un8_q_out[10]
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
CTOF_DEL --- 0.495 R11C15D.A0 to R11C15D.F0 cpu0/alu/SLICE_1213
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
ROUTE 1 1.675 R11C15D.F0 to R11C22B.C1 cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO_0
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
C1TOFCO_DE --- 0.889 R11C22B.C1 to R11C22B.FCO cpu0/alu/alu16/a16/SLICE_112
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
ROUTE 1 0.000 R11C22B.FCO to R11C22C.FCI cpu0/alu/alu16/a16/q_out_2_cry_10
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
FCITOF0_DE --- 0.585 R11C22C.FCI to R11C22C.F0 cpu0/alu/alu16/a16/SLICE_111
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
ROUTE 1 1.072 R11C22C.F0 to R7C22D.D0 cpu0/alu/alu16/a16/N_2324
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
CTOF_DEL --- 0.495 R7C22D.D0 to R7C22D.F0 cpu0/alu/alu16/SLICE_986
|
FCITOF1_DE --- 0.643 R19C19A.FCI to R19C19A.F1 cpu0/regs/ea/SLICE_41
|
ROUTE 1 0.436 R7C22D.F0 to R7C22D.C1 cpu0/alu/alu16/arith_q[11]
|
ROUTE 4 2.403 R19C19A.F1 to R16C32D.D0 cpu0/regs/ea/regs_o_eamem_addr[8]
|
CTOF_DEL --- 0.495 R7C22D.C1 to R7C22D.F1 cpu0/alu/alu16/SLICE_986
|
CTOF_DEL --- 0.495 R16C32D.D0 to R16C32D.F0 cpu0/regs/SLICE_922
|
ROUTE 1 0.958 R7C22D.F1 to R10C22C.D1 cpu0/alu/alu16/N_2298
|
ROUTE 1 0.645 R16C32D.F0 to R14C32C.D0 cpu0/regs/ea/N_1412
|
CTOF_DEL --- 0.495 R10C22C.D1 to R10C22C.F1 cpu0/alu/alu16/SLICE_1001
|
CTOF_DEL --- 0.495 R14C32C.D0 to R14C32C.F0 cpu0/SLICE_900
|
ROUTE 2 1.032 R10C22C.F1 to R12C22D.B1 cpu0/alu/q16_out[11]
|
ROUTE 2 1.704 R14C32C.F0 to R12C25C.D0 cpu0/datamux_o_dest[8]
|
CTOF_DEL --- 0.495 R12C22D.B1 to R12C22D.F1 cpu0/alu/SLICE_1236
|
CTOF_DEL --- 0.495 R12C25C.D0 to R12C25C.F0 cpu0/regs/SLICE_361
|
ROUTE 2 0.635 R12C22D.F1 to R12C22A.D1 cpu0/datamux_o_dest[11]
|
ROUTE 6 0.469 R12C25C.F0 to R12C25B.C1 cpu0/regs/left_1[8]
|
CTOF_DEL --- 0.495 R12C22A.D1 to R12C22A.F1 cpu0/regs/SLICE_941
|
CTOF_DEL --- 0.495 R12C25B.C1 to R12C25B.F1 cpu0/regs/SLICE_1189
|
ROUTE 6 1.479 R12C22A.F1 to R14C19C.D0 cpu0/regs/left_1[11]
|
ROUTE 1 1.088 R12C25B.F1 to R14C25C.B1 cpu0/regs/N_251
|
CTOF_DEL --- 0.495 R14C19C.D0 to R14C19C.F0 cpu0/regs/SLICE_1193
|
CTOF_DEL --- 0.495 R14C25C.B1 to R14C25C.F1 cpu0/regs/SLICE_955
|
ROUTE 1 1.035 R14C19C.F0 to R12C19D.D1 cpu0/regs/N_290
|
ROUTE 1 0.626 R14C25C.F1 to R14C25C.D0 cpu0/regs/SS_16[8]
|
CTOF_DEL --- 0.495 R12C19D.D1 to R12C19D.F1 cpu0/regs/SLICE_914
|
CTOF_DEL --- 0.495 R14C25C.D0 to R14C25C.F0 cpu0/regs/SLICE_955
|
ROUTE 1 0.436 R12C19D.F1 to R12C19D.C0 cpu0/regs/SU_16[11]
|
ROUTE 1 1.570 R14C25C.F0 to R10C26B.C0 cpu0/regs/SS_231_i1_mux
|
CTOF_DEL --- 0.495 R12C19D.C0 to R12C19D.F0 cpu0/regs/SLICE_914
|
C0TOFCO_DE --- 1.023 R10C26B.C0 to R10C26B.FCO cpu0/regs/SLICE_67
|
ROUTE 1 1.476 R12C19D.F0 to R10C19C.C1 cpu0/regs/SU_216_i1_mux
|
ROUTE 1 0.000 R10C26B.FCO to R10C26C.FCI cpu0/regs/SS_cry[9]
|
C1TOFCO_DE --- 0.889 R10C19C.C1 to R10C19C.FCO cpu0/regs/SLICE_66
|
FCITOFCO_D --- 0.162 R10C26C.FCI to R10C26C.FCO cpu0/regs/SLICE_66
|
ROUTE 1 0.000 R10C19C.FCO to R10C19D.FCI cpu0/regs/SU_cry[11]
|
ROUTE 1 0.000 R10C26C.FCO to R10C26D.FCI cpu0/regs/SS_cry[11]
|
FCITOFCO_D --- 0.162 R10C19D.FCI to R10C19D.FCO cpu0/regs/SLICE_65
|
FCITOFCO_D --- 0.162 R10C26D.FCI to R10C26D.FCO cpu0/regs/SLICE_65
|
ROUTE 1 0.000 R10C19D.FCO to R10C20A.FCI cpu0/regs/SU_cry[13]
|
ROUTE 1 0.000 R10C26D.FCO to R10C27A.FCI cpu0/regs/SS_cry[13]
|
FCITOF0_DE --- 0.585 R10C20A.FCI to R10C20A.F0 cpu0/regs/SLICE_64
|
FCITOF1_DE --- 0.643 R10C27A.FCI to R10C27A.F1 cpu0/regs/SLICE_64
|
ROUTE 1 0.000 R10C20A.F0 to R10C20A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
|
ROUTE 1 0.000 R10C27A.F1 to R10C27A.DI1 cpu0/regs/SS_s[15] (to cpu_clkgen)
|
--------
|
--------
|
23.719 (42.3% logic, 57.7% route), 18 logic levels.
|
24.438 (36.4% logic, 63.6% route), 18 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_232:
|
Source Clock Path clk40_i to SLICE_260:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R14C16C.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R10C20A.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R10C27A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 1.115ns
|
Passed: The following path meets requirements by 0.409ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_postbyte[4] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Destination: FF Data in cpu0/k_cpu_addr[14] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SU[14] (to cpu_clkgen +)
|
|
|
Delay: 23.719ns (34.8% logic, 65.2% route), 19 logic levels.
|
Delay: 24.425ns (36.0% logic, 64.0% route), 19 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
23.719ns physical path delay cpu0/SLICE_1133 to cpu0/SLICE_203 meets
|
24.425ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
25.000ns delay constraint less
|
25.000ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 1.115ns
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.409ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_1133 to cpu0/SLICE_203:
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R14C26D.CLK to R14C26D.Q0 cpu0/SLICE_1133 (from cpu_clkgen)
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
ROUTE 21 1.473 R14C26D.Q0 to R14C25D.B1 cpu0/k_postbyte[4]
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
CTOF_DEL --- 0.495 R14C25D.B1 to R14C25D.F1 cpu0/dec_op/SLICE_1032
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
ROUTE 1 1.525 R14C25D.F1 to R12C26B.A1 cpu0/dec_op/mode76_0
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
CTOF_DEL --- 0.495 R12C26B.A1 to R12C26B.F1 cpu0/dec_op/SLICE_743
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
ROUTE 3 0.984 R12C26B.F1 to R12C26B.A0 cpu0/dec_op/mode76
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
CTOF_DEL --- 0.495 R12C26B.A0 to R12C26B.F0 cpu0/dec_op/SLICE_743
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
ROUTE 1 1.022 R12C26B.F0 to R14C26C.D0 cpu0/dec_op/mode_8_sqmuxa_1_93_2
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
CTOF_DEL --- 0.495 R14C26C.D0 to R14C26C.F0 cpu0/dec_op/SLICE_739
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
ROUTE 2 0.632 R14C26C.F0 to R14C27B.D1 cpu0/dec_op/N_290
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
CTOF_DEL --- 0.495 R14C27B.D1 to R14C27B.F1 cpu0/dec_op/SLICE_700
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
ROUTE 3 2.174 R14C27B.F1 to R15C27B.M0 cpu0/dec_op/un1_mode93
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
MTOOFX_DEL --- 0.376 R15C27B.M0 to R15C27B.OFX0 cpu0/dec_op/un1_mode93_RNIMJAL1/SLICE_420
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
ROUTE 5 2.393 R15C27B.OFX0 to R14C23C.B0 cpu0/mode_7[2]
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
CTOF_DEL --- 0.495 R14C23C.B0 to R14C23C.F0 cpu0/SLICE_592
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
ROUTE 11 0.635 R14C23C.F0 to R14C23D.D0 cpu0/state81
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
CTOF_DEL --- 0.495 R14C23D.D0 to R14C23D.F0 cpu0/dec_op/SLICE_718
|
FCITOF0_DE --- 0.585 R19C19B.FCI to R19C19B.F0 cpu0/regs/ea/SLICE_40
|
ROUTE 3 1.153 R14C23D.F0 to R12C24B.D0 cpu0/un1_cpu_reset_11
|
ROUTE 4 2.326 R19C19B.F0 to R16C33D.C1 cpu0/regs/regs_o_eamem_addr[9]
|
CTOF_DEL --- 0.495 R12C24B.D0 to R12C24B.F0 cpu0/SLICE_593
|
CTOF_DEL --- 0.495 R16C33D.C1 to R16C33D.F1 cpu0/regs/SLICE_1180
|
ROUTE 33 1.345 R12C24B.F0 to R10C24B.A0 cpu0/un1_state_122
|
ROUTE 1 1.023 R16C33D.F1 to R14C33A.B0 cpu0/regs/N_1413
|
C0TOFCO_DE --- 1.023 R10C24B.A0 to R10C24B.FCO cpu0/SLICE_195
|
CTOF_DEL --- 0.495 R14C33A.B0 to R14C33A.F0 cpu0/SLICE_974
|
ROUTE 1 0.000 R10C24B.FCO to R10C24C.FCI cpu0/un1_k_cpu_addr_1_cry_2
|
ROUTE 2 1.971 R14C33A.F0 to R12C25C.D1 cpu0/datamux_o_dest[9]
|
FCITOFCO_D --- 0.162 R10C24C.FCI to R10C24C.FCO cpu0/SLICE_194
|
CTOF_DEL --- 0.495 R12C25C.D1 to R12C25C.F1 cpu0/regs/SLICE_361
|
ROUTE 1 0.000 R10C24C.FCO to R10C24D.FCI cpu0/un1_k_cpu_addr_1_cry_4
|
ROUTE 6 0.675 R12C25C.F1 to R12C24B.D0 cpu0/regs/left_1[9]
|
FCITOFCO_D --- 0.162 R10C24D.FCI to R10C24D.FCO cpu0/SLICE_193
|
CTOF_DEL --- 0.495 R12C24B.D0 to R12C24B.F0 cpu0/regs/SLICE_1190
|
ROUTE 1 0.000 R10C24D.FCO to R10C25A.FCI cpu0/un1_k_cpu_addr_1_cry_6
|
ROUTE 1 0.986 R12C24B.F0 to R11C24D.A1 cpu0/regs/N_288
|
FCITOFCO_D --- 0.162 R10C25A.FCI to R10C25A.FCO cpu0/SLICE_192
|
CTOF_DEL --- 0.495 R11C24D.A1 to R11C24D.F1 cpu0/regs/SLICE_948
|
ROUTE 1 0.000 R10C25A.FCO to R10C25B.FCI cpu0/un1_k_cpu_addr_1_cry_8
|
ROUTE 1 0.436 R11C24D.F1 to R11C24D.C0 cpu0/regs/SU_16[9]
|
FCITOFCO_D --- 0.162 R10C25B.FCI to R10C25B.FCO cpu0/SLICE_191
|
CTOF_DEL --- 0.495 R11C24D.C0 to R11C24D.F0 cpu0/regs/SLICE_948
|
ROUTE 1 0.000 R10C25B.FCO to R10C25C.FCI cpu0/un1_k_cpu_addr_1_cry_10
|
ROUTE 1 1.163 R11C24D.F0 to R11C23B.C1 cpu0/regs/SU_216_i1_mux
|
FCITOFCO_D --- 0.162 R10C25C.FCI to R10C25C.FCO cpu0/SLICE_190
|
C1TOFCO_DE --- 0.889 R11C23B.C1 to R11C23B.FCO cpu0/regs/SLICE_58
|
ROUTE 1 0.000 R10C25C.FCO to R10C25D.FCI cpu0/un1_k_cpu_addr_1_cry_12
|
ROUTE 1 0.000 R11C23B.FCO to R11C23C.FCI cpu0/regs/SU_cry[9]
|
FCITOF1_DE --- 0.643 R10C25D.FCI to R10C25D.F1 cpu0/SLICE_189
|
FCITOFCO_D --- 0.162 R11C23C.FCI to R11C23C.FCO cpu0/regs/SLICE_57
|
ROUTE 1 1.385 R10C25D.F1 to R12C28A.D0 cpu0/un1_k_cpu_addr_1_cry_13_0_S1
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
CTOF_DEL --- 0.495 R12C28A.D0 to R12C28A.F0 cpu0/SLICE_1246
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
ROUTE 1 0.744 R12C28A.F0 to R12C27A.C0 cpu0/alu/un1_k_cpu_addr_1_m[14]
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
CTOF_DEL --- 0.495 R12C27A.C0 to R12C27A.F0 cpu0/SLICE_203
|
FCITOF0_DE --- 0.585 R11C24A.FCI to R11C24A.F0 cpu0/regs/SLICE_55
|
ROUTE 1 0.000 R12C27A.F0 to R12C27A.DI0 cpu0/k_cpu_addr_28[14] (to cpu_clkgen)
|
ROUTE 1 0.000 R11C24A.F0 to R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
|
--------
|
--------
|
23.719 (34.8% logic, 65.2% route), 19 logic levels.
|
24.425 (36.0% logic, 64.0% route), 19 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_1133:
|
Source Clock Path clk40_i to SLICE_260:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R14C26D.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/SLICE_203:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R12C27A.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 1.149ns
|
Passed: The following path meets requirements by 0.413ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/alu/rb_in[1] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SS[15] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SU[13] (to cpu_clkgen +)
|
|
|
Delay: 23.685ns (43.0% logic, 57.0% route), 19 logic levels.
|
Delay: 24.421ns (35.7% logic, 64.3% route), 17 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
23.685ns physical path delay cpu0/SLICE_229 to cpu0/regs/SLICE_73 meets
|
24.421ns physical path delay SLICE_260 to cpu0/regs/SLICE_56 meets
|
25.000ns delay constraint less
|
25.000ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 1.149ns
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.413ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_229 to cpu0/regs/SLICE_73:
|
Data path SLICE_260 to cpu0/regs/SLICE_56:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R12C13B.CLK to R12C13B.Q1 cpu0/SLICE_229 (from cpu_clkgen)
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
ROUTE 26 1.735 R12C13B.Q1 to R10C14B.A0 cpu0/alu/rb_in[1]
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
C0TOFCO_DE --- 1.023 R10C14B.A0 to R10C14B.FCO cpu0/alu/alu16/a16/SLICE_98
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
ROUTE 1 0.000 R10C14B.FCO to R10C14C.FCI cpu0/alu/alu16/a16/un8_q_out_cry_2
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
FCITOF1_DE --- 0.643 R10C14C.FCI to R10C14C.F1 cpu0/alu/alu16/a16/SLICE_97
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
ROUTE 1 1.385 R10C14C.F1 to R11C17C.D0 cpu0/alu/alu16/a16/un8_q_out[4]
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
CTOF_DEL --- 0.495 R11C17C.D0 to R11C17C.F0 cpu0/alu/SLICE_1151
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
ROUTE 1 1.675 R11C17C.F0 to R11C21C.C1 cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO_0_0
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
C1TOFCO_DE --- 0.889 R11C21C.C1 to R11C21C.FCO cpu0/alu/alu16/a16/SLICE_115
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
ROUTE 1 0.000 R11C21C.FCO to R11C21D.FCI cpu0/alu/alu16/a16/q_out_2_cry_4
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
FCITOF0_DE --- 0.585 R11C21D.FCI to R11C21D.F0 cpu0/alu/alu16/a16/SLICE_114
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
ROUTE 1 1.705 R11C21D.F0 to R7C15D.C0 cpu0/alu/alu16/a16/N_2261
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
CTOF_DEL --- 0.495 R7C15D.C0 to R7C15D.F0 cpu0/alu/alu16/SLICE_1209
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
ROUTE 1 0.958 R7C15D.F0 to R9C15A.D1 cpu0/alu/alu16/arith_q[5]
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
CTOOFX_DEL --- 0.721 R9C15A.D1 to R9C15A.OFX0 cpu0/alu/alu16/q_out[5]/SLICE_537
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
ROUTE 2 1.285 R9C15A.OFX0 to R9C22B.C1 cpu0/alu/q16_out[5]
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
CTOOFX_DEL --- 0.721 R9C22B.C1 to R9C22B.OFX0 cpu0/alu/alu16/datamux_o_dest[5]/SLICE_540
|
FCITOF1_DE --- 0.643 R19C19B.FCI to R19C19B.F1 cpu0/regs/ea/SLICE_40
|
ROUTE 2 1.392 R9C22B.OFX0 to R11C20D.D0 cpu0/datamux_o_dest[5]
|
ROUTE 4 2.307 R19C19B.F1 to R16C30C.C1 cpu0/regs_o_eamem_addr[10]
|
CTOF_DEL --- 0.495 R11C20D.D0 to R11C20D.F0 cpu0/regs/SLICE_890
|
CTOF_DEL --- 0.495 R16C30C.C1 to R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
|
ROUTE 9 0.798 R11C20D.F0 to R9C20D.C0 cpu0/regs/left_1[5]
|
ROUTE 1 1.023 R16C30C.F1 to R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
|
CTOF_DEL --- 0.495 R9C20D.C0 to R9C20D.F0 cpu0/regs/SLICE_1124
|
CTOF_DEL --- 0.495 R14C30D.B0 to R14C30D.F0 cpu0/alu/alu16/SLICE_1054
|
ROUTE 1 0.626 R9C20D.F0 to R9C20B.D1 cpu0/regs/N_248
|
ROUTE 2 1.640 R14C30D.F0 to R12C24A.A0 cpu0/datamux_o_dest[10]
|
CTOF_DEL --- 0.495 R9C20B.D1 to R9C20B.F1 cpu0/regs/SLICE_908
|
CTOF_DEL --- 0.495 R12C24A.A0 to R12C24A.F0 cpu0/regs/SLICE_362
|
ROUTE 1 0.436 R9C20B.F1 to R9C20B.C0 cpu0/regs/SS_16[5]
|
ROUTE 6 0.780 R12C24A.F0 to R11C24B.C0 cpu0/regs/left_1[10]
|
CTOF_DEL --- 0.495 R9C20B.C0 to R9C20B.F0 cpu0/regs/SLICE_908
|
CTOF_DEL --- 0.495 R11C24B.C0 to R11C24B.F0 cpu0/regs/SLICE_1191
|
ROUTE 1 1.506 R9C20B.F0 to R11C18D.C1 cpu0/regs/SS_226_i1_mux
|
ROUTE 1 0.958 R11C24B.F0 to R10C23D.D1 cpu0/regs/N_289
|
C1TOFCO_DE --- 0.889 R11C18D.C1 to R11C18D.FCO cpu0/regs/SLICE_78
|
CTOF_DEL --- 0.495 R10C23D.D1 to R10C23D.F1 cpu0/regs/SLICE_949
|
ROUTE 1 0.000 R11C18D.FCO to R11C19A.FCI cpu0/regs/SS_cry[5]
|
ROUTE 1 0.436 R10C23D.F1 to R10C23D.C0 cpu0/regs/SU_16[10]
|
FCITOFCO_D --- 0.162 R11C19A.FCI to R11C19A.FCO cpu0/regs/SLICE_77
|
CTOF_DEL --- 0.495 R10C23D.C0 to R10C23D.F0 cpu0/regs/SLICE_949
|
ROUTE 1 0.000 R11C19A.FCO to R11C19B.FCI cpu0/regs/SS_cry[7]
|
ROUTE 1 1.506 R10C23D.F0 to R11C23C.C0 cpu0/regs/SU_217_i1_mux
|
FCITOFCO_D --- 0.162 R11C19B.FCI to R11C19B.FCO cpu0/regs/SLICE_76
|
C0TOFCO_DE --- 1.023 R11C23C.C0 to R11C23C.FCO cpu0/regs/SLICE_57
|
ROUTE 1 0.000 R11C19B.FCO to R11C19C.FCI cpu0/regs/SS_cry[9]
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
FCITOFCO_D --- 0.162 R11C19C.FCI to R11C19C.FCO cpu0/regs/SLICE_75
|
FCITOF1_DE --- 0.643 R11C23D.FCI to R11C23D.F1 cpu0/regs/SLICE_56
|
ROUTE 1 0.000 R11C19C.FCO to R11C19D.FCI cpu0/regs/SS_cry[11]
|
ROUTE 1 0.000 R11C23D.F1 to R11C23D.DI1 cpu0/regs/SU_s[13] (to cpu_clkgen)
|
FCITOFCO_D --- 0.162 R11C19D.FCI to R11C19D.FCO cpu0/regs/SLICE_74
|
|
ROUTE 1 0.000 R11C19D.FCO to R11C20A.FCI cpu0/regs/SS_cry[13]
|
|
FCITOF1_DE --- 0.643 R11C20A.FCI to R11C20A.F1 cpu0/regs/SLICE_73
|
|
ROUTE 1 0.000 R11C20A.F1 to R11C20A.DI1 cpu0/regs/SS_s[15] (to cpu_clkgen)
|
|
--------
|
--------
|
23.685 (43.0% logic, 57.0% route), 19 logic levels.
|
24.421 (35.7% logic, 64.3% route), 17 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_229:
|
Source Clock Path clk40_i to SLICE_260:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R12C13B.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_73:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_56:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 2.399 27.PADDI to R11C20A.CLK cpu_clkgen
|
ROUTE 367 2.399 27.PADDI to R11C23D.CLK cpu_clkgen
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Report: 41.761MHz is the maximum frequency for this preference.
|
Report: 40.406MHz is the maximum frequency for this preference.
|
|
|
Report Summary
|
Report Summary
|
--------------
|
--------------
|
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
Preference | Constraint| Actual|Levels
|
Preference | Constraint| Actual|Levels
|
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
| | |
|
| | |
|
FREQUENCY NET "cpu_clkgen" 40.000000 | | |
|
FREQUENCY NET "cpu_clkgen" 40.000000 | | |
|
MHz ; | 40.000 MHz| 41.761 MHz| 19
|
MHz ; | 40.000 MHz| 40.406 MHz| 18
|
| | |
|
| | |
|
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
|
|
|
|
All preferences were met.
|
All preferences were met.
|
| Line 843... |
Line 841... |
Clock Domains Analysis
|
Clock Domains Analysis
|
------------------------
|
------------------------
|
|
|
Found 1 clocks:
|
Found 1 clocks:
|
|
|
Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 290
|
Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 367
|
Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
|
|
|
|
Timing summary (Setup):
|
Timing summary (Setup):
|
---------------
|
---------------
|
|
|
Timing errors: 0 Score: 0
|
Timing errors: 0 Score: 0
|
Cumulative negative slack: 0
|
Cumulative negative slack: 0
|
|
|
Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
|
Constraints cover 1107881 paths, 1 nets, and 9532 connections (99.1% coverage)
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
|
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
|
Mon Jan 6 06:55:04 2014
|
Thu Feb 6 15:36:12 2014
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
| Line 886... |
Line 884... |
Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
4096 items scored, 0 timing errors detected.
|
4096 items scored, 0 timing errors detected.
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
|
|
Passed: The following path meets requirements by 0.180ns
|
Passed: The following path meets requirements by 0.217ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_cpu_addr[5] (from cpu_clkgen +)
|
Source: FF Q textctrl/chars_data[6] (from cpu_clkgen +)
|
Destination: DP8KC Port textctrl/chars/textmem4k_0_3_0(ASIC) (to cpu_clkgen +)
|
Destination: DP8KC Port textctrl/font/fontrom_0_0_3(ASIC) (to cpu_clkgen +)
|
|
|
Delay: 0.304ns (43.1% logic, 56.9% route), 1 logic levels.
|
Delay: 0.322ns (40.7% logic, 59.3% route), 1 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
0.304ns physical path delay cpu0/SLICE_198 to textctrl/chars/textmem4k_0_3_0 meets
|
0.322ns physical path delay SLICE_454 to textctrl/font/fontrom_0_0_3 meets
|
0.071ns ADDR_HLD and
|
0.052ns ADDR_HLD and
|
0.000ns delay constraint less
|
0.000ns delay constraint less
|
-0.053ns skew requirement (totaling 0.124ns) by 0.180ns
|
-0.053ns skew requirement (totaling 0.105ns) by 0.217ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_198 to textctrl/chars/textmem4k_0_3_0:
|
Data path SLICE_454 to textctrl/font/fontrom_0_0_3:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R12C28D.CLK to R12C28D.Q1 cpu0/SLICE_198 (from cpu_clkgen)
|
REG_DEL --- 0.131 R14C17C.CLK to R14C17C.Q0 SLICE_454 (from cpu_clkgen)
|
ROUTE 8 0.173 R12C28D.Q1 to *R_R13C27.ADB6 addr_o_c[5] (to cpu_clkgen)
|
ROUTE 4 0.191 R14C17C.Q0 to *_R13C16.ADA11 textctrl/chars_data[6] (to cpu_clkgen)
|
--------
|
--------
|
0.304 (43.1% logic, 56.9% route), 1 logic levels.
|
0.322 (40.7% logic, 59.3% route), 1 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_198:
|
Source Clock Path clk40_i to SLICE_454:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.846 27.PADDI to R12C28D.CLK cpu_clkgen
|
ROUTE 367 0.846 27.PADDI to R14C17C.CLK cpu_clkgen
|
--------
|
--------
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_3_0:
|
Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.899 27.PADDI to *R_R13C27.CLKB cpu_clkgen
|
ROUTE 367 0.899 27.PADDI to *R_R13C16.CLKA cpu_clkgen
|
--------
|
--------
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.261ns
|
Passed: The following path meets requirements by 0.234ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_cpu_addr[11] (from cpu_clkgen +)
|
Source: FF Q textctrl/chars_data[7] (from cpu_clkgen +)
|
Destination: DP8KC Port textctrl/chars/textmem4k_0_2_1(ASIC) (to cpu_clkgen +)
|
Destination: DP8KC Port textctrl/font/fontrom_0_0_3(ASIC) (to cpu_clkgen +)
|
|
|
Delay: 0.385ns (34.0% logic, 66.0% route), 1 logic levels.
|
Delay: 0.339ns (38.6% logic, 61.4% route), 1 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
0.385ns physical path delay cpu0/SLICE_201 to textctrl/chars/textmem4k_0_2_1 meets
|
0.339ns physical path delay SLICE_454 to textctrl/font/fontrom_0_0_3 meets
|
0.071ns ADDR_HLD and
|
0.052ns ADDR_HLD and
|
0.000ns delay constraint less
|
0.000ns delay constraint less
|
-0.053ns skew requirement (totaling 0.124ns) by 0.261ns
|
-0.053ns skew requirement (totaling 0.105ns) by 0.234ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_201 to textctrl/chars/textmem4k_0_2_1:
|
Data path SLICE_454 to textctrl/font/fontrom_0_0_3:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R11C26A.CLK to R11C26A.Q1 cpu0/SLICE_201 (from cpu_clkgen)
|
REG_DEL --- 0.131 R14C17C.CLK to R14C17C.Q1 SLICE_454 (from cpu_clkgen)
|
ROUTE 6 0.254 R11C26A.Q1 to *_R13C24.ADB12 addr_o_c[11] (to cpu_clkgen)
|
ROUTE 4 0.208 R14C17C.Q1 to *_R13C16.ADA12 textctrl/chars_data[7] (to cpu_clkgen)
|
--------
|
--------
|
0.385 (34.0% logic, 66.0% route), 1 logic levels.
|
0.339 (38.6% logic, 61.4% route), 1 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_201:
|
Source Clock Path clk40_i to SLICE_454:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.846 27.PADDI to R11C26A.CLK cpu_clkgen
|
ROUTE 367 0.846 27.PADDI to R14C17C.CLK cpu_clkgen
|
--------
|
--------
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
|
Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.899 27.PADDI to *R_R13C24.CLKB cpu_clkgen
|
ROUTE 367 0.899 27.PADDI to *R_R13C16.CLKA cpu_clkgen
|
--------
|
--------
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.297ns
|
Passed: The following path meets requirements by 0.344ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_cpu_addr[6] (from cpu_clkgen +)
|
Source: FF Q reset_cnt[0] (from cpu_clkgen +)
|
Destination: DP8KC Port textctrl/chars/textmem4k_0_2_1(ASIC) (to cpu_clkgen +)
|
Destination: FF Data in reset_cnt[0] (to cpu_clkgen +)
|
|
|
Delay: 0.421ns (31.1% logic, 68.9% route), 1 logic levels.
|
Delay: 0.288ns (45.5% logic, 54.5% route), 1 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
0.421ns physical path delay cpu0/SLICE_199 to textctrl/chars/textmem4k_0_2_1 meets
|
0.288ns physical path delay SLICE_444 to SLICE_444 meets
|
0.071ns ADDR_HLD and
|
-0.056ns LSR_HLD and
|
0.000ns delay constraint less
|
0.000ns delay constraint less
|
-0.053ns skew requirement (totaling 0.124ns) by 0.297ns
|
0.000ns skew requirement (totaling -0.056ns) by 0.344ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_199 to textctrl/chars/textmem4k_0_2_1:
|
Data path SLICE_444 to SLICE_444:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R11C25D.CLK to R11C25D.Q0 cpu0/SLICE_199 (from cpu_clkgen)
|
REG_DEL --- 0.131 R19C8D.CLK to R19C8D.Q0 SLICE_444 (from cpu_clkgen)
|
ROUTE 8 0.290 R11C25D.Q0 to *R_R13C24.ADB7 addr_o_c[6] (to cpu_clkgen)
|
ROUTE 5 0.157 R19C8D.Q0 to R19C8D.LSR reset_cnt[0] (to cpu_clkgen)
|
--------
|
--------
|
0.421 (31.1% logic, 68.9% route), 1 logic levels.
|
0.288 (45.5% logic, 54.5% route), 1 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_199:
|
Source Clock Path clk40_i to SLICE_444:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.846 27.PADDI to R11C25D.CLK cpu_clkgen
|
ROUTE 367 0.846 27.PADDI to R19C8D.CLK cpu_clkgen
|
--------
|
--------
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
|
Destination Clock Path clk40_i to SLICE_444:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.899 27.PADDI to *R_R13C24.CLKB cpu_clkgen
|
ROUTE 367 0.846 27.PADDI to R19C8D.CLK cpu_clkgen
|
--------
|
--------
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.301ns
|
Passed: The following path meets requirements by 0.370ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/alu/alu16/mulu/pipe0[0] (from cpu_clkgen +)
|
Source: FF Q textctrl/blink_cnt[0] (from cpu_clkgen +)
|
Destination: FF Data in cpu0/alu/alu16/mulu/pipe1[0] (to cpu_clkgen +)
|
Destination: FF Data in textctrl/blink_cnt[0] (to cpu_clkgen +)
|
|
|
Delay: 0.282ns (46.5% logic, 53.5% route), 1 logic levels.
|
Delay: 0.357ns (64.4% logic, 35.6% route), 2 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
0.282ns physical path delay cpu0/alu/alu16/mulu/SLICE_210 to cpu0/alu/alu16/mulu/SLICE_133 meets
|
0.357ns physical path delay textctrl/SLICE_29 to textctrl/SLICE_29 meets
|
-0.019ns M_HLD and
|
-0.013ns DIN_HLD and
|
0.000ns delay constraint less
|
0.000ns delay constraint less
|
0.000ns skew requirement (totaling -0.019ns) by 0.301ns
|
0.000ns skew requirement (totaling -0.013ns) by 0.370ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/alu/alu16/mulu/SLICE_210 to cpu0/alu/alu16/mulu/SLICE_133:
|
Data path textctrl/SLICE_29 to textctrl/SLICE_29:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R8C12C.CLK to R8C12C.Q0 cpu0/alu/alu16/mulu/SLICE_210 (from cpu_clkgen)
|
REG_DEL --- 0.131 R25C10A.CLK to R25C10A.Q1 textctrl/SLICE_29 (from cpu_clkgen)
|
ROUTE 2 0.151 R8C12C.Q0 to R8C12A.M1 cpu0/alu/alu16/mulu/pipe0[0] (to cpu_clkgen)
|
ROUTE 1 0.127 R25C10A.Q1 to R25C10A.A1 textctrl/blink_cnt[0]
|
|
CTOF_DEL --- 0.099 R25C10A.A1 to R25C10A.F1 textctrl/SLICE_29
|
|
ROUTE 1 0.000 R25C10A.F1 to R25C10A.DI1 textctrl/blink_cnt_s[0] (to cpu_clkgen)
|
--------
|
--------
|
0.282 (46.5% logic, 53.5% route), 1 logic levels.
|
0.357 (64.4% logic, 35.6% route), 2 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/alu/alu16/mulu/SLICE_210:
|
Source Clock Path clk40_i to textctrl/SLICE_29:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.846 27.PADDI to R8C12C.CLK cpu_clkgen
|
ROUTE 367 0.828 27.PADDI to R25C10A.CLK cpu_clkgen
|
--------
|
--------
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/alu/alu16/mulu/SLICE_133:
|
Destination Clock Path clk40_i to textctrl/SLICE_29:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.846 27.PADDI to R8C12A.CLK cpu_clkgen
|
ROUTE 367 0.828 27.PADDI to R25C10A.CLK cpu_clkgen
|
--------
|
--------
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.364ns
|
Passed: The following path meets requirements by 0.370ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_cpu_addr[10] (from cpu_clkgen +)
|
Source: FF Q textctrl/blink_cnt[4] (from cpu_clkgen +)
|
Destination: DP8KC Port textctrl/chars/textmem4k_0_3_0(ASIC) (to cpu_clkgen +)
|
Destination: FF Data in textctrl/blink_cnt[4] (to cpu_clkgen +)
|
|
|
Delay: 0.488ns (26.8% logic, 73.2% route), 1 logic levels.
|
Delay: 0.357ns (64.4% logic, 35.6% route), 2 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
0.488ns physical path delay cpu0/SLICE_201 to textctrl/chars/textmem4k_0_3_0 meets
|
0.357ns physical path delay textctrl/SLICE_27 to textctrl/SLICE_27 meets
|
0.071ns ADDR_HLD and
|
-0.013ns DIN_HLD and
|
0.000ns delay constraint less
|
0.000ns delay constraint less
|
-0.053ns skew requirement (totaling 0.124ns) by 0.364ns
|
0.000ns skew requirement (totaling -0.013ns) by 0.370ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_201 to textctrl/chars/textmem4k_0_3_0:
|
Data path textctrl/SLICE_27 to textctrl/SLICE_27:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R11C26A.CLK to R11C26A.Q0 cpu0/SLICE_201 (from cpu_clkgen)
|
REG_DEL --- 0.131 R25C10C.CLK to R25C10C.Q1 textctrl/SLICE_27 (from cpu_clkgen)
|
ROUTE 8 0.357 R11C26A.Q0 to *_R13C27.ADB11 addr_o_c[10] (to cpu_clkgen)
|
ROUTE 1 0.127 R25C10C.Q1 to R25C10C.A1 textctrl/blink_cnt[4]
|
|
CTOF_DEL --- 0.099 R25C10C.A1 to R25C10C.F1 textctrl/SLICE_27
|
|
ROUTE 1 0.000 R25C10C.F1 to R25C10C.DI1 textctrl/blink_cnt_s[4] (to cpu_clkgen)
|
--------
|
--------
|
0.488 (26.8% logic, 73.2% route), 1 logic levels.
|
0.357 (64.4% logic, 35.6% route), 2 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_201:
|
Source Clock Path clk40_i to textctrl/SLICE_27:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.846 27.PADDI to R11C26A.CLK cpu_clkgen
|
ROUTE 367 0.828 27.PADDI to R25C10C.CLK cpu_clkgen
|
--------
|
--------
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_3_0:
|
Destination Clock Path clk40_i to textctrl/SLICE_27:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.899 27.PADDI to *R_R13C27.CLKB cpu_clkgen
|
ROUTE 367 0.828 27.PADDI to R25C10C.CLK cpu_clkgen
|
--------
|
--------
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.370ns
|
Passed: The following path meets requirements by 0.370ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q textctrl/blink_cnt[0] (from cpu_clkgen +)
|
Source: FF Q textctrl/blink_cnt[3] (from cpu_clkgen +)
|
Destination: FF Data in textctrl/blink_cnt[0] (to cpu_clkgen +)
|
Destination: FF Data in textctrl/blink_cnt[3] (to cpu_clkgen +)
|
|
|
Delay: 0.357ns (64.4% logic, 35.6% route), 2 logic levels.
|
Delay: 0.357ns (64.4% logic, 35.6% route), 2 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
0.357ns physical path delay textctrl/SLICE_29 to textctrl/SLICE_29 meets
|
0.357ns physical path delay textctrl/SLICE_27 to textctrl/SLICE_27 meets
|
-0.013ns DIN_HLD and
|
-0.013ns DIN_HLD and
|
0.000ns delay constraint less
|
0.000ns delay constraint less
|
0.000ns skew requirement (totaling -0.013ns) by 0.370ns
|
0.000ns skew requirement (totaling -0.013ns) by 0.370ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path textctrl/SLICE_29 to textctrl/SLICE_29:
|
Data path textctrl/SLICE_27 to textctrl/SLICE_27:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R23C32A.CLK to R23C32A.Q1 textctrl/SLICE_29 (from cpu_clkgen)
|
REG_DEL --- 0.131 R25C10C.CLK to R25C10C.Q0 textctrl/SLICE_27 (from cpu_clkgen)
|
ROUTE 1 0.127 R23C32A.Q1 to R23C32A.A1 textctrl/blink_cnt[0]
|
ROUTE 1 0.127 R25C10C.Q0 to R25C10C.A0 textctrl/blink_cnt[3]
|
CTOF_DEL --- 0.099 R23C32A.A1 to R23C32A.F1 textctrl/SLICE_29
|
CTOF_DEL --- 0.099 R25C10C.A0 to R25C10C.F0 textctrl/SLICE_27
|
ROUTE 1 0.000 R23C32A.F1 to R23C32A.DI1 textctrl/blink_cnt_s[0] (to cpu_clkgen)
|
ROUTE 1 0.000 R25C10C.F0 to R25C10C.DI0 textctrl/blink_cnt_s[3] (to cpu_clkgen)
|
--------
|
--------
|
0.357 (64.4% logic, 35.6% route), 2 logic levels.
|
0.357 (64.4% logic, 35.6% route), 2 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to textctrl/SLICE_29:
|
Source Clock Path clk40_i to textctrl/SLICE_27:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.828 27.PADDI to R23C32A.CLK cpu_clkgen
|
ROUTE 367 0.828 27.PADDI to R25C10C.CLK cpu_clkgen
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/SLICE_29:
|
Destination Clock Path clk40_i to textctrl/SLICE_27:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.828 27.PADDI to R23C32A.CLK cpu_clkgen
|
ROUTE 367 0.828 27.PADDI to R25C10C.CLK cpu_clkgen
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.370ns
|
Passed: The following path meets requirements by 0.370ns
|
| Line 1167... |
Line 1169... |
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path textctrl/SLICE_28 to textctrl/SLICE_28:
|
Data path textctrl/SLICE_28 to textctrl/SLICE_28:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R23C32B.CLK to R23C32B.Q0 textctrl/SLICE_28 (from cpu_clkgen)
|
REG_DEL --- 0.131 R25C10B.CLK to R25C10B.Q0 textctrl/SLICE_28 (from cpu_clkgen)
|
ROUTE 1 0.127 R23C32B.Q0 to R23C32B.A0 textctrl/blink_cnt[1]
|
ROUTE 1 0.127 R25C10B.Q0 to R25C10B.A0 textctrl/blink_cnt[1]
|
CTOF_DEL --- 0.099 R23C32B.A0 to R23C32B.F0 textctrl/SLICE_28
|
CTOF_DEL --- 0.099 R25C10B.A0 to R25C10B.F0 textctrl/SLICE_28
|
ROUTE 1 0.000 R23C32B.F0 to R23C32B.DI0 textctrl/blink_cnt_s[1] (to cpu_clkgen)
|
ROUTE 1 0.000 R25C10B.F0 to R25C10B.DI0 textctrl/blink_cnt_s[1] (to cpu_clkgen)
|
--------
|
--------
|
0.357 (64.4% logic, 35.6% route), 2 logic levels.
|
0.357 (64.4% logic, 35.6% route), 2 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to textctrl/SLICE_28:
|
Source Clock Path clk40_i to textctrl/SLICE_28:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.828 27.PADDI to R23C32B.CLK cpu_clkgen
|
ROUTE 367 0.828 27.PADDI to R25C10B.CLK cpu_clkgen
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/SLICE_28:
|
Destination Clock Path clk40_i to textctrl/SLICE_28:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.828 27.PADDI to R23C32B.CLK cpu_clkgen
|
ROUTE 367 0.828 27.PADDI to R25C10B.CLK cpu_clkgen
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.370ns
|
Passed: The following path meets requirements by 0.370ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q textctrl/blink_cnt[3] (from cpu_clkgen +)
|
Source: FF Q textctrl/blink_cnt[2] (from cpu_clkgen +)
|
Destination: FF Data in textctrl/blink_cnt[3] (to cpu_clkgen +)
|
Destination: FF Data in textctrl/blink_cnt[2] (to cpu_clkgen +)
|
|
|
Delay: 0.357ns (64.4% logic, 35.6% route), 2 logic levels.
|
Delay: 0.357ns (64.4% logic, 35.6% route), 2 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
0.357ns physical path delay textctrl/SLICE_27 to textctrl/SLICE_27 meets
|
0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
|
-0.013ns DIN_HLD and
|
-0.013ns DIN_HLD and
|
0.000ns delay constraint less
|
0.000ns delay constraint less
|
0.000ns skew requirement (totaling -0.013ns) by 0.370ns
|
0.000ns skew requirement (totaling -0.013ns) by 0.370ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path textctrl/SLICE_27 to textctrl/SLICE_27:
|
Data path textctrl/SLICE_28 to textctrl/SLICE_28:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R23C32C.CLK to R23C32C.Q0 textctrl/SLICE_27 (from cpu_clkgen)
|
REG_DEL --- 0.131 R25C10B.CLK to R25C10B.Q1 textctrl/SLICE_28 (from cpu_clkgen)
|
ROUTE 1 0.127 R23C32C.Q0 to R23C32C.A0 textctrl/blink_cnt[3]
|
ROUTE 1 0.127 R25C10B.Q1 to R25C10B.A1 textctrl/blink_cnt[2]
|
CTOF_DEL --- 0.099 R23C32C.A0 to R23C32C.F0 textctrl/SLICE_27
|
CTOF_DEL --- 0.099 R25C10B.A1 to R25C10B.F1 textctrl/SLICE_28
|
ROUTE 1 0.000 R23C32C.F0 to R23C32C.DI0 textctrl/blink_cnt_s[3] (to cpu_clkgen)
|
ROUTE 1 0.000 R25C10B.F1 to R25C10B.DI1 textctrl/blink_cnt_s[2] (to cpu_clkgen)
|
--------
|
--------
|
0.357 (64.4% logic, 35.6% route), 2 logic levels.
|
0.357 (64.4% logic, 35.6% route), 2 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to textctrl/SLICE_27:
|
Source Clock Path clk40_i to textctrl/SLICE_28:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.828 27.PADDI to R23C32C.CLK cpu_clkgen
|
ROUTE 367 0.828 27.PADDI to R25C10B.CLK cpu_clkgen
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/SLICE_27:
|
Destination Clock Path clk40_i to textctrl/SLICE_28:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.828 27.PADDI to R23C32C.CLK cpu_clkgen
|
ROUTE 367 0.828 27.PADDI to R25C10B.CLK cpu_clkgen
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.370ns
|
Passed: The following path meets requirements by 0.371ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q textctrl/blink_cnt[2] (from cpu_clkgen +)
|
Source: FF Q textctrl/chars_data[3] (from cpu_clkgen +)
|
Destination: FF Data in textctrl/blink_cnt[2] (to cpu_clkgen +)
|
Destination: DP8KC Port textctrl/font/fontrom_0_3_0(ASIC) (to cpu_clkgen +)
|
|
|
Delay: 0.357ns (64.4% logic, 35.6% route), 2 logic levels.
|
Delay: 0.476ns (27.5% logic, 72.5% route), 1 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
|
0.476ns physical path delay textctrl/SLICE_1231 to textctrl/font/fontrom_0_3_0 meets
|
-0.013ns DIN_HLD and
|
0.052ns ADDR_HLD and
|
0.000ns delay constraint less
|
0.000ns delay constraint less
|
0.000ns skew requirement (totaling -0.013ns) by 0.370ns
|
-0.053ns skew requirement (totaling 0.105ns) by 0.371ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path textctrl/SLICE_28 to textctrl/SLICE_28:
|
Data path textctrl/SLICE_1231 to textctrl/font/fontrom_0_3_0:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R23C32B.CLK to R23C32B.Q1 textctrl/SLICE_28 (from cpu_clkgen)
|
REG_DEL --- 0.131 R19C14D.CLK to R19C14D.Q1 textctrl/SLICE_1231 (from cpu_clkgen)
|
ROUTE 1 0.127 R23C32B.Q1 to R23C32B.A1 textctrl/blink_cnt[2]
|
ROUTE 4 0.345 R19C14D.Q1 to *R_R20C16.ADA8 textctrl/chars_data[3] (to cpu_clkgen)
|
CTOF_DEL --- 0.099 R23C32B.A1 to R23C32B.F1 textctrl/SLICE_28
|
|
ROUTE 1 0.000 R23C32B.F1 to R23C32B.DI1 textctrl/blink_cnt_s[2] (to cpu_clkgen)
|
|
--------
|
--------
|
0.357 (64.4% logic, 35.6% route), 2 logic levels.
|
0.476 (27.5% logic, 72.5% route), 1 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to textctrl/SLICE_28:
|
Source Clock Path clk40_i to textctrl/SLICE_1231:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.828 27.PADDI to R23C32B.CLK cpu_clkgen
|
ROUTE 367 0.846 27.PADDI to R19C14D.CLK cpu_clkgen
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/SLICE_28:
|
Destination Clock Path clk40_i to textctrl/font/fontrom_0_3_0:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.828 27.PADDI to R23C32B.CLK cpu_clkgen
|
ROUTE 367 0.899 27.PADDI to *R_R20C16.CLKA cpu_clkgen
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.370ns
|
Passed: The following path meets requirements by 0.372ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_cpu_addr[3] (from cpu_clkgen +)
|
Source: FF Q textctrl/x_cnt[3] (from cpu_clkgen +)
|
Destination: DP8KC Port textctrl/chars/textmem4k_0_2_1(ASIC) (to cpu_clkgen +)
|
Destination: FF Data in textctrl/x_cnt[3] (to cpu_clkgen +)
|
|
|
Delay: 0.494ns (26.5% logic, 73.5% route), 1 logic levels.
|
Delay: 0.359ns (64.1% logic, 35.9% route), 2 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
0.494ns physical path delay cpu0/SLICE_197 to textctrl/chars/textmem4k_0_2_1 meets
|
0.359ns physical path delay textctrl/SLICE_13 to textctrl/SLICE_13 meets
|
0.071ns ADDR_HLD and
|
-0.013ns DIN_HLD and
|
0.000ns delay constraint less
|
0.000ns delay constraint less
|
-0.053ns skew requirement (totaling 0.124ns) by 0.370ns
|
0.000ns skew requirement (totaling -0.013ns) by 0.372ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/SLICE_197 to textctrl/chars/textmem4k_0_2_1:
|
Data path textctrl/SLICE_13 to textctrl/SLICE_13:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R12C25A.CLK to R12C25A.Q1 cpu0/SLICE_197 (from cpu_clkgen)
|
REG_DEL --- 0.131 R22C10C.CLK to R22C10C.Q0 textctrl/SLICE_13 (from cpu_clkgen)
|
ROUTE 8 0.363 R12C25A.Q1 to *R_R13C24.ADB4 addr_o_c[3] (to cpu_clkgen)
|
ROUTE 3 0.129 R22C10C.Q0 to R22C10C.A0 textctrl/x_cnt[3]
|
|
CTOF_DEL --- 0.099 R22C10C.A0 to R22C10C.F0 textctrl/SLICE_13
|
|
ROUTE 1 0.000 R22C10C.F0 to R22C10C.DI0 textctrl/x_cnt_s[3] (to cpu_clkgen)
|
--------
|
--------
|
0.494 (26.5% logic, 73.5% route), 1 logic levels.
|
0.359 (64.1% logic, 35.9% route), 2 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/SLICE_197:
|
Source Clock Path clk40_i to textctrl/SLICE_13:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.846 27.PADDI to R12C25A.CLK cpu_clkgen
|
ROUTE 367 0.828 27.PADDI to R22C10C.CLK cpu_clkgen
|
--------
|
--------
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
|
Destination Clock Path clk40_i to textctrl/SLICE_13:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 290 0.899 27.PADDI to *R_R13C24.CLKB cpu_clkgen
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ROUTE 367 0.828 27.PADDI to R22C10C.CLK cpu_clkgen
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--------
|
--------
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
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0.828 (0.0% logic, 100.0% route), 0 logic levels.
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|
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Report Summary
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Report Summary
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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Preference(MIN Delays) | Constraint| Actual|Levels
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Preference(MIN Delays) | Constraint| Actual|Levels
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| Line 1343... |
Line 1345... |
Clock Domains Analysis
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Clock Domains Analysis
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------------------------
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------------------------
|
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Found 1 clocks:
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Found 1 clocks:
|
|
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Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 290
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Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 367
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Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
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|
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Timing summary (Hold):
|
Timing summary (Hold):
|
---------------
|
---------------
|
|
|
Timing errors: 0 Score: 0
|
Timing errors: 0 Score: 0
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Cumulative negative slack: 0
|
Cumulative negative slack: 0
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|
|
Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
|
Constraints cover 1107881 paths, 1 nets, and 9532 connections (99.1% coverage)
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|
|
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Timing summary (Setup and Hold):
|
Timing summary (Setup and Hold):
|
---------------
|
---------------
|
