| Line 6... |
Line 6... |
-->
|
-->
|
</STYLE>
|
</STYLE>
|
</HEAD>
|
</HEAD>
|
<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
|
<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
|
|
|
Loading design for application trce from file P6809_P6809.ncd.
|
Loading design for application trce from file p6809_p6809.ncd.
|
Design name: CC3_top
|
Design name: CC3_top
|
NCD version: 3.2
|
NCD version: 3.2
|
Vendor: LATTICE
|
Vendor: LATTICE
|
Device: LCMXO2-7000HE
|
Device: LCMXO2-7000HE
|
Package: TQFP144
|
Package: TQFP144
|
Performance: 4
|
Performance: 4
|
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
|
Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.1_x64/ispfpga.
|
Package Status: Final Version 1.36
|
Package Status: Final Version 1.36
|
Performance Hardware Data Status: Final) Version 23.4
|
Performance Hardware Data Status: Final) Version 23.4
|
Setup and Hold Report
|
Setup and Hold Report
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101</big></U></B>
|
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.1.0.96</big></U></B>
|
Thu Feb 6 15:36:11 2014
|
Sun Jul 06 07:47:15 2014
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
|
Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
|
|
|
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
|
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
|
------------------
|
------------------
|
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
|
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr -gui P6809_P6809.ncd P6809_P6809.prf
|
Design file: P6809_P6809.ncd
|
Design file: p6809_p6809.ncd
|
Preference file: P6809_P6809.prf
|
Preference file: p6809_p6809.prf
|
Device,speed: LCMXO2-7000HE,4
|
Device,speed: LCMXO2-7000HE,4
|
Report level: verbose report, limited to 10 items per preference
|
Report level: verbose report, limited to 10 items per preference
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
|
<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
|
|
|
<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (0 errors)</A></LI> 4096 items scored, 0 timing errors detected.
|
<FONT COLOR=red><LI><A href='#par_twr_pref_0_0' Target='right'><FONT COLOR=red>FREQUENCY NET "clk40_i_c" 111.645000 MHz (4096 errors)</FONT></A></LI>
|
Report: 40.406MHz is the maximum frequency for this preference.
|
</FONT> 4096 items scored, 4096 timing errors detected.
|
|
Warning: 29.641MHz is the maximum frequency for this preference.
|
|
|
|
Report Type: based on TRACE automatically generated preferences
|
BLOCK ASYNCPATHS
|
BLOCK ASYNCPATHS
|
BLOCK RESETPATHS
|
BLOCK RESETPATHS
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
================================================================================
|
================================================================================
|
<A name="par_twr_pref_0_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
<A name="par_twr_pref_0_0"></A>Preference: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
|
4096 items scored, 0 timing errors detected.
|
4096 items scored, 4096 timing errors detected.
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
|
|
Passed: The following path meets requirements by 0.251ns
|
Error: The following path exceeds requirements by 24.781ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_opcode[7] (from clk40_i_c +)
|
Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SS[15] (to clk40_i_c +)
|
|
|
Delay: 24.583ns (36.2% logic, 63.8% route), 18 logic levels.
|
Delay: 33.571ns (26.7% logic, 73.3% route), 18 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
24.583ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
33.571ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_64 exceeds
|
25.000ns delay constraint less
|
8.956ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.251ns
|
0.166ns DIN_SET requirement (totaling 8.790ns) by 24.781ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_64:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
REG_DEL --- 0.452 R12C21C.CLK to R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
ROUTE 42 3.151 R12C21C.Q1 to R18C26B.C1 cpu0/k_opcode[7]
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
CTOF_DEL --- 0.495 R18C26B.C1 to R18C26B.F1 cpu0/SLICE_726
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
ROUTE 13 2.235 R18C26B.F1 to R19C25B.A1 cpu0/state133_3
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
CTOF_DEL --- 0.495 R19C25B.A1 to R19C25B.F1 cpu0/dec_regs/SLICE_659
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
ROUTE 1 0.436 R19C25B.F1 to R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
CTOF_DEL --- 0.495 R19C25B.C0 to R19C25B.F0 cpu0/dec_regs/SLICE_659
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
ROUTE 2 1.343 R19C25B.F0 to R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
CTOF_DEL --- 0.495 R18C24D.B1 to R18C24D.F1 cpu0/SLICE_766
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
ROUTE 1 0.623 R18C24D.F1 to R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
CTOF_DEL --- 0.495 R17C24A.D1 to R17C24A.F1 cpu0/dec_regs/SLICE_813
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
ROUTE 6 0.675 R17C24A.F1 to R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
CTOF_DEL --- 0.495 R15C24D.D1 to R15C24D.F1 cpu0/dec_regs/SLICE_806
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
ROUTE 8 0.772 R15C24D.F1 to R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
CTOF_DEL --- 0.495 R15C24A.C1 to R15C24A.F1 cpu0/dec_regs/SLICE_802
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
ROUTE 5 1.441 R15C24A.F1 to R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
|
FCITOF1_DE --- 0.643 R19C19B.FCI to R19C19B.F1 cpu0/regs/ea/SLICE_40
|
MTOOFX_DEL --- 0.376 R17C25D.M0 to R17C25D.OFX0 cpu0/dec_regs/SLICE_264
|
ROUTE 4 2.307 R19C19B.F1 to R16C30C.C1 cpu0/regs_o_eamem_addr[10]
|
ROUTE 5 1.882 R17C25D.OFX0 to R18C22B.A1 cpu0/dec_o_left_path_addr[3]
|
CTOF_DEL --- 0.495 R16C30C.C1 to R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
|
CTOF_DEL --- 0.495 R18C22B.A1 to R18C22B.F1 cpu0/dec_regs/SLICE_846
|
ROUTE 1 1.023 R16C30C.F1 to R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
|
ROUTE 25 3.725 R18C22B.F1 to R9C25A.A0 cpu0/dec_o_alu_size
|
CTOF_DEL --- 0.495 R14C30D.B0 to R14C30D.F0 cpu0/alu/alu16/SLICE_1054
|
CTOF_DEL --- 0.495 R9C25A.A0 to R9C25A.F0 cpu0/SLICE_862
|
ROUTE 2 1.640 R14C30D.F0 to R12C24A.A0 cpu0/datamux_o_dest[10]
|
ROUTE 2 2.557 R9C25A.F0 to R9C20D.B1 cpu0/datamux_o_dest[11]
|
CTOF_DEL --- 0.495 R12C24A.A0 to R12C24A.F0 cpu0/regs/SLICE_362
|
CTOF_DEL --- 0.495 R9C20D.B1 to R9C20D.F1 cpu0/regs/SLICE_945
|
ROUTE 6 0.780 R12C24A.F0 to R11C24B.C0 cpu0/regs/left_1[10]
|
ROUTE 6 2.382 R9C20D.F1 to R10C16B.D0 cpu0/regs/left_1[11]
|
CTOF_DEL --- 0.495 R11C24B.C0 to R11C24B.F0 cpu0/regs/SLICE_1191
|
CTOF_DEL --- 0.495 R10C16B.D0 to R10C16B.F0 cpu0/regs/SLICE_1220
|
ROUTE 1 0.958 R11C24B.F0 to R10C23D.D1 cpu0/regs/N_289
|
ROUTE 1 1.450 R10C16B.F0 to R10C12D.B1 cpu0/regs/N_256
|
CTOF_DEL --- 0.495 R10C23D.D1 to R10C23D.F1 cpu0/regs/SLICE_949
|
CTOF_DEL --- 0.495 R10C12D.B1 to R10C12D.F1 cpu0/regs/SLICE_934
|
ROUTE 1 0.436 R10C23D.F1 to R10C23D.C0 cpu0/regs/SU_16[10]
|
ROUTE 1 0.436 R10C12D.F1 to R10C12D.C0 cpu0/regs/SS_16[11]
|
CTOF_DEL --- 0.495 R10C23D.C0 to R10C23D.F0 cpu0/regs/SLICE_949
|
CTOF_DEL --- 0.495 R10C12D.C0 to R10C12D.F0 cpu0/regs/SLICE_934
|
ROUTE 1 1.506 R10C23D.F0 to R11C23C.C0 cpu0/regs/SU_217_i1_mux
|
ROUTE 1 1.506 R10C12D.F0 to R11C12C.C1 cpu0/regs/SS_226_i1_mux
|
C0TOFCO_DE --- 1.023 R11C23C.C0 to R11C23C.FCO cpu0/regs/SLICE_57
|
C1TOFCO_DE --- 0.889 R11C12C.C1 to R11C12C.FCO cpu0/regs/SLICE_66
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
ROUTE 1 0.000 R11C12C.FCO to R11C12D.FCI cpu0/regs/SS_cry[11]
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
FCITOFCO_D --- 0.162 R11C12D.FCI to R11C12D.FCO cpu0/regs/SLICE_65
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
ROUTE 1 0.000 R11C12D.FCO to R11C13A.FCI cpu0/regs/SS_cry[13]
|
FCITOF1_DE --- 0.643 R11C24A.FCI to R11C24A.F1 cpu0/regs/SLICE_55
|
FCITOF1_DE --- 0.643 R11C13A.FCI to R11C13A.F1 cpu0/regs/SLICE_64
|
ROUTE 1 0.000 R11C24A.F1 to R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
|
ROUTE 1 0.000 R11C13A.F1 to R11C13A.DI1 cpu0/regs/SS_s[15] (to clk40_i_c)
|
--------
|
--------
|
24.583 (36.2% logic, 63.8% route), 18 logic levels.
|
33.571 (26.7% logic, 73.3% route), 18 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to SLICE_260:
|
Source Clock Path clk40_i to cpu0/SLICE_1217:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R12C21C.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R11C13A.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.309ns
|
Error: The following path exceeds requirements by 24.723ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_opcode[7] (from clk40_i_c +)
|
Destination: FF Data in cpu0/regs/SU[14] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SS[14] (to clk40_i_c +)
|
|
|
Delay: 24.525ns (36.0% logic, 64.0% route), 18 logic levels.
|
Delay: 33.513ns (26.6% logic, 73.4% route), 18 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
24.525ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
33.513ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_64 exceeds
|
25.000ns delay constraint less
|
8.956ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.309ns
|
0.166ns DIN_SET requirement (totaling 8.790ns) by 24.723ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_64:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
REG_DEL --- 0.452 R12C21C.CLK to R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
ROUTE 42 3.151 R12C21C.Q1 to R18C26B.C1 cpu0/k_opcode[7]
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
CTOF_DEL --- 0.495 R18C26B.C1 to R18C26B.F1 cpu0/SLICE_726
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
ROUTE 13 2.235 R18C26B.F1 to R19C25B.A1 cpu0/state133_3
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
CTOF_DEL --- 0.495 R19C25B.A1 to R19C25B.F1 cpu0/dec_regs/SLICE_659
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
ROUTE 1 0.436 R19C25B.F1 to R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
CTOF_DEL --- 0.495 R19C25B.C0 to R19C25B.F0 cpu0/dec_regs/SLICE_659
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
ROUTE 2 1.343 R19C25B.F0 to R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
CTOF_DEL --- 0.495 R18C24D.B1 to R18C24D.F1 cpu0/SLICE_766
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
ROUTE 1 0.623 R18C24D.F1 to R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
CTOF_DEL --- 0.495 R17C24A.D1 to R17C24A.F1 cpu0/dec_regs/SLICE_813
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
ROUTE 6 0.675 R17C24A.F1 to R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
CTOF_DEL --- 0.495 R15C24D.D1 to R15C24D.F1 cpu0/dec_regs/SLICE_806
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
ROUTE 8 0.772 R15C24D.F1 to R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
CTOF_DEL --- 0.495 R15C24A.C1 to R15C24A.F1 cpu0/dec_regs/SLICE_802
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
ROUTE 5 1.441 R15C24A.F1 to R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
|
FCITOF1_DE --- 0.643 R19C19B.FCI to R19C19B.F1 cpu0/regs/ea/SLICE_40
|
MTOOFX_DEL --- 0.376 R17C25D.M0 to R17C25D.OFX0 cpu0/dec_regs/SLICE_264
|
ROUTE 4 2.307 R19C19B.F1 to R16C30C.C1 cpu0/regs_o_eamem_addr[10]
|
ROUTE 5 1.882 R17C25D.OFX0 to R18C22B.A1 cpu0/dec_o_left_path_addr[3]
|
CTOF_DEL --- 0.495 R16C30C.C1 to R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
|
CTOF_DEL --- 0.495 R18C22B.A1 to R18C22B.F1 cpu0/dec_regs/SLICE_846
|
ROUTE 1 1.023 R16C30C.F1 to R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
|
ROUTE 25 3.725 R18C22B.F1 to R9C25A.A0 cpu0/dec_o_alu_size
|
CTOF_DEL --- 0.495 R14C30D.B0 to R14C30D.F0 cpu0/alu/alu16/SLICE_1054
|
CTOF_DEL --- 0.495 R9C25A.A0 to R9C25A.F0 cpu0/SLICE_862
|
ROUTE 2 1.640 R14C30D.F0 to R12C24A.A0 cpu0/datamux_o_dest[10]
|
ROUTE 2 2.557 R9C25A.F0 to R9C20D.B1 cpu0/datamux_o_dest[11]
|
CTOF_DEL --- 0.495 R12C24A.A0 to R12C24A.F0 cpu0/regs/SLICE_362
|
CTOF_DEL --- 0.495 R9C20D.B1 to R9C20D.F1 cpu0/regs/SLICE_945
|
ROUTE 6 0.780 R12C24A.F0 to R11C24B.C0 cpu0/regs/left_1[10]
|
ROUTE 6 2.382 R9C20D.F1 to R10C16B.D0 cpu0/regs/left_1[11]
|
CTOF_DEL --- 0.495 R11C24B.C0 to R11C24B.F0 cpu0/regs/SLICE_1191
|
CTOF_DEL --- 0.495 R10C16B.D0 to R10C16B.F0 cpu0/regs/SLICE_1220
|
ROUTE 1 0.958 R11C24B.F0 to R10C23D.D1 cpu0/regs/N_289
|
ROUTE 1 1.450 R10C16B.F0 to R10C12D.B1 cpu0/regs/N_256
|
CTOF_DEL --- 0.495 R10C23D.D1 to R10C23D.F1 cpu0/regs/SLICE_949
|
CTOF_DEL --- 0.495 R10C12D.B1 to R10C12D.F1 cpu0/regs/SLICE_934
|
ROUTE 1 0.436 R10C23D.F1 to R10C23D.C0 cpu0/regs/SU_16[10]
|
ROUTE 1 0.436 R10C12D.F1 to R10C12D.C0 cpu0/regs/SS_16[11]
|
CTOF_DEL --- 0.495 R10C23D.C0 to R10C23D.F0 cpu0/regs/SLICE_949
|
CTOF_DEL --- 0.495 R10C12D.C0 to R10C12D.F0 cpu0/regs/SLICE_934
|
ROUTE 1 1.506 R10C23D.F0 to R11C23C.C0 cpu0/regs/SU_217_i1_mux
|
ROUTE 1 1.506 R10C12D.F0 to R11C12C.C1 cpu0/regs/SS_226_i1_mux
|
C0TOFCO_DE --- 1.023 R11C23C.C0 to R11C23C.FCO cpu0/regs/SLICE_57
|
C1TOFCO_DE --- 0.889 R11C12C.C1 to R11C12C.FCO cpu0/regs/SLICE_66
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
ROUTE 1 0.000 R11C12C.FCO to R11C12D.FCI cpu0/regs/SS_cry[11]
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
FCITOFCO_D --- 0.162 R11C12D.FCI to R11C12D.FCO cpu0/regs/SLICE_65
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
ROUTE 1 0.000 R11C12D.FCO to R11C13A.FCI cpu0/regs/SS_cry[13]
|
FCITOF0_DE --- 0.585 R11C24A.FCI to R11C24A.F0 cpu0/regs/SLICE_55
|
FCITOF0_DE --- 0.585 R11C13A.FCI to R11C13A.F0 cpu0/regs/SLICE_64
|
ROUTE 1 0.000 R11C24A.F0 to R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
|
ROUTE 1 0.000 R11C13A.F0 to R11C13A.DI0 cpu0/regs/SS_s[14] (to clk40_i_c)
|
--------
|
--------
|
24.525 (36.0% logic, 64.0% route), 18 logic levels.
|
33.513 (26.6% logic, 73.4% route), 18 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to SLICE_260:
|
Source Clock Path clk40_i to cpu0/SLICE_1217:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R12C21C.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R11C13A.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.324ns
|
Error: The following path exceeds requirements by 24.619ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_opcode[7] (from clk40_i_c +)
|
Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SS[13] (to clk40_i_c +)
|
|
|
Delay: 24.510ns (36.1% logic, 63.9% route), 19 logic levels.
|
Delay: 33.409ns (26.3% logic, 73.7% route), 17 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
24.510ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
33.409ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_65 exceeds
|
25.000ns delay constraint less
|
8.956ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.324ns
|
0.166ns DIN_SET requirement (totaling 8.790ns) by 24.619ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_65:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
REG_DEL --- 0.452 R12C21C.CLK to R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
ROUTE 42 3.151 R12C21C.Q1 to R18C26B.C1 cpu0/k_opcode[7]
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
CTOF_DEL --- 0.495 R18C26B.C1 to R18C26B.F1 cpu0/SLICE_726
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
ROUTE 13 2.235 R18C26B.F1 to R19C25B.A1 cpu0/state133_3
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
CTOF_DEL --- 0.495 R19C25B.A1 to R19C25B.F1 cpu0/dec_regs/SLICE_659
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
ROUTE 1 0.436 R19C25B.F1 to R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
CTOF_DEL --- 0.495 R19C25B.C0 to R19C25B.F0 cpu0/dec_regs/SLICE_659
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
ROUTE 2 1.343 R19C25B.F0 to R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
CTOF_DEL --- 0.495 R18C24D.B1 to R18C24D.F1 cpu0/SLICE_766
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
ROUTE 1 0.623 R18C24D.F1 to R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
CTOF_DEL --- 0.495 R17C24A.D1 to R17C24A.F1 cpu0/dec_regs/SLICE_813
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
ROUTE 6 0.675 R17C24A.F1 to R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
CTOF_DEL --- 0.495 R15C24D.D1 to R15C24D.F1 cpu0/dec_regs/SLICE_806
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
ROUTE 8 0.772 R15C24D.F1 to R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
CTOF_DEL --- 0.495 R15C24A.C1 to R15C24A.F1 cpu0/dec_regs/SLICE_802
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
ROUTE 5 1.441 R15C24A.F1 to R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
|
FCITOFCO_D --- 0.162 R19C19B.FCI to R19C19B.FCO cpu0/regs/ea/SLICE_40
|
MTOOFX_DEL --- 0.376 R17C25D.M0 to R17C25D.OFX0 cpu0/dec_regs/SLICE_264
|
ROUTE 1 0.000 R19C19B.FCO to R19C19C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
|
ROUTE 5 1.882 R17C25D.OFX0 to R18C22B.A1 cpu0/dec_o_left_path_addr[3]
|
FCITOF0_DE --- 0.585 R19C19C.FCI to R19C19C.F0 cpu0/regs/ea/SLICE_39
|
CTOF_DEL --- 0.495 R18C22B.A1 to R18C22B.F1 cpu0/dec_regs/SLICE_846
|
ROUTE 4 2.187 R19C19C.F0 to R16C33D.D0 cpu0/regs_o_eamem_addr[11]
|
ROUTE 25 3.725 R18C22B.F1 to R9C25A.A0 cpu0/dec_o_alu_size
|
CTOF_DEL --- 0.495 R16C33D.D0 to R16C33D.F0 cpu0/regs/SLICE_1180
|
CTOF_DEL --- 0.495 R9C25A.A0 to R9C25A.F0 cpu0/SLICE_862
|
ROUTE 1 1.004 R16C33D.F0 to R16C33B.B0 cpu0/regs/ea/N_1415
|
ROUTE 2 2.557 R9C25A.F0 to R9C20D.B1 cpu0/datamux_o_dest[11]
|
CTOF_DEL --- 0.495 R16C33B.B0 to R16C33B.F0 cpu0/SLICE_901
|
CTOF_DEL --- 0.495 R9C20D.B1 to R9C20D.F1 cpu0/regs/SLICE_945
|
ROUTE 2 2.179 R16C33B.F0 to R12C24A.D1 cpu0/datamux_o_dest[11]
|
ROUTE 6 2.382 R9C20D.F1 to R10C16B.D0 cpu0/regs/left_1[11]
|
CTOF_DEL --- 0.495 R12C24A.D1 to R12C24A.F1 cpu0/regs/SLICE_362
|
CTOF_DEL --- 0.495 R10C16B.D0 to R10C16B.F0 cpu0/regs/SLICE_1220
|
ROUTE 6 0.790 R12C24A.F1 to R12C26C.C0 cpu0/regs/left_1[11]
|
ROUTE 1 1.450 R10C16B.F0 to R10C12D.B1 cpu0/regs/N_256
|
CTOF_DEL --- 0.495 R12C26C.C0 to R12C26C.F0 cpu0/regs/SLICE_1192
|
CTOF_DEL --- 0.495 R10C12D.B1 to R10C12D.F1 cpu0/regs/SLICE_934
|
ROUTE 1 0.315 R12C26C.F0 to R12C26A.D1 cpu0/regs/N_290
|
ROUTE 1 0.436 R10C12D.F1 to R10C12D.C0 cpu0/regs/SS_16[11]
|
CTOF_DEL --- 0.495 R12C26A.D1 to R12C26A.F1 cpu0/regs/SLICE_950
|
CTOF_DEL --- 0.495 R10C12D.C0 to R10C12D.F0 cpu0/regs/SLICE_934
|
ROUTE 1 0.626 R12C26A.F1 to R12C26A.D0 cpu0/regs/SU_16[11]
|
ROUTE 1 1.506 R10C12D.F0 to R11C12C.C1 cpu0/regs/SS_226_i1_mux
|
CTOF_DEL --- 0.495 R12C26A.D0 to R12C26A.F0 cpu0/regs/SLICE_950
|
C1TOFCO_DE --- 0.889 R11C12C.C1 to R11C12C.FCO cpu0/regs/SLICE_66
|
ROUTE 1 1.506 R12C26A.F0 to R11C23C.C1 cpu0/regs/SU_218_i1_mux
|
ROUTE 1 0.000 R11C12C.FCO to R11C12D.FCI cpu0/regs/SS_cry[11]
|
C1TOFCO_DE --- 0.889 R11C23C.C1 to R11C23C.FCO cpu0/regs/SLICE_57
|
FCITOF1_DE --- 0.643 R11C12D.FCI to R11C12D.F1 cpu0/regs/SLICE_65
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
ROUTE 1 0.000 R11C12D.F1 to R11C12D.DI1 cpu0/regs/SS_s[13] (to clk40_i_c)
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
|
FCITOF1_DE --- 0.643 R11C24A.FCI to R11C24A.F1 cpu0/regs/SLICE_55
|
|
ROUTE 1 0.000 R11C24A.F1 to R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
|
|
--------
|
--------
|
24.510 (36.1% logic, 63.9% route), 19 logic levels.
|
33.409 (26.3% logic, 73.7% route), 17 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to SLICE_260:
|
Source Clock Path clk40_i to cpu0/SLICE_1217:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R12C21C.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_65:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R11C12D.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.351ns
|
Error: The following path exceeds requirements by 24.561ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_opcode[7] (from clk40_i_c +)
|
Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SS[12] (to clk40_i_c +)
|
|
|
Delay: 24.483ns (36.2% logic, 63.8% route), 19 logic levels.
|
Delay: 33.351ns (26.2% logic, 73.8% route), 17 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
24.483ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
33.351ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_65 exceeds
|
25.000ns delay constraint less
|
8.956ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.351ns
|
0.166ns DIN_SET requirement (totaling 8.790ns) by 24.561ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_65:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
REG_DEL --- 0.452 R12C21C.CLK to R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
ROUTE 42 3.151 R12C21C.Q1 to R18C26B.C1 cpu0/k_opcode[7]
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
CTOF_DEL --- 0.495 R18C26B.C1 to R18C26B.F1 cpu0/SLICE_726
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
ROUTE 13 2.235 R18C26B.F1 to R19C25B.A1 cpu0/state133_3
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
CTOF_DEL --- 0.495 R19C25B.A1 to R19C25B.F1 cpu0/dec_regs/SLICE_659
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
ROUTE 1 0.436 R19C25B.F1 to R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
CTOF_DEL --- 0.495 R19C25B.C0 to R19C25B.F0 cpu0/dec_regs/SLICE_659
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
ROUTE 2 1.343 R19C25B.F0 to R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
CTOF_DEL --- 0.495 R18C24D.B1 to R18C24D.F1 cpu0/SLICE_766
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
ROUTE 1 0.623 R18C24D.F1 to R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
CTOF_DEL --- 0.495 R17C24A.D1 to R17C24A.F1 cpu0/dec_regs/SLICE_813
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
ROUTE 6 0.675 R17C24A.F1 to R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
CTOF_DEL --- 0.495 R15C24D.D1 to R15C24D.F1 cpu0/dec_regs/SLICE_806
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
ROUTE 8 0.772 R15C24D.F1 to R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
CTOF_DEL --- 0.495 R15C24A.C1 to R15C24A.F1 cpu0/dec_regs/SLICE_802
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
ROUTE 5 1.441 R15C24A.F1 to R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
|
FCITOF0_DE --- 0.585 R19C19B.FCI to R19C19B.F0 cpu0/regs/ea/SLICE_40
|
MTOOFX_DEL --- 0.376 R17C25D.M0 to R17C25D.OFX0 cpu0/dec_regs/SLICE_264
|
ROUTE 4 2.326 R19C19B.F0 to R16C33D.C1 cpu0/regs/regs_o_eamem_addr[9]
|
ROUTE 5 1.882 R17C25D.OFX0 to R18C22B.A1 cpu0/dec_o_left_path_addr[3]
|
CTOF_DEL --- 0.495 R16C33D.C1 to R16C33D.F1 cpu0/regs/SLICE_1180
|
CTOF_DEL --- 0.495 R18C22B.A1 to R18C22B.F1 cpu0/dec_regs/SLICE_846
|
ROUTE 1 1.023 R16C33D.F1 to R14C33A.B0 cpu0/regs/N_1413
|
ROUTE 25 3.725 R18C22B.F1 to R9C25A.A0 cpu0/dec_o_alu_size
|
CTOF_DEL --- 0.495 R14C33A.B0 to R14C33A.F0 cpu0/SLICE_974
|
CTOF_DEL --- 0.495 R9C25A.A0 to R9C25A.F0 cpu0/SLICE_862
|
ROUTE 2 1.971 R14C33A.F0 to R12C25C.D1 cpu0/datamux_o_dest[9]
|
ROUTE 2 2.557 R9C25A.F0 to R9C20D.B1 cpu0/datamux_o_dest[11]
|
CTOF_DEL --- 0.495 R12C25C.D1 to R12C25C.F1 cpu0/regs/SLICE_361
|
CTOF_DEL --- 0.495 R9C20D.B1 to R9C20D.F1 cpu0/regs/SLICE_945
|
ROUTE 6 0.675 R12C25C.F1 to R12C24B.D0 cpu0/regs/left_1[9]
|
ROUTE 6 2.382 R9C20D.F1 to R10C16B.D0 cpu0/regs/left_1[11]
|
CTOF_DEL --- 0.495 R12C24B.D0 to R12C24B.F0 cpu0/regs/SLICE_1190
|
CTOF_DEL --- 0.495 R10C16B.D0 to R10C16B.F0 cpu0/regs/SLICE_1220
|
ROUTE 1 0.986 R12C24B.F0 to R11C24D.A1 cpu0/regs/N_288
|
ROUTE 1 1.450 R10C16B.F0 to R10C12D.B1 cpu0/regs/N_256
|
CTOF_DEL --- 0.495 R11C24D.A1 to R11C24D.F1 cpu0/regs/SLICE_948
|
CTOF_DEL --- 0.495 R10C12D.B1 to R10C12D.F1 cpu0/regs/SLICE_934
|
ROUTE 1 0.436 R11C24D.F1 to R11C24D.C0 cpu0/regs/SU_16[9]
|
ROUTE 1 0.436 R10C12D.F1 to R10C12D.C0 cpu0/regs/SS_16[11]
|
CTOF_DEL --- 0.495 R11C24D.C0 to R11C24D.F0 cpu0/regs/SLICE_948
|
CTOF_DEL --- 0.495 R10C12D.C0 to R10C12D.F0 cpu0/regs/SLICE_934
|
ROUTE 1 1.163 R11C24D.F0 to R11C23B.C1 cpu0/regs/SU_216_i1_mux
|
ROUTE 1 1.506 R10C12D.F0 to R11C12C.C1 cpu0/regs/SS_226_i1_mux
|
C1TOFCO_DE --- 0.889 R11C23B.C1 to R11C23B.FCO cpu0/regs/SLICE_58
|
C1TOFCO_DE --- 0.889 R11C12C.C1 to R11C12C.FCO cpu0/regs/SLICE_66
|
ROUTE 1 0.000 R11C23B.FCO to R11C23C.FCI cpu0/regs/SU_cry[9]
|
ROUTE 1 0.000 R11C12C.FCO to R11C12D.FCI cpu0/regs/SS_cry[11]
|
FCITOFCO_D --- 0.162 R11C23C.FCI to R11C23C.FCO cpu0/regs/SLICE_57
|
FCITOF0_DE --- 0.585 R11C12D.FCI to R11C12D.F0 cpu0/regs/SLICE_65
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
ROUTE 1 0.000 R11C12D.F0 to R11C12D.DI0 cpu0/regs/SS_s[12] (to clk40_i_c)
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
|
FCITOF1_DE --- 0.643 R11C24A.FCI to R11C24A.F1 cpu0/regs/SLICE_55
|
|
ROUTE 1 0.000 R11C24A.F1 to R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
|
|
--------
|
--------
|
24.483 (36.2% logic, 63.8% route), 19 logic levels.
|
33.351 (26.2% logic, 73.8% route), 17 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to SLICE_260:
|
Source Clock Path clk40_i to cpu0/SLICE_1217:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R12C21C.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_65:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R11C12D.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.362ns
|
Error: The following path exceeds requirements by 24.119ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_ind_ea[1] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_opcode[7] (from clk40_i_c +)
|
Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SU[15] (to clk40_i_c +)
|
|
|
Delay: 24.472ns (36.3% logic, 63.7% route), 18 logic levels.
|
Delay: 32.909ns (30.3% logic, 69.7% route), 22 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
24.472ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
32.909ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_55 exceeds
|
25.000ns delay constraint less
|
8.956ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.362ns
|
0.166ns DIN_SET requirement (totaling 8.790ns) by 24.119ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q1 SLICE_260 (from cpu_clkgen)
|
REG_DEL --- 0.452 R12C21C.CLK to R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
|
ROUTE 30 1.613 R18C14A.Q1 to R18C24D.D1 cpu0/k_ind_ea[1]
|
ROUTE 42 3.151 R12C21C.Q1 to R18C26B.C1 cpu0/k_opcode[7]
|
CTOF_DEL --- 0.495 R18C24D.D1 to R18C24D.F1 cpu0/SLICE_337
|
CTOF_DEL --- 0.495 R18C26B.C1 to R18C26B.F1 cpu0/SLICE_726
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
ROUTE 13 2.235 R18C26B.F1 to R19C25B.A1 cpu0/state133_3
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
CTOF_DEL --- 0.495 R19C25B.A1 to R19C25B.F1 cpu0/dec_regs/SLICE_659
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
ROUTE 1 0.436 R19C25B.F1 to R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
CTOF_DEL --- 0.495 R19C25B.C0 to R19C25B.F0 cpu0/dec_regs/SLICE_659
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
ROUTE 2 1.343 R19C25B.F0 to R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
CTOF_DEL --- 0.495 R18C24D.B1 to R18C24D.F1 cpu0/SLICE_766
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
ROUTE 1 0.623 R18C24D.F1 to R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
CTOF_DEL --- 0.495 R17C24A.D1 to R17C24A.F1 cpu0/dec_regs/SLICE_813
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
ROUTE 6 0.675 R17C24A.F1 to R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
CTOF_DEL --- 0.495 R15C24D.D1 to R15C24D.F1 cpu0/dec_regs/SLICE_806
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
ROUTE 8 0.772 R15C24D.F1 to R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
CTOF_DEL --- 0.495 R15C24A.C1 to R15C24A.F1 cpu0/dec_regs/SLICE_802
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
ROUTE 5 1.441 R15C24A.F1 to R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
|
FCITOF1_DE --- 0.643 R19C19B.FCI to R19C19B.F1 cpu0/regs/ea/SLICE_40
|
MTOOFX_DEL --- 0.376 R17C25D.M0 to R17C25D.OFX0 cpu0/dec_regs/SLICE_264
|
ROUTE 4 2.307 R19C19B.F1 to R16C30C.C1 cpu0/regs_o_eamem_addr[10]
|
ROUTE 5 1.882 R17C25D.OFX0 to R18C22B.A1 cpu0/dec_o_left_path_addr[3]
|
CTOF_DEL --- 0.495 R16C30C.C1 to R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
|
CTOF_DEL --- 0.495 R18C22B.A1 to R18C22B.F1 cpu0/dec_regs/SLICE_846
|
ROUTE 1 1.023 R16C30C.F1 to R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
|
ROUTE 25 2.485 R18C22B.F1 to R10C25C.B1 cpu0/dec_o_alu_size
|
CTOF_DEL --- 0.495 R14C30D.B0 to R14C30D.F0 cpu0/alu/alu16/SLICE_1054
|
CTOOFX_DEL --- 0.721 R10C25C.B1 to R10C25C.OFX0 cpu0/alu/alu8/datamux_o_dest[2]/SLICE_600
|
ROUTE 2 1.640 R14C30D.F0 to R12C24A.A0 cpu0/datamux_o_dest[10]
|
ROUTE 2 1.513 R10C25C.OFX0 to R9C23D.C0 cpu0/datamux_o_dest[2]
|
CTOF_DEL --- 0.495 R12C24A.A0 to R12C24A.F0 cpu0/regs/SLICE_362
|
CTOF_DEL --- 0.495 R9C23D.C0 to R9C23D.F0 cpu0/regs/SLICE_895
|
ROUTE 6 0.780 R12C24A.F0 to R11C24B.C0 cpu0/regs/left_1[10]
|
ROUTE 9 2.274 R9C23D.F0 to R10C16D.A0 cpu0/regs/left_1[2]
|
CTOF_DEL --- 0.495 R11C24B.C0 to R11C24B.F0 cpu0/regs/SLICE_1191
|
CTOF_DEL --- 0.495 R10C16D.A0 to R10C16D.F0 cpu0/regs/SLICE_1219
|
ROUTE 1 0.958 R11C24B.F0 to R10C23D.D1 cpu0/regs/N_289
|
ROUTE 1 1.801 R10C16D.F0 to R10C10A.A1 cpu0/regs/N_283
|
CTOF_DEL --- 0.495 R10C23D.D1 to R10C23D.F1 cpu0/regs/SLICE_949
|
CTOF_DEL --- 0.495 R10C10A.A1 to R10C10A.F1 cpu0/regs/SLICE_909
|
ROUTE 1 0.436 R10C23D.F1 to R10C23D.C0 cpu0/regs/SU_16[10]
|
ROUTE 1 0.693 R10C10A.F1 to R10C10A.B0 cpu0/regs/SU_16[2]
|
CTOF_DEL --- 0.495 R10C23D.C0 to R10C23D.F0 cpu0/regs/SLICE_949
|
CTOF_DEL --- 0.495 R10C10A.B0 to R10C10A.F0 cpu0/regs/SLICE_909
|
ROUTE 1 1.506 R10C23D.F0 to R11C23C.C0 cpu0/regs/SU_217_i1_mux
|
ROUTE 1 1.620 R10C10A.F0 to R12C9C.C0 cpu0/regs/SU_201_i1_mux
|
C0TOFCO_DE --- 1.023 R11C23C.C0 to R11C23C.FCO cpu0/regs/SLICE_57
|
C0TOFCO_DE --- 1.023 R12C9C.C0 to R12C9C.FCO cpu0/regs/SLICE_61
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
ROUTE 1 0.000 R12C9C.FCO to R12C9D.FCI cpu0/regs/SU_cry[3]
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
FCITOFCO_D --- 0.162 R12C9D.FCI to R12C9D.FCO cpu0/regs/SLICE_60
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
ROUTE 1 0.000 R12C9D.FCO to R12C10A.FCI cpu0/regs/SU_cry[5]
|
FCITOF1_DE --- 0.643 R11C24A.FCI to R11C24A.F1 cpu0/regs/SLICE_55
|
FCITOFCO_D --- 0.162 R12C10A.FCI to R12C10A.FCO cpu0/regs/SLICE_59
|
ROUTE 1 0.000 R11C24A.F1 to R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
|
ROUTE 1 0.000 R12C10A.FCO to R12C10B.FCI cpu0/regs/SU_cry[7]
|
|
FCITOFCO_D --- 0.162 R12C10B.FCI to R12C10B.FCO cpu0/regs/SLICE_58
|
|
ROUTE 1 0.000 R12C10B.FCO to R12C10C.FCI cpu0/regs/SU_cry[9]
|
|
FCITOFCO_D --- 0.162 R12C10C.FCI to R12C10C.FCO cpu0/regs/SLICE_57
|
|
ROUTE 1 0.000 R12C10C.FCO to R12C10D.FCI cpu0/regs/SU_cry[11]
|
|
FCITOFCO_D --- 0.162 R12C10D.FCI to R12C10D.FCO cpu0/regs/SLICE_56
|
|
ROUTE 1 0.000 R12C10D.FCO to R12C11A.FCI cpu0/regs/SU_cry[13]
|
|
FCITOF1_DE --- 0.643 R12C11A.FCI to R12C11A.F1 cpu0/regs/SLICE_55
|
|
ROUTE 1 0.000 R12C11A.F1 to R12C11A.DI1 cpu0/regs/SU_s[15] (to clk40_i_c)
|
--------
|
--------
|
24.472 (36.3% logic, 63.7% route), 18 logic levels.
|
32.909 (30.3% logic, 69.7% route), 22 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to SLICE_260:
|
Source Clock Path clk40_i to cpu0/SLICE_1217:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R12C21C.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R12C11A.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.382ns
|
Error: The following path exceeds requirements by 24.061ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_opcode[7] (from clk40_i_c +)
|
Destination: FF Data in cpu0/regs/SU[14] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SU[14] (to clk40_i_c +)
|
|
|
Delay: 24.452ns (36.0% logic, 64.0% route), 19 logic levels.
|
Delay: 32.851ns (30.2% logic, 69.8% route), 22 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
24.452ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
32.851ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_55 exceeds
|
25.000ns delay constraint less
|
8.956ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.382ns
|
0.166ns DIN_SET requirement (totaling 8.790ns) by 24.061ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
REG_DEL --- 0.452 R12C21C.CLK to R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
ROUTE 42 3.151 R12C21C.Q1 to R18C26B.C1 cpu0/k_opcode[7]
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
CTOF_DEL --- 0.495 R18C26B.C1 to R18C26B.F1 cpu0/SLICE_726
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
ROUTE 13 2.235 R18C26B.F1 to R19C25B.A1 cpu0/state133_3
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
CTOF_DEL --- 0.495 R19C25B.A1 to R19C25B.F1 cpu0/dec_regs/SLICE_659
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
ROUTE 1 0.436 R19C25B.F1 to R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
CTOF_DEL --- 0.495 R19C25B.C0 to R19C25B.F0 cpu0/dec_regs/SLICE_659
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
ROUTE 2 1.343 R19C25B.F0 to R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
CTOF_DEL --- 0.495 R18C24D.B1 to R18C24D.F1 cpu0/SLICE_766
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
ROUTE 1 0.623 R18C24D.F1 to R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
CTOF_DEL --- 0.495 R17C24A.D1 to R17C24A.F1 cpu0/dec_regs/SLICE_813
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
ROUTE 6 0.675 R17C24A.F1 to R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
CTOF_DEL --- 0.495 R15C24D.D1 to R15C24D.F1 cpu0/dec_regs/SLICE_806
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
ROUTE 8 0.772 R15C24D.F1 to R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
CTOF_DEL --- 0.495 R15C24A.C1 to R15C24A.F1 cpu0/dec_regs/SLICE_802
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
ROUTE 5 1.441 R15C24A.F1 to R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
|
FCITOFCO_D --- 0.162 R19C19B.FCI to R19C19B.FCO cpu0/regs/ea/SLICE_40
|
MTOOFX_DEL --- 0.376 R17C25D.M0 to R17C25D.OFX0 cpu0/dec_regs/SLICE_264
|
ROUTE 1 0.000 R19C19B.FCO to R19C19C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
|
ROUTE 5 1.882 R17C25D.OFX0 to R18C22B.A1 cpu0/dec_o_left_path_addr[3]
|
FCITOF0_DE --- 0.585 R19C19C.FCI to R19C19C.F0 cpu0/regs/ea/SLICE_39
|
CTOF_DEL --- 0.495 R18C22B.A1 to R18C22B.F1 cpu0/dec_regs/SLICE_846
|
ROUTE 4 2.187 R19C19C.F0 to R16C33D.D0 cpu0/regs_o_eamem_addr[11]
|
ROUTE 25 2.485 R18C22B.F1 to R10C25C.B1 cpu0/dec_o_alu_size
|
CTOF_DEL --- 0.495 R16C33D.D0 to R16C33D.F0 cpu0/regs/SLICE_1180
|
CTOOFX_DEL --- 0.721 R10C25C.B1 to R10C25C.OFX0 cpu0/alu/alu8/datamux_o_dest[2]/SLICE_600
|
ROUTE 1 1.004 R16C33D.F0 to R16C33B.B0 cpu0/regs/ea/N_1415
|
ROUTE 2 1.513 R10C25C.OFX0 to R9C23D.C0 cpu0/datamux_o_dest[2]
|
CTOF_DEL --- 0.495 R16C33B.B0 to R16C33B.F0 cpu0/SLICE_901
|
CTOF_DEL --- 0.495 R9C23D.C0 to R9C23D.F0 cpu0/regs/SLICE_895
|
ROUTE 2 2.179 R16C33B.F0 to R12C24A.D1 cpu0/datamux_o_dest[11]
|
ROUTE 9 2.274 R9C23D.F0 to R10C16D.A0 cpu0/regs/left_1[2]
|
CTOF_DEL --- 0.495 R12C24A.D1 to R12C24A.F1 cpu0/regs/SLICE_362
|
CTOF_DEL --- 0.495 R10C16D.A0 to R10C16D.F0 cpu0/regs/SLICE_1219
|
ROUTE 6 0.790 R12C24A.F1 to R12C26C.C0 cpu0/regs/left_1[11]
|
ROUTE 1 1.801 R10C16D.F0 to R10C10A.A1 cpu0/regs/N_283
|
CTOF_DEL --- 0.495 R12C26C.C0 to R12C26C.F0 cpu0/regs/SLICE_1192
|
CTOF_DEL --- 0.495 R10C10A.A1 to R10C10A.F1 cpu0/regs/SLICE_909
|
ROUTE 1 0.315 R12C26C.F0 to R12C26A.D1 cpu0/regs/N_290
|
ROUTE 1 0.693 R10C10A.F1 to R10C10A.B0 cpu0/regs/SU_16[2]
|
CTOF_DEL --- 0.495 R12C26A.D1 to R12C26A.F1 cpu0/regs/SLICE_950
|
CTOF_DEL --- 0.495 R10C10A.B0 to R10C10A.F0 cpu0/regs/SLICE_909
|
ROUTE 1 0.626 R12C26A.F1 to R12C26A.D0 cpu0/regs/SU_16[11]
|
ROUTE 1 1.620 R10C10A.F0 to R12C9C.C0 cpu0/regs/SU_201_i1_mux
|
CTOF_DEL --- 0.495 R12C26A.D0 to R12C26A.F0 cpu0/regs/SLICE_950
|
C0TOFCO_DE --- 1.023 R12C9C.C0 to R12C9C.FCO cpu0/regs/SLICE_61
|
ROUTE 1 1.506 R12C26A.F0 to R11C23C.C1 cpu0/regs/SU_218_i1_mux
|
ROUTE 1 0.000 R12C9C.FCO to R12C9D.FCI cpu0/regs/SU_cry[3]
|
C1TOFCO_DE --- 0.889 R11C23C.C1 to R11C23C.FCO cpu0/regs/SLICE_57
|
FCITOFCO_D --- 0.162 R12C9D.FCI to R12C9D.FCO cpu0/regs/SLICE_60
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
ROUTE 1 0.000 R12C9D.FCO to R12C10A.FCI cpu0/regs/SU_cry[5]
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
FCITOFCO_D --- 0.162 R12C10A.FCI to R12C10A.FCO cpu0/regs/SLICE_59
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
ROUTE 1 0.000 R12C10A.FCO to R12C10B.FCI cpu0/regs/SU_cry[7]
|
FCITOF0_DE --- 0.585 R11C24A.FCI to R11C24A.F0 cpu0/regs/SLICE_55
|
FCITOFCO_D --- 0.162 R12C10B.FCI to R12C10B.FCO cpu0/regs/SLICE_58
|
ROUTE 1 0.000 R11C24A.F0 to R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
|
ROUTE 1 0.000 R12C10B.FCO to R12C10C.FCI cpu0/regs/SU_cry[9]
|
|
FCITOFCO_D --- 0.162 R12C10C.FCI to R12C10C.FCO cpu0/regs/SLICE_57
|
|
ROUTE 1 0.000 R12C10C.FCO to R12C10D.FCI cpu0/regs/SU_cry[11]
|
|
FCITOFCO_D --- 0.162 R12C10D.FCI to R12C10D.FCO cpu0/regs/SLICE_56
|
|
ROUTE 1 0.000 R12C10D.FCO to R12C11A.FCI cpu0/regs/SU_cry[13]
|
|
FCITOF0_DE --- 0.585 R12C11A.FCI to R12C11A.F0 cpu0/regs/SLICE_55
|
|
ROUTE 1 0.000 R12C11A.F0 to R12C11A.DI0 cpu0/regs/SU_s[14] (to clk40_i_c)
|
--------
|
--------
|
24.452 (36.0% logic, 64.0% route), 19 logic levels.
|
32.851 (30.2% logic, 69.8% route), 22 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to SLICE_260:
|
Source Clock Path clk40_i to cpu0/SLICE_1217:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R12C21C.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R12C11A.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.391ns
|
Error: The following path exceeds requirements by 23.971ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/regs/IY_pipe_14 (from cpu_clkgen +)
|
Source: FF Q cpu0/k_opcode[5] (from clk40_i_c +)
|
Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SS[15] (to clk40_i_c +)
|
|
|
Delay: 24.443ns (39.4% logic, 60.6% route), 20 logic levels.
|
Delay: 32.761ns (25.8% logic, 74.2% route), 17 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
24.443ns physical path delay cpu0/regs/SLICE_323 to cpu0/regs/SLICE_55 meets
|
32.761ns physical path delay cpu0/SLICE_1144 to cpu0/regs/SLICE_64 exceeds
|
25.000ns delay constraint less
|
8.956ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.391ns
|
0.166ns DIN_SET requirement (totaling 8.790ns) by 23.971ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path cpu0/regs/SLICE_323 to cpu0/regs/SLICE_55:
|
Data path cpu0/SLICE_1144 to cpu0/regs/SLICE_64:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R16C22A.CLK to R16C22A.Q0 cpu0/regs/SLICE_323 (from cpu_clkgen)
|
REG_DEL --- 0.452 R12C21A.CLK to R12C21A.Q1 cpu0/SLICE_1144 (from clk40_i_c)
|
ROUTE 16 1.390 R16C22A.Q0 to R16C25A.A1 cpu0/regs/IY_1_sqmuxaf
|
ROUTE 52 4.508 R12C21A.Q1 to R19C22A.A0 cpu0/k_opcode[5]
|
CTOF_DEL --- 0.495 R16C25A.A1 to R16C25A.F1 cpu0/regs/SLICE_1012
|
CTOF_DEL --- 0.495 R19C22A.A0 to R19C22A.F0 cpu0/SLICE_772
|
ROUTE 1 0.693 R16C25A.F1 to R16C25A.B0 cpu0/regs/N_665
|
ROUTE 2 1.308 R19C22A.F0 to R18C24A.A0 cpu0/un1_k_opcode_3_4
|
CTOF_DEL --- 0.495 R16C25A.B0 to R16C25A.F0 cpu0/regs/SLICE_1012
|
CTOF_DEL --- 0.495 R18C24A.A0 to R18C24A.F0 cpu0/dec_regs/SLICE_1118
|
ROUTE 3 1.435 R16C25A.F0 to R21C25B.C1 cpu0/regs/IY[0]
|
ROUTE 1 0.693 R18C24A.F0 to R18C24B.B1 cpu0/dec_regs/path_left_addr79
|
CTOOFX_DEL --- 0.721 R21C25B.C1 to R21C25B.OFX0 cpu0/regs/ea/ea_reg_3[0]/SLICE_511
|
CTOF_DEL --- 0.495 R18C24B.B1 to R18C24B.F1 cpu0/dec_regs/SLICE_771
|
ROUTE 5 1.487 R21C25B.OFX0 to R21C19D.D0 cpu0/regs/ea_reg[0]
|
ROUTE 1 0.964 R18C24B.F1 to R17C24A.A1 cpu0/dec_regs/un1_path_left_addr75_1_0
|
CTOF_DEL --- 0.495 R21C19D.D0 to R21C19D.F0 cpu0/regs/SLICE_917
|
CTOF_DEL --- 0.495 R17C24A.A1 to R17C24A.F1 cpu0/dec_regs/SLICE_813
|
ROUTE 2 1.152 R21C19D.F0 to R19C18A.C1 cpu0/regs/ea/N_72
|
ROUTE 6 0.675 R17C24A.F1 to R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
|
C1TOFCO_DE --- 0.889 R19C18A.C1 to R19C18A.FCO cpu0/regs/ea/SLICE_45
|
CTOF_DEL --- 0.495 R15C24D.D1 to R15C24D.F1 cpu0/dec_regs/SLICE_806
|
ROUTE 1 0.000 R19C18A.FCO to R19C18B.FCI cpu0/regs/ea/eamem_addr_o_cry_0
|
ROUTE 8 0.772 R15C24D.F1 to R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
|
FCITOFCO_D --- 0.162 R19C18B.FCI to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
CTOF_DEL --- 0.495 R15C24A.C1 to R15C24A.F1 cpu0/dec_regs/SLICE_802
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
ROUTE 5 1.441 R15C24A.F1 to R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
MTOOFX_DEL --- 0.376 R17C25D.M0 to R17C25D.OFX0 cpu0/dec_regs/SLICE_264
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
ROUTE 5 1.882 R17C25D.OFX0 to R18C22B.A1 cpu0/dec_o_left_path_addr[3]
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
CTOF_DEL --- 0.495 R18C22B.A1 to R18C22B.F1 cpu0/dec_regs/SLICE_846
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
ROUTE 25 3.725 R18C22B.F1 to R9C25A.A0 cpu0/dec_o_alu_size
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
CTOF_DEL --- 0.495 R9C25A.A0 to R9C25A.F0 cpu0/SLICE_862
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
ROUTE 2 2.557 R9C25A.F0 to R9C20D.B1 cpu0/datamux_o_dest[11]
|
FCITOF1_DE --- 0.643 R19C19B.FCI to R19C19B.F1 cpu0/regs/ea/SLICE_40
|
CTOF_DEL --- 0.495 R9C20D.B1 to R9C20D.F1 cpu0/regs/SLICE_945
|
ROUTE 4 2.307 R19C19B.F1 to R16C30C.C1 cpu0/regs_o_eamem_addr[10]
|
ROUTE 6 2.382 R9C20D.F1 to R10C16B.D0 cpu0/regs/left_1[11]
|
CTOF_DEL --- 0.495 R16C30C.C1 to R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
|
CTOF_DEL --- 0.495 R10C16B.D0 to R10C16B.F0 cpu0/regs/SLICE_1220
|
ROUTE 1 1.023 R16C30C.F1 to R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
|
ROUTE 1 1.450 R10C16B.F0 to R10C12D.B1 cpu0/regs/N_256
|
CTOF_DEL --- 0.495 R14C30D.B0 to R14C30D.F0 cpu0/alu/alu16/SLICE_1054
|
CTOF_DEL --- 0.495 R10C12D.B1 to R10C12D.F1 cpu0/regs/SLICE_934
|
ROUTE 2 1.640 R14C30D.F0 to R12C24A.A0 cpu0/datamux_o_dest[10]
|
ROUTE 1 0.436 R10C12D.F1 to R10C12D.C0 cpu0/regs/SS_16[11]
|
CTOF_DEL --- 0.495 R12C24A.A0 to R12C24A.F0 cpu0/regs/SLICE_362
|
CTOF_DEL --- 0.495 R10C12D.C0 to R10C12D.F0 cpu0/regs/SLICE_934
|
ROUTE 6 0.780 R12C24A.F0 to R11C24B.C0 cpu0/regs/left_1[10]
|
ROUTE 1 1.506 R10C12D.F0 to R11C12C.C1 cpu0/regs/SS_226_i1_mux
|
CTOF_DEL --- 0.495 R11C24B.C0 to R11C24B.F0 cpu0/regs/SLICE_1191
|
C1TOFCO_DE --- 0.889 R11C12C.C1 to R11C12C.FCO cpu0/regs/SLICE_66
|
ROUTE 1 0.958 R11C24B.F0 to R10C23D.D1 cpu0/regs/N_289
|
ROUTE 1 0.000 R11C12C.FCO to R11C12D.FCI cpu0/regs/SS_cry[11]
|
CTOF_DEL --- 0.495 R10C23D.D1 to R10C23D.F1 cpu0/regs/SLICE_949
|
FCITOFCO_D --- 0.162 R11C12D.FCI to R11C12D.FCO cpu0/regs/SLICE_65
|
ROUTE 1 0.436 R10C23D.F1 to R10C23D.C0 cpu0/regs/SU_16[10]
|
ROUTE 1 0.000 R11C12D.FCO to R11C13A.FCI cpu0/regs/SS_cry[13]
|
CTOF_DEL --- 0.495 R10C23D.C0 to R10C23D.F0 cpu0/regs/SLICE_949
|
FCITOF1_DE --- 0.643 R11C13A.FCI to R11C13A.F1 cpu0/regs/SLICE_64
|
ROUTE 1 1.506 R10C23D.F0 to R11C23C.C0 cpu0/regs/SU_217_i1_mux
|
ROUTE 1 0.000 R11C13A.F1 to R11C13A.DI1 cpu0/regs/SS_s[15] (to clk40_i_c)
|
C0TOFCO_DE --- 1.023 R11C23C.C0 to R11C23C.FCO cpu0/regs/SLICE_57
|
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
|
FCITOF1_DE --- 0.643 R11C24A.FCI to R11C24A.F1 cpu0/regs/SLICE_55
|
|
ROUTE 1 0.000 R11C24A.F1 to R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
|
|
--------
|
--------
|
24.443 (39.4% logic, 60.6% route), 20 logic levels.
|
32.761 (25.8% logic, 74.2% route), 17 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to cpu0/regs/SLICE_323:
|
Source Clock Path clk40_i to cpu0/SLICE_1144:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R16C22A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R12C21A.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R11C13A.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.396ns
|
Error: The following path exceeds requirements by 23.957ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_opcode[7] (from clk40_i_c +)
|
Destination: FF Data in cpu0/regs/SS[15] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SU[13] (to clk40_i_c +)
|
|
|
Delay: 24.438ns (36.4% logic, 63.6% route), 18 logic levels.
|
Delay: 32.747ns (29.9% logic, 70.1% route), 21 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
24.438ns physical path delay SLICE_260 to cpu0/regs/SLICE_64 meets
|
32.747ns physical path delay cpu0/SLICE_1217 to cpu0/regs/SLICE_56 exceeds
|
25.000ns delay constraint less
|
8.956ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.396ns
|
0.166ns DIN_SET requirement (totaling 8.790ns) by 23.957ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path SLICE_260 to cpu0/regs/SLICE_64:
|
Data path cpu0/SLICE_1217 to cpu0/regs/SLICE_56:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
REG_DEL --- 0.452 R12C21C.CLK to R12C21C.Q1 cpu0/SLICE_1217 (from clk40_i_c)
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
ROUTE 42 3.151 R12C21C.Q1 to R18C26B.C1 cpu0/k_opcode[7]
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
CTOF_DEL --- 0.495 R18C26B.C1 to R18C26B.F1 cpu0/SLICE_726
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
ROUTE 13 2.235 R18C26B.F1 to R19C25B.A1 cpu0/state133_3
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
CTOF_DEL --- 0.495 R19C25B.A1 to R19C25B.F1 cpu0/dec_regs/SLICE_659
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
ROUTE 1 0.436 R19C25B.F1 to R19C25B.C0 cpu0/dec_regs/un1_path_left_addr85_1_1_2
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
CTOF_DEL --- 0.495 R19C25B.C0 to R19C25B.F0 cpu0/dec_regs/SLICE_659
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
ROUTE 2 1.343 R19C25B.F0 to R18C24D.B1 cpu0/dec_regs/un1_path_left_addr85_1_0
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
CTOF_DEL --- 0.495 R18C24D.B1 to R18C24D.F1 cpu0/SLICE_766
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
ROUTE 1 0.623 R18C24D.F1 to R17C24A.D1 cpu0/dec_regs/un1_path_left_addr75_1_4
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
CTOF_DEL --- 0.495 R17C24A.D1 to R17C24A.F1 cpu0/dec_regs/SLICE_813
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
ROUTE 6 0.675 R17C24A.F1 to R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
CTOF_DEL --- 0.495 R15C24D.D1 to R15C24D.F1 cpu0/dec_regs/SLICE_806
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
ROUTE 8 0.772 R15C24D.F1 to R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
|
FCITOF1_DE --- 0.643 R19C19A.FCI to R19C19A.F1 cpu0/regs/ea/SLICE_41
|
CTOF_DEL --- 0.495 R15C24A.C1 to R15C24A.F1 cpu0/dec_regs/SLICE_802
|
ROUTE 4 2.403 R19C19A.F1 to R16C32D.D0 cpu0/regs/ea/regs_o_eamem_addr[8]
|
ROUTE 5 1.441 R15C24A.F1 to R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
|
CTOF_DEL --- 0.495 R16C32D.D0 to R16C32D.F0 cpu0/regs/SLICE_922
|
MTOOFX_DEL --- 0.376 R17C25D.M0 to R17C25D.OFX0 cpu0/dec_regs/SLICE_264
|
ROUTE 1 0.645 R16C32D.F0 to R14C32C.D0 cpu0/regs/ea/N_1412
|
ROUTE 5 1.882 R17C25D.OFX0 to R18C22B.A1 cpu0/dec_o_left_path_addr[3]
|
CTOF_DEL --- 0.495 R14C32C.D0 to R14C32C.F0 cpu0/SLICE_900
|
CTOF_DEL --- 0.495 R18C22B.A1 to R18C22B.F1 cpu0/dec_regs/SLICE_846
|
ROUTE 2 1.704 R14C32C.F0 to R12C25C.D0 cpu0/datamux_o_dest[8]
|
ROUTE 25 2.485 R18C22B.F1 to R10C25C.B1 cpu0/dec_o_alu_size
|
CTOF_DEL --- 0.495 R12C25C.D0 to R12C25C.F0 cpu0/regs/SLICE_361
|
CTOOFX_DEL --- 0.721 R10C25C.B1 to R10C25C.OFX0 cpu0/alu/alu8/datamux_o_dest[2]/SLICE_600
|
ROUTE 6 0.469 R12C25C.F0 to R12C25B.C1 cpu0/regs/left_1[8]
|
ROUTE 2 1.513 R10C25C.OFX0 to R9C23D.C0 cpu0/datamux_o_dest[2]
|
CTOF_DEL --- 0.495 R12C25B.C1 to R12C25B.F1 cpu0/regs/SLICE_1189
|
CTOF_DEL --- 0.495 R9C23D.C0 to R9C23D.F0 cpu0/regs/SLICE_895
|
ROUTE 1 1.088 R12C25B.F1 to R14C25C.B1 cpu0/regs/N_251
|
ROUTE 9 2.274 R9C23D.F0 to R10C16D.A0 cpu0/regs/left_1[2]
|
CTOF_DEL --- 0.495 R14C25C.B1 to R14C25C.F1 cpu0/regs/SLICE_955
|
CTOF_DEL --- 0.495 R10C16D.A0 to R10C16D.F0 cpu0/regs/SLICE_1219
|
ROUTE 1 0.626 R14C25C.F1 to R14C25C.D0 cpu0/regs/SS_16[8]
|
ROUTE 1 1.801 R10C16D.F0 to R10C10A.A1 cpu0/regs/N_283
|
CTOF_DEL --- 0.495 R14C25C.D0 to R14C25C.F0 cpu0/regs/SLICE_955
|
CTOF_DEL --- 0.495 R10C10A.A1 to R10C10A.F1 cpu0/regs/SLICE_909
|
ROUTE 1 1.570 R14C25C.F0 to R10C26B.C0 cpu0/regs/SS_231_i1_mux
|
ROUTE 1 0.693 R10C10A.F1 to R10C10A.B0 cpu0/regs/SU_16[2]
|
C0TOFCO_DE --- 1.023 R10C26B.C0 to R10C26B.FCO cpu0/regs/SLICE_67
|
CTOF_DEL --- 0.495 R10C10A.B0 to R10C10A.F0 cpu0/regs/SLICE_909
|
ROUTE 1 0.000 R10C26B.FCO to R10C26C.FCI cpu0/regs/SS_cry[9]
|
ROUTE 1 1.620 R10C10A.F0 to R12C9C.C0 cpu0/regs/SU_201_i1_mux
|
FCITOFCO_D --- 0.162 R10C26C.FCI to R10C26C.FCO cpu0/regs/SLICE_66
|
C0TOFCO_DE --- 1.023 R12C9C.C0 to R12C9C.FCO cpu0/regs/SLICE_61
|
ROUTE 1 0.000 R10C26C.FCO to R10C26D.FCI cpu0/regs/SS_cry[11]
|
ROUTE 1 0.000 R12C9C.FCO to R12C9D.FCI cpu0/regs/SU_cry[3]
|
FCITOFCO_D --- 0.162 R10C26D.FCI to R10C26D.FCO cpu0/regs/SLICE_65
|
FCITOFCO_D --- 0.162 R12C9D.FCI to R12C9D.FCO cpu0/regs/SLICE_60
|
ROUTE 1 0.000 R10C26D.FCO to R10C27A.FCI cpu0/regs/SS_cry[13]
|
ROUTE 1 0.000 R12C9D.FCO to R12C10A.FCI cpu0/regs/SU_cry[5]
|
FCITOF1_DE --- 0.643 R10C27A.FCI to R10C27A.F1 cpu0/regs/SLICE_64
|
FCITOFCO_D --- 0.162 R12C10A.FCI to R12C10A.FCO cpu0/regs/SLICE_59
|
ROUTE 1 0.000 R10C27A.F1 to R10C27A.DI1 cpu0/regs/SS_s[15] (to cpu_clkgen)
|
ROUTE 1 0.000 R12C10A.FCO to R12C10B.FCI cpu0/regs/SU_cry[7]
|
|
FCITOFCO_D --- 0.162 R12C10B.FCI to R12C10B.FCO cpu0/regs/SLICE_58
|
|
ROUTE 1 0.000 R12C10B.FCO to R12C10C.FCI cpu0/regs/SU_cry[9]
|
|
FCITOFCO_D --- 0.162 R12C10C.FCI to R12C10C.FCO cpu0/regs/SLICE_57
|
|
ROUTE 1 0.000 R12C10C.FCO to R12C10D.FCI cpu0/regs/SU_cry[11]
|
|
FCITOF1_DE --- 0.643 R12C10D.FCI to R12C10D.F1 cpu0/regs/SLICE_56
|
|
ROUTE 1 0.000 R12C10D.F1 to R12C10D.DI1 cpu0/regs/SU_s[13] (to clk40_i_c)
|
--------
|
--------
|
24.438 (36.4% logic, 63.6% route), 18 logic levels.
|
32.747 (29.9% logic, 70.1% route), 21 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to SLICE_260:
|
Source Clock Path clk40_i to cpu0/SLICE_1217:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R12C21C.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_56:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R10C27A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R12C10D.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.409ns
|
Error: The following path exceeds requirements by 23.922ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_ind_ea[7] (from clk40_i_c +)
|
Destination: FF Data in cpu0/regs/SU[14] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SS[15] (to clk40_i_c +)
|
|
|
Delay: 24.425ns (36.0% logic, 64.0% route), 19 logic levels.
|
Delay: 32.712ns (27.6% logic, 72.4% route), 18 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
24.425ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
|
32.712ns physical path delay SLICE_284 to cpu0/regs/SLICE_64 exceeds
|
25.000ns delay constraint less
|
8.956ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.409ns
|
0.166ns DIN_SET requirement (totaling 8.790ns) by 23.922ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path SLICE_260 to cpu0/regs/SLICE_55:
|
Data path SLICE_284 to cpu0/regs/SLICE_64:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
REG_DEL --- 0.452 R14C14A.CLK to R14C14A.Q1 SLICE_284 (from clk40_i_c)
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
ROUTE 26 3.767 R14C14A.Q1 to R5C14B.A1 cpu0/k_ind_ea[7]
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
CTOF_DEL --- 0.495 R5C14B.A1 to R5C14B.F1 cpu0/regs/ea/SLICE_877
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
ROUTE 18 1.450 R5C14B.F1 to R5C15D.A1 cpu0/regs/ea/N_62
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
CTOF_DEL --- 0.495 R5C15D.A1 to R5C15D.F1 cpu0/regs/ea/SLICE_668
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
ROUTE 18 1.939 R5C15D.F1 to R6C15B.D1 cpu0/regs/ea/N_107
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
CTOF_DEL --- 0.495 R6C15B.D1 to R6C15B.F1 cpu0/regs/ea/SLICE_876
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
ROUTE 16 2.634 R6C15B.F1 to R8C12C.A1 cpu0/regs/ea/un1_eapostbyte_12
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
CTOF_DEL --- 0.495 R8C12C.A1 to R8C12C.F1 cpu0/regs/ea/SLICE_1211
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
ROUTE 1 1.163 R8C12C.F1 to R8C13D.C0 cpu0/regs/ea/N_77
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
C0TOFCO_DE --- 1.023 R8C13D.C0 to R8C13D.FCO cpu0/regs/ea/SLICE_51
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
ROUTE 1 0.000 R8C13D.FCO to R8C14A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
FCITOFCO_D --- 0.162 R8C14A.FCI to R8C14A.FCO cpu0/regs/ea/SLICE_50
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
ROUTE 1 0.000 R8C14A.FCO to R8C14B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
FCITOFCO_D --- 0.162 R8C14B.FCI to R8C14B.FCO cpu0/regs/ea/SLICE_49
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
ROUTE 1 0.000 R8C14B.FCO to R8C14C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
|
FCITOF0_DE --- 0.585 R19C19B.FCI to R19C19B.F0 cpu0/regs/ea/SLICE_40
|
FCITOF0_DE --- 0.585 R8C14C.FCI to R8C14C.F0 cpu0/regs/ea/SLICE_48
|
ROUTE 4 2.326 R19C19B.F0 to R16C33D.C1 cpu0/regs/regs_o_eamem_addr[9]
|
ROUTE 4 3.207 R8C14C.F0 to R9C22A.A1 cpu0/regs/ea/regs_o_eamem_addr[11]
|
CTOF_DEL --- 0.495 R16C33D.C1 to R16C33D.F1 cpu0/regs/SLICE_1180
|
CTOF_DEL --- 0.495 R9C22A.A1 to R9C22A.F1 cpu0/regs/ea/SLICE_1071
|
ROUTE 1 1.023 R16C33D.F1 to R14C33A.B0 cpu0/regs/N_1413
|
ROUTE 1 1.193 R9C22A.F1 to R9C25A.C0 cpu0/regs/ea/N_1327
|
CTOF_DEL --- 0.495 R14C33A.B0 to R14C33A.F0 cpu0/SLICE_974
|
CTOF_DEL --- 0.495 R9C25A.C0 to R9C25A.F0 cpu0/SLICE_862
|
ROUTE 2 1.971 R14C33A.F0 to R12C25C.D1 cpu0/datamux_o_dest[9]
|
ROUTE 2 2.557 R9C25A.F0 to R9C20D.B1 cpu0/datamux_o_dest[11]
|
CTOF_DEL --- 0.495 R12C25C.D1 to R12C25C.F1 cpu0/regs/SLICE_361
|
CTOF_DEL --- 0.495 R9C20D.B1 to R9C20D.F1 cpu0/regs/SLICE_945
|
ROUTE 6 0.675 R12C25C.F1 to R12C24B.D0 cpu0/regs/left_1[9]
|
ROUTE 6 2.382 R9C20D.F1 to R10C16B.D0 cpu0/regs/left_1[11]
|
CTOF_DEL --- 0.495 R12C24B.D0 to R12C24B.F0 cpu0/regs/SLICE_1190
|
CTOF_DEL --- 0.495 R10C16B.D0 to R10C16B.F0 cpu0/regs/SLICE_1220
|
ROUTE 1 0.986 R12C24B.F0 to R11C24D.A1 cpu0/regs/N_288
|
ROUTE 1 1.450 R10C16B.F0 to R10C12D.B1 cpu0/regs/N_256
|
CTOF_DEL --- 0.495 R11C24D.A1 to R11C24D.F1 cpu0/regs/SLICE_948
|
CTOF_DEL --- 0.495 R10C12D.B1 to R10C12D.F1 cpu0/regs/SLICE_934
|
ROUTE 1 0.436 R11C24D.F1 to R11C24D.C0 cpu0/regs/SU_16[9]
|
ROUTE 1 0.436 R10C12D.F1 to R10C12D.C0 cpu0/regs/SS_16[11]
|
CTOF_DEL --- 0.495 R11C24D.C0 to R11C24D.F0 cpu0/regs/SLICE_948
|
CTOF_DEL --- 0.495 R10C12D.C0 to R10C12D.F0 cpu0/regs/SLICE_934
|
ROUTE 1 1.163 R11C24D.F0 to R11C23B.C1 cpu0/regs/SU_216_i1_mux
|
ROUTE 1 1.506 R10C12D.F0 to R11C12C.C1 cpu0/regs/SS_226_i1_mux
|
C1TOFCO_DE --- 0.889 R11C23B.C1 to R11C23B.FCO cpu0/regs/SLICE_58
|
C1TOFCO_DE --- 0.889 R11C12C.C1 to R11C12C.FCO cpu0/regs/SLICE_66
|
ROUTE 1 0.000 R11C23B.FCO to R11C23C.FCI cpu0/regs/SU_cry[9]
|
ROUTE 1 0.000 R11C12C.FCO to R11C12D.FCI cpu0/regs/SS_cry[11]
|
FCITOFCO_D --- 0.162 R11C23C.FCI to R11C23C.FCO cpu0/regs/SLICE_57
|
FCITOFCO_D --- 0.162 R11C12D.FCI to R11C12D.FCO cpu0/regs/SLICE_65
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
ROUTE 1 0.000 R11C12D.FCO to R11C13A.FCI cpu0/regs/SS_cry[13]
|
FCITOFCO_D --- 0.162 R11C23D.FCI to R11C23D.FCO cpu0/regs/SLICE_56
|
FCITOF1_DE --- 0.643 R11C13A.FCI to R11C13A.F1 cpu0/regs/SLICE_64
|
ROUTE 1 0.000 R11C23D.FCO to R11C24A.FCI cpu0/regs/SU_cry[13]
|
ROUTE 1 0.000 R11C13A.F1 to R11C13A.DI1 cpu0/regs/SS_s[15] (to clk40_i_c)
|
FCITOF0_DE --- 0.585 R11C24A.FCI to R11C24A.F0 cpu0/regs/SLICE_55
|
|
ROUTE 1 0.000 R11C24A.F0 to R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
|
|
--------
|
--------
|
24.425 (36.0% logic, 64.0% route), 19 logic levels.
|
32.712 (27.6% logic, 72.4% route), 18 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to SLICE_260:
|
Source Clock Path clk40_i to SLICE_284:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R14C14A.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R11C24A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R11C13A.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.413ns
|
Error: The following path exceeds requirements by 23.913ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q cpu0/k_ind_ea[0] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_opcode[5] (from clk40_i_c +)
|
Destination: FF Data in cpu0/regs/SU[13] (to cpu_clkgen +)
|
Destination: FF Data in cpu0/regs/SS[14] (to clk40_i_c +)
|
|
|
Delay: 24.421ns (35.7% logic, 64.3% route), 17 logic levels.
|
Delay: 32.703ns (25.7% logic, 74.3% route), 17 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
24.421ns physical path delay SLICE_260 to cpu0/regs/SLICE_56 meets
|
32.703ns physical path delay cpu0/SLICE_1144 to cpu0/regs/SLICE_64 exceeds
|
25.000ns delay constraint less
|
8.956ns delay constraint less
|
0.000ns skew and
|
0.000ns skew and
|
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.413ns
|
0.166ns DIN_SET requirement (totaling 8.790ns) by 23.913ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path SLICE_260 to cpu0/regs/SLICE_56:
|
Data path cpu0/SLICE_1144 to cpu0/regs/SLICE_64:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.452 R18C14A.CLK to R18C14A.Q0 SLICE_260 (from cpu_clkgen)
|
REG_DEL --- 0.452 R12C21A.CLK to R12C21A.Q1 cpu0/SLICE_1144 (from clk40_i_c)
|
ROUTE 22 1.724 R18C14A.Q0 to R18C24D.C1 cpu0/k_ind_ea[0]
|
ROUTE 52 4.508 R12C21A.Q1 to R19C22A.A0 cpu0/k_opcode[5]
|
CTOF_DEL --- 0.495 R18C24D.C1 to R18C24D.F1 cpu0/SLICE_337
|
CTOF_DEL --- 0.495 R19C22A.A0 to R19C22A.F0 cpu0/SLICE_772
|
ROUTE 1 1.959 R18C24D.F1 to R15C12A.D1 cpu0/noofs7_2[0]
|
ROUTE 2 1.308 R19C22A.F0 to R18C24A.A0 cpu0/un1_k_opcode_3_4
|
CTOF_DEL --- 0.495 R15C12A.D1 to R15C12A.F1 cpu0/SLICE_782
|
CTOF_DEL --- 0.495 R18C24A.A0 to R18C24A.F0 cpu0/dec_regs/SLICE_1118
|
ROUTE 13 2.026 R15C12A.F1 to R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
|
ROUTE 1 0.693 R18C24A.F0 to R18C24B.B1 cpu0/dec_regs/path_left_addr79
|
CTOF_DEL --- 0.495 R19C20D.D1 to R19C20D.F1 cpu0/regs/ea/SLICE_1256
|
CTOF_DEL --- 0.495 R18C24B.B1 to R18C24B.F1 cpu0/dec_regs/SLICE_771
|
ROUTE 5 1.337 R19C20D.F1 to R19C18B.A0 cpu0/regs/ea/eamem_addr_o
|
ROUTE 1 0.964 R18C24B.F1 to R17C24A.A1 cpu0/dec_regs/un1_path_left_addr75_1_0
|
C0TOFCO_DE --- 1.023 R19C18B.A0 to R19C18B.FCO cpu0/regs/ea/SLICE_44
|
CTOF_DEL --- 0.495 R17C24A.A1 to R17C24A.F1 cpu0/dec_regs/SLICE_813
|
ROUTE 1 0.000 R19C18B.FCO to R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
|
ROUTE 6 0.675 R17C24A.F1 to R15C24D.D1 cpu0/dec_regs/un1_path_left_addr75_1
|
FCITOFCO_D --- 0.162 R19C18C.FCI to R19C18C.FCO cpu0/regs/ea/SLICE_43
|
CTOF_DEL --- 0.495 R15C24D.D1 to R15C24D.F1 cpu0/dec_regs/SLICE_806
|
ROUTE 1 0.000 R19C18C.FCO to R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
|
ROUTE 8 0.772 R15C24D.F1 to R15C24A.C1 cpu0/dec_regs/path_left_addr_2_sqmuxa
|
FCITOFCO_D --- 0.162 R19C18D.FCI to R19C18D.FCO cpu0/regs/ea/SLICE_42
|
CTOF_DEL --- 0.495 R15C24A.C1 to R15C24A.F1 cpu0/dec_regs/SLICE_802
|
ROUTE 1 0.000 R19C18D.FCO to R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
|
ROUTE 5 1.441 R15C24A.F1 to R17C25D.M0 cpu0/dec_regs/path_left_addr_o_sn_N_2
|
FCITOFCO_D --- 0.162 R19C19A.FCI to R19C19A.FCO cpu0/regs/ea/SLICE_41
|
MTOOFX_DEL --- 0.376 R17C25D.M0 to R17C25D.OFX0 cpu0/dec_regs/SLICE_264
|
ROUTE 1 0.000 R19C19A.FCO to R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
|
ROUTE 5 1.882 R17C25D.OFX0 to R18C22B.A1 cpu0/dec_o_left_path_addr[3]
|
FCITOF1_DE --- 0.643 R19C19B.FCI to R19C19B.F1 cpu0/regs/ea/SLICE_40
|
CTOF_DEL --- 0.495 R18C22B.A1 to R18C22B.F1 cpu0/dec_regs/SLICE_846
|
ROUTE 4 2.307 R19C19B.F1 to R16C30C.C1 cpu0/regs_o_eamem_addr[10]
|
ROUTE 25 3.725 R18C22B.F1 to R9C25A.A0 cpu0/dec_o_alu_size
|
CTOF_DEL --- 0.495 R16C30C.C1 to R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
|
CTOF_DEL --- 0.495 R9C25A.A0 to R9C25A.F0 cpu0/SLICE_862
|
ROUTE 1 1.023 R16C30C.F1 to R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
|
ROUTE 2 2.557 R9C25A.F0 to R9C20D.B1 cpu0/datamux_o_dest[11]
|
CTOF_DEL --- 0.495 R14C30D.B0 to R14C30D.F0 cpu0/alu/alu16/SLICE_1054
|
CTOF_DEL --- 0.495 R9C20D.B1 to R9C20D.F1 cpu0/regs/SLICE_945
|
ROUTE 2 1.640 R14C30D.F0 to R12C24A.A0 cpu0/datamux_o_dest[10]
|
ROUTE 6 2.382 R9C20D.F1 to R10C16B.D0 cpu0/regs/left_1[11]
|
CTOF_DEL --- 0.495 R12C24A.A0 to R12C24A.F0 cpu0/regs/SLICE_362
|
CTOF_DEL --- 0.495 R10C16B.D0 to R10C16B.F0 cpu0/regs/SLICE_1220
|
ROUTE 6 0.780 R12C24A.F0 to R11C24B.C0 cpu0/regs/left_1[10]
|
ROUTE 1 1.450 R10C16B.F0 to R10C12D.B1 cpu0/regs/N_256
|
CTOF_DEL --- 0.495 R11C24B.C0 to R11C24B.F0 cpu0/regs/SLICE_1191
|
CTOF_DEL --- 0.495 R10C12D.B1 to R10C12D.F1 cpu0/regs/SLICE_934
|
ROUTE 1 0.958 R11C24B.F0 to R10C23D.D1 cpu0/regs/N_289
|
ROUTE 1 0.436 R10C12D.F1 to R10C12D.C0 cpu0/regs/SS_16[11]
|
CTOF_DEL --- 0.495 R10C23D.D1 to R10C23D.F1 cpu0/regs/SLICE_949
|
CTOF_DEL --- 0.495 R10C12D.C0 to R10C12D.F0 cpu0/regs/SLICE_934
|
ROUTE 1 0.436 R10C23D.F1 to R10C23D.C0 cpu0/regs/SU_16[10]
|
ROUTE 1 1.506 R10C12D.F0 to R11C12C.C1 cpu0/regs/SS_226_i1_mux
|
CTOF_DEL --- 0.495 R10C23D.C0 to R10C23D.F0 cpu0/regs/SLICE_949
|
C1TOFCO_DE --- 0.889 R11C12C.C1 to R11C12C.FCO cpu0/regs/SLICE_66
|
ROUTE 1 1.506 R10C23D.F0 to R11C23C.C0 cpu0/regs/SU_217_i1_mux
|
ROUTE 1 0.000 R11C12C.FCO to R11C12D.FCI cpu0/regs/SS_cry[11]
|
C0TOFCO_DE --- 1.023 R11C23C.C0 to R11C23C.FCO cpu0/regs/SLICE_57
|
FCITOFCO_D --- 0.162 R11C12D.FCI to R11C12D.FCO cpu0/regs/SLICE_65
|
ROUTE 1 0.000 R11C23C.FCO to R11C23D.FCI cpu0/regs/SU_cry[11]
|
ROUTE 1 0.000 R11C12D.FCO to R11C13A.FCI cpu0/regs/SS_cry[13]
|
FCITOF1_DE --- 0.643 R11C23D.FCI to R11C23D.F1 cpu0/regs/SLICE_56
|
FCITOF0_DE --- 0.585 R11C13A.FCI to R11C13A.F0 cpu0/regs/SLICE_64
|
ROUTE 1 0.000 R11C23D.F1 to R11C23D.DI1 cpu0/regs/SU_s[13] (to cpu_clkgen)
|
ROUTE 1 0.000 R11C13A.F0 to R11C13A.DI0 cpu0/regs/SS_s[14] (to clk40_i_c)
|
--------
|
--------
|
24.421 (35.7% logic, 64.3% route), 17 logic levels.
|
32.703 (25.7% logic, 74.3% route), 17 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to SLICE_260:
|
Source Clock Path clk40_i to cpu0/SLICE_1144:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R18C14A.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R12C21A.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_56:
|
Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 2.399 27.PADDI to R11C23D.CLK cpu_clkgen
|
ROUTE 318 2.399 27.PADDI to R11C13A.CLK clk40_i_c
|
--------
|
--------
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
2.399 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Report: 40.406MHz is the maximum frequency for this preference.
|
Warning: 29.641MHz is the maximum frequency for this preference.
|
|
|
<A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
<A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
--------------
|
--------------
|
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
Preference | Constraint| Actual|Levels
|
Preference | Constraint| Actual|Levels
|
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
| | |
|
| | |
|
FREQUENCY NET "cpu_clkgen" 40.000000 | | |
|
FREQUENCY NET "clk40_i_c" 111.645000 | | |
|
MHz ; | 40.000 MHz| 40.406 MHz| 18
|
MHz ; | 111.645 MHz| 29.641 MHz| 18 *
|
| | |
|
| | |
|
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
|
|
|
|
All preferences were met.
|
1 preference(marked by "*" above) not met.
|
|
|
|
----------------------------------------------------------------------------
|
|
Critical Nets | Loads| Errors| % of total
|
|
----------------------------------------------------------------------------
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/dec_o_alu_size">cpu0/dec_o_alu_size</a> | 25| 3143| 76.73%
|
|
| | |
|
|
cpu0/dec_o_left_path_addr[3] | 5| 2799| 68.33%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/dec_regs/un1_path_left_addr75_1">cpu0/dec_regs/un1_path_left_addr75_1</a> | 6| 2724| 66.50%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/dec_regs/path_left_addr_2_sqmuxa">cpu0/dec_regs/path_left_addr_2_sqmuxa</a> | 8| 2457| 59.99%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/dec_regs/path_left_addr_o_sn_N_2">cpu0/dec_regs/path_left_addr_o_sn_N_2</a> | 5| 2152| 52.54%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/dec_regs/un1_path_left_addr85_1_0">cpu0/dec_regs/un1_path_left_addr85_1_0</a> | 2| 1902| 46.44%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/dec_regs/un1_path_left_addr75_1_4">cpu0/dec_regs/un1_path_left_addr75_1_4</a> | 1| 1706| 41.65%
|
|
| | |
|
|
cpu0/regs/SU_cry[9] | 1| 1283| 31.32%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/dec_regs/un1_path_left_addr85_1_1_2">cpu0/dec_regs/un1_path_left_addr85_1_1_2</a>| 1| 1267| 30.93%
|
|
| | |
|
|
cpu0/regs/SS_cry[11] | 1| 1111| 27.12%
|
|
| | |
|
|
cpu0/regs/SU_cry[5] | 1| 1107| 27.03%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/state133_3">cpu0/state133_3</a> | 13| 1096| 26.76%
|
|
| | |
|
|
cpu0/regs/SU_cry[11] | 1| 1045| 25.51%
|
|
| | |
|
|
cpu0/regs/SU_cry[7] | 1| 1024| 25.00%
|
|
| | |
|
|
cpu0/regs/left_1[11] | 6| 955| 23.32%
|
|
| | |
|
|
cpu0/datamux_o_dest[11] | 2| 955| 23.32%
|
|
| | |
|
|
cpu0/k_opcode[7] | 42| 951| 23.22%
|
|
| | |
|
|
cpu0/regs/SU_cry[3] | 1| 891| 21.75%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/regs/ea/N_107">cpu0/regs/ea/N_107</a> | 18| 882| 21.53%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/regs/ea/un1_eapostbyte_12">cpu0/regs/ea/un1_eapostbyte_12</a> | 16| 864| 21.09%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/regs/N_256">cpu0/regs/N_256</a> | 1| 852| 20.80%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/regs/SS_226_i1_mux">cpu0/regs/SS_226_i1_mux</a> | 1| 852| 20.80%
|
|
| | |
|
|
cpu0/regs/SS_16[11] | 1| 852| 20.80%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/regs/ea/eamem_addr_o_cry_8">cpu0/regs/ea/eamem_addr_o_cry_8</a> | 1| 770| 18.80%
|
|
| | |
|
|
cpu0/regs/SU_cry[13] | 1| 672| 16.41%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/dec_regs/un1_path_left_addr75_1_0">cpu0/dec_regs/un1_path_left_addr75_1_0</a> | 1| 636| 15.53%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/alu/k_cpu_addr_1_sqmuxa_1">cpu0/alu/k_cpu_addr_1_sqmuxa_1</a> | 1| 619| 15.11%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/un1_cpu_reset_9">cpu0/un1_cpu_reset_9</a> | 4| 619| 15.11%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/regs/ea/eamem_addr_o_cry_6">cpu0/regs/ea/eamem_addr_o_cry_6</a> | 1| 616| 15.04%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/un1_state_116">cpu0/un1_state_116</a> | 16| 615| 15.01%
|
|
| | |
|
|
cpu0/regs/SS_cry[13] | 1| 612| 14.94%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/dec_regs/un1_path_left_addr85_1_1_1">cpu0/dec_regs/un1_path_left_addr85_1_1_1</a>| 1| 588| 14.36%
|
|
| | |
|
|
cpu0/regs/left_1[2] | 9| 585| 14.28%
|
|
| | |
|
|
cpu0/datamux_o_dest[2] | 2| 585| 14.28%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/dec_regs/path_left_addr79">cpu0/dec_regs/path_left_addr79</a> | 1| 583| 14.23%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/regs/ea/N_62">cpu0/regs/ea/N_62</a> | 18| 576| 14.06%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/regs/N_283">cpu0/regs/N_283</a> | 1| 545| 13.31%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/regs/SU_201_i1_mux">cpu0/regs/SU_201_i1_mux</a> | 1| 545| 13.31%
|
|
| | |
|
|
cpu0/regs/SU_16[2] | 1| 545| 13.31%
|
|
| | |
|
|
cpu0/k_opcode[1] | 61| 537| 13.11%
|
|
| | |
|
|
cpu0/datamux_o_dest[9] | 2| 525| 12.82%
|
|
| | |
|
|
cpu0/regs/left_1[9] | 6| 525| 12.82%
|
|
| | |
|
|
cpu0/regs/left_1[3] | 9| 502| 12.26%
|
|
| | |
|
|
cpu0/datamux_o_dest[3] | 2| 502| 12.26%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/un1_k_opcode_3_4">cpu0/un1_k_opcode_3_4</a> | 2| 499| 12.18%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/un1_k_cpu_addr_1_cry_8">cpu0/un1_k_cpu_addr_1_cry_8</a> | 1| 472| 11.52%
|
|
| | |
|
|
cpu0/k_opcode[5] | 52| 469| 11.45%
|
|
| | |
|
|
cpu0/regs/SS_cry[5] | 1| 463| 11.30%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/un1_k_cpu_addr_1_cry_10">cpu0/un1_k_cpu_addr_1_cry_10</a> | 1| 459| 11.21%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/regs/ea/eamem_addr_o_cry_10">cpu0/regs/ea/eamem_addr_o_cry_10</a> | 1| 450| 10.99%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/regs/N_290">cpu0/regs/N_290</a> | 1| 445| 10.86%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/regs/SU_208_i1_mux">cpu0/regs/SU_208_i1_mux</a> | 1| 445| 10.86%
|
|
| | |
|
|
cpu0/regs/SU_16[9] | 1| 445| 10.86%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/un1_k_cpu_addr_1_cry_6">cpu0/un1_k_cpu_addr_1_cry_6</a> | 1| 444| 10.84%
|
|
| | |
|
|
cpu0/regs/SS_cry[9] | 1| 437| 10.67%
|
|
| | |
|
|
cpu0/regs/SS_cry[7] | 1| 424| 10.35%
|
|
| | |
|
|
<a href="bali://?app=PHYSICAL_VIEW&sig=LocateNet&args=cpu0/alu/mulu/N_1325">cpu0/alu/mulu/N_1325</a> | 1| 419| 10.23%
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
<A name="ptwr_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
<A name="ptwr_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
------------------------
|
------------------------
|
|
|
Found 1 clocks:
|
Found 1 clocks:
|
|
|
Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 367
|
Clock Domain: clk40_i_c Source: clk40_i.PAD Loads: 318
|
Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
Covered under: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
|
|
|
|
|
<A name="ptwr_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
|
<A name="ptwr_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
|
---------------
|
---------------
|
|
|
Timing errors: 0 Score: 0
|
Timing errors: 4096 Score: 88089612
|
Cumulative negative slack: 0
|
Cumulative negative slack: 88089612
|
|
|
Constraints cover 1107881 paths, 1 nets, and 9532 connections (99.1% coverage)
|
Constraints cover 1430483 paths, 1 nets, and 9633 connections (99.1% coverage)
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101</big></U></B>
|
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.1.0.96</big></U></B>
|
Thu Feb 6 15:36:12 2014
|
Sun Jul 06 07:47:16 2014
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
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Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
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<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
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<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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------------------
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr -gui P6809_P6809.ncd P6809_P6809.prf
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Design file: P6809_P6809.ncd
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Design file: p6809_p6809.ncd
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Preference file: P6809_P6809.prf
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Preference file: p6809_p6809.prf
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Device,speed: LCMXO2-7000HE,m
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Device,speed: LCMXO2-7000HE,m
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Report level: verbose report, limited to 10 items per preference
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Report level: verbose report, limited to 10 items per preference
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--------------------------------------------------------------------------------
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<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
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<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
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<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (0 errors)</A></LI> 4096 items scored, 0 timing errors detected.
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<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY NET "clk40_i_c" 111.645000 MHz (0 errors)</A></LI> 4096 items scored, 0 timing errors detected.
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BLOCK ASYNCPATHS
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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================================================================================
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================================================================================
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<A name="par_twr_pref_1_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
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<A name="par_twr_pref_1_0"></A>Preference: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
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4096 items scored, 0 timing errors detected.
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4096 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.217ns
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Passed: The following path meets requirements by 0.199ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q textctrl/chars_data[6] (from cpu_clkgen +)
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Source: FF Q textctrl/chars_data[1] (from clk40_i_c +)
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Destination: DP8KC Port textctrl/font/fontrom_0_0_3(ASIC) (to cpu_clkgen +)
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Destination: DP8KC Port textctrl/font/fontrom_0_0_3(ASIC) (to clk40_i_c +)
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Delay: 0.322ns (40.7% logic, 59.3% route), 1 logic levels.
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Delay: 0.304ns (43.1% logic, 56.9% route), 1 logic levels.
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Constraint Details:
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Constraint Details:
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0.322ns physical path delay SLICE_454 to textctrl/font/fontrom_0_0_3 meets
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0.304ns physical path delay SLICE_412 to textctrl/font/fontrom_0_0_3 meets
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0.052ns ADDR_HLD and
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0.052ns ADDR_HLD and
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0.000ns delay constraint less
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0.000ns delay constraint less
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-0.053ns skew requirement (totaling 0.105ns) by 0.217ns
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-0.053ns skew requirement (totaling 0.105ns) by 0.199ns
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Physical Path Details:
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Physical Path Details:
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Data path SLICE_454 to textctrl/font/fontrom_0_0_3:
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Data path SLICE_412 to textctrl/font/fontrom_0_0_3:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.131 R14C17C.CLK to R14C17C.Q0 SLICE_454 (from cpu_clkgen)
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REG_DEL --- 0.131 R18C28D.CLK to R18C28D.Q1 SLICE_412 (from clk40_i_c)
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ROUTE 4 0.191 R14C17C.Q0 to *_R13C16.ADA11 textctrl/chars_data[6] (to cpu_clkgen)
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ROUTE 4 0.173 R18C28D.Q1 to *R_R20C27.ADA6 textctrl/chars_data[1] (to clk40_i_c)
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--------
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--------
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0.322 (40.7% logic, 59.3% route), 1 logic levels.
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0.304 (43.1% logic, 56.9% route), 1 logic levels.
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Clock Skew Details:
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Clock Skew Details:
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Source Clock Path clk40_i to SLICE_454:
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Source Clock Path clk40_i to SLICE_412:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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ROUTE 367 0.846 27.PADDI to R14C17C.CLK cpu_clkgen
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ROUTE 318 0.846 27.PADDI to R18C28D.CLK clk40_i_c
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--------
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--------
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0.846 (0.0% logic, 100.0% route), 0 logic levels.
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0.846 (0.0% logic, 100.0% route), 0 logic levels.
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Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
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Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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ROUTE 367 0.899 27.PADDI to *R_R13C16.CLKA cpu_clkgen
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ROUTE 318 0.899 27.PADDI to *R_R20C27.CLKA clk40_i_c
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--------
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--------
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0.899 (0.0% logic, 100.0% route), 0 logic levels.
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0.899 (0.0% logic, 100.0% route), 0 logic levels.
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Passed: The following path meets requirements by 0.234ns
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Passed: The following path meets requirements by 0.216ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q textctrl/chars_data[7] (from cpu_clkgen +)
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Source: FF Q textctrl/line_cnt[3] (from clk40_i_c +)
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Destination: DP8KC Port textctrl/font/fontrom_0_0_3(ASIC) (to cpu_clkgen +)
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Destination: DP8KC Port textctrl/font/fontrom_0_3_0(ASIC) (to clk40_i_c +)
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Delay: 0.339ns (38.6% logic, 61.4% route), 1 logic levels.
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Delay: 0.339ns (38.6% logic, 61.4% route), 1 logic levels.
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Constraint Details:
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Constraint Details:
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0.339ns physical path delay SLICE_454 to textctrl/font/fontrom_0_0_3 meets
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0.339ns physical path delay textctrl/SLICE_421 to textctrl/font/fontrom_0_3_0 meets
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0.052ns ADDR_HLD and
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0.052ns ADDR_HLD and
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0.000ns delay constraint less
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0.000ns delay constraint less
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-0.053ns skew requirement (totaling 0.105ns) by 0.234ns
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-0.071ns skew requirement (totaling 0.123ns) by 0.216ns
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Physical Path Details:
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Physical Path Details:
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Data path SLICE_454 to textctrl/font/fontrom_0_0_3:
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Data path textctrl/SLICE_421 to textctrl/font/fontrom_0_3_0:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.131 R14C17C.CLK to R14C17C.Q1 SLICE_454 (from cpu_clkgen)
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REG_DEL --- 0.131 R22C26B.CLK to R22C26B.Q1 textctrl/SLICE_421 (from clk40_i_c)
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ROUTE 4 0.208 R14C17C.Q1 to *_R13C16.ADA12 textctrl/chars_data[7] (to cpu_clkgen)
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ROUTE 7 0.208 R22C26B.Q1 to *R_R20C24.ADA4 textctrl/line_cnt[3] (to clk40_i_c)
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--------
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--------
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0.339 (38.6% logic, 61.4% route), 1 logic levels.
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0.339 (38.6% logic, 61.4% route), 1 logic levels.
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Clock Skew Details:
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Clock Skew Details:
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Source Clock Path clk40_i to SLICE_454:
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Source Clock Path clk40_i to textctrl/SLICE_421:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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ROUTE 367 0.846 27.PADDI to R14C17C.CLK cpu_clkgen
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ROUTE 318 0.828 27.PADDI to R22C26B.CLK clk40_i_c
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--------
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--------
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0.846 (0.0% logic, 100.0% route), 0 logic levels.
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0.828 (0.0% logic, 100.0% route), 0 logic levels.
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Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
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Destination Clock Path clk40_i to textctrl/font/fontrom_0_3_0:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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ROUTE 367 0.899 27.PADDI to *R_R13C16.CLKA cpu_clkgen
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ROUTE 318 0.899 27.PADDI to *R_R20C24.CLKA clk40_i_c
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--------
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--------
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0.899 (0.0% logic, 100.0% route), 0 logic levels.
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0.899 (0.0% logic, 100.0% route), 0 logic levels.
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Passed: The following path meets requirements by 0.344ns
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Passed: The following path meets requirements by 0.277ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q reset_cnt[0] (from cpu_clkgen +)
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Source: FF Q textctrl/chars_data[0] (from clk40_i_c +)
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Destination: FF Data in reset_cnt[0] (to cpu_clkgen +)
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Destination: DP8KC Port textctrl/font/fontrom_0_0_3(ASIC) (to clk40_i_c +)
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Delay: 0.288ns (45.5% logic, 54.5% route), 1 logic levels.
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Delay: 0.382ns (34.3% logic, 65.7% route), 1 logic levels.
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Constraint Details:
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Constraint Details:
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0.288ns physical path delay SLICE_444 to SLICE_444 meets
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0.382ns physical path delay SLICE_412 to textctrl/font/fontrom_0_0_3 meets
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-0.056ns LSR_HLD and
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0.052ns ADDR_HLD and
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0.000ns delay constraint less
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0.000ns delay constraint less
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0.000ns skew requirement (totaling -0.056ns) by 0.344ns
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-0.053ns skew requirement (totaling 0.105ns) by 0.277ns
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Physical Path Details:
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Physical Path Details:
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Data path SLICE_444 to SLICE_444:
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Data path SLICE_412 to textctrl/font/fontrom_0_0_3:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.131 R19C8D.CLK to R19C8D.Q0 SLICE_444 (from cpu_clkgen)
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REG_DEL --- 0.131 R18C28D.CLK to R18C28D.Q0 SLICE_412 (from clk40_i_c)
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ROUTE 5 0.157 R19C8D.Q0 to R19C8D.LSR reset_cnt[0] (to cpu_clkgen)
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ROUTE 4 0.251 R18C28D.Q0 to *R_R20C27.ADA5 textctrl/chars_data[0] (to clk40_i_c)
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--------
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--------
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0.288 (45.5% logic, 54.5% route), 1 logic levels.
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0.382 (34.3% logic, 65.7% route), 1 logic levels.
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Clock Skew Details:
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Clock Skew Details:
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Source Clock Path clk40_i to SLICE_444:
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Source Clock Path clk40_i to SLICE_412:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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ROUTE 367 0.846 27.PADDI to R19C8D.CLK cpu_clkgen
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ROUTE 318 0.846 27.PADDI to R18C28D.CLK clk40_i_c
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--------
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--------
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0.846 (0.0% logic, 100.0% route), 0 logic levels.
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0.846 (0.0% logic, 100.0% route), 0 logic levels.
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Destination Clock Path clk40_i to SLICE_444:
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Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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ROUTE 367 0.846 27.PADDI to R19C8D.CLK cpu_clkgen
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ROUTE 318 0.899 27.PADDI to *R_R20C27.CLKA clk40_i_c
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--------
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--------
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0.846 (0.0% logic, 100.0% route), 0 logic levels.
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0.899 (0.0% logic, 100.0% route), 0 logic levels.
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Passed: The following path meets requirements by 0.370ns
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Passed: The following path meets requirements by 0.294ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q textctrl/blink_cnt[0] (from cpu_clkgen +)
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Source: FF Q cpu0/k_cpu_addr[0] (from clk40_i_c +)
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Destination: FF Data in textctrl/blink_cnt[0] (to cpu_clkgen +)
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Destination: DP8KC Port textctrl/chars/textmem4k_0_2_1(ASIC) (to clk40_i_c +)
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Delay: 0.357ns (64.4% logic, 35.6% route), 2 logic levels.
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Delay: 0.418ns (31.3% logic, 68.7% route), 1 logic levels.
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Constraint Details:
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Constraint Details:
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0.357ns physical path delay textctrl/SLICE_29 to textctrl/SLICE_29 meets
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0.418ns physical path delay cpu0/SLICE_183 to textctrl/chars/textmem4k_0_2_1 meets
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-0.013ns DIN_HLD and
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0.071ns ADDR_HLD and
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0.000ns delay constraint less
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0.000ns delay constraint less
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0.000ns skew requirement (totaling -0.013ns) by 0.370ns
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-0.053ns skew requirement (totaling 0.124ns) by 0.294ns
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Physical Path Details:
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Physical Path Details:
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Data path textctrl/SLICE_29 to textctrl/SLICE_29:
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Data path cpu0/SLICE_183 to textctrl/chars/textmem4k_0_2_1:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.131 R25C10A.CLK to R25C10A.Q1 textctrl/SLICE_29 (from cpu_clkgen)
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REG_DEL --- 0.131 R16C14C.CLK to R16C14C.Q0 cpu0/SLICE_183 (from clk40_i_c)
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ROUTE 1 0.127 R25C10A.Q1 to R25C10A.A1 textctrl/blink_cnt[0]
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ROUTE 11 0.287 R16C14C.Q0 to *R_R13C13.ADB1 addr_o_c[0] (to clk40_i_c)
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CTOF_DEL --- 0.099 R25C10A.A1 to R25C10A.F1 textctrl/SLICE_29
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ROUTE 1 0.000 R25C10A.F1 to R25C10A.DI1 textctrl/blink_cnt_s[0] (to cpu_clkgen)
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--------
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--------
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0.357 (64.4% logic, 35.6% route), 2 logic levels.
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0.418 (31.3% logic, 68.7% route), 1 logic levels.
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Clock Skew Details:
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Clock Skew Details:
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Source Clock Path clk40_i to textctrl/SLICE_29:
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Source Clock Path clk40_i to cpu0/SLICE_183:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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ROUTE 367 0.828 27.PADDI to R25C10A.CLK cpu_clkgen
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ROUTE 318 0.846 27.PADDI to R16C14C.CLK clk40_i_c
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--------
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--------
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0.828 (0.0% logic, 100.0% route), 0 logic levels.
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0.846 (0.0% logic, 100.0% route), 0 logic levels.
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Destination Clock Path clk40_i to textctrl/SLICE_29:
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Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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ROUTE 367 0.828 27.PADDI to R25C10A.CLK cpu_clkgen
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ROUTE 318 0.899 27.PADDI to *R_R13C13.CLKB clk40_i_c
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--------
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--------
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0.828 (0.0% logic, 100.0% route), 0 logic levels.
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0.899 (0.0% logic, 100.0% route), 0 logic levels.
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Passed: The following path meets requirements by 0.370ns
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Passed: The following path meets requirements by 0.302ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q textctrl/blink_cnt[4] (from cpu_clkgen +)
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Source: FF Q textctrl/chars_data[7] (from clk40_i_c +)
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Destination: FF Data in textctrl/blink_cnt[4] (to cpu_clkgen +)
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Destination: DP8KC Port textctrl/font/fontrom_0_0_3(ASIC) (to clk40_i_c +)
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Delay: 0.357ns (64.4% logic, 35.6% route), 2 logic levels.
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Delay: 0.407ns (32.2% logic, 67.8% route), 1 logic levels.
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Constraint Details:
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Constraint Details:
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0.357ns physical path delay textctrl/SLICE_27 to textctrl/SLICE_27 meets
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0.407ns physical path delay SLICE_415 to textctrl/font/fontrom_0_0_3 meets
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-0.013ns DIN_HLD and
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0.052ns ADDR_HLD and
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0.000ns delay constraint less
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0.000ns delay constraint less
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0.000ns skew requirement (totaling -0.013ns) by 0.370ns
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-0.053ns skew requirement (totaling 0.105ns) by 0.302ns
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Physical Path Details:
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Physical Path Details:
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Data path textctrl/SLICE_27 to textctrl/SLICE_27:
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Data path SLICE_415 to textctrl/font/fontrom_0_0_3:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.131 R25C10C.CLK to R25C10C.Q1 textctrl/SLICE_27 (from cpu_clkgen)
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REG_DEL --- 0.131 R16C28A.CLK to R16C28A.Q1 SLICE_415 (from clk40_i_c)
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ROUTE 1 0.127 R25C10C.Q1 to R25C10C.A1 textctrl/blink_cnt[4]
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ROUTE 4 0.276 R16C28A.Q1 to *_R20C27.ADA12 textctrl/chars_data[7] (to clk40_i_c)
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CTOF_DEL --- 0.099 R25C10C.A1 to R25C10C.F1 textctrl/SLICE_27
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ROUTE 1 0.000 R25C10C.F1 to R25C10C.DI1 textctrl/blink_cnt_s[4] (to cpu_clkgen)
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--------
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--------
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0.357 (64.4% logic, 35.6% route), 2 logic levels.
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0.407 (32.2% logic, 67.8% route), 1 logic levels.
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|
|
Clock Skew Details:
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Clock Skew Details:
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|
Source Clock Path clk40_i to textctrl/SLICE_27:
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Source Clock Path clk40_i to SLICE_415:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
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ROUTE 367 0.828 27.PADDI to R25C10C.CLK cpu_clkgen
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ROUTE 318 0.846 27.PADDI to R16C28A.CLK clk40_i_c
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--------
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--------
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0.828 (0.0% logic, 100.0% route), 0 logic levels.
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0.846 (0.0% logic, 100.0% route), 0 logic levels.
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|
|
Destination Clock Path clk40_i to textctrl/SLICE_27:
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Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
|
ROUTE 367 0.828 27.PADDI to R25C10C.CLK cpu_clkgen
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ROUTE 318 0.899 27.PADDI to *R_R20C27.CLKA clk40_i_c
|
--------
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--------
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0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.370ns
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Passed: The following path meets requirements by 0.314ns
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|
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q textctrl/blink_cnt[3] (from cpu_clkgen +)
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Source: FF Q cpu0/k_cpu_addr[6] (from clk40_i_c +)
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Destination: FF Data in textctrl/blink_cnt[3] (to cpu_clkgen +)
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Destination: DP8KC Port bios/bios2k_0_1_0(ASIC) (to clk40_i_c +)
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|
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Delay: 0.357ns (64.4% logic, 35.6% route), 2 logic levels.
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Delay: 0.419ns (31.3% logic, 68.7% route), 1 logic levels.
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|
|
Constraint Details:
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Constraint Details:
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|
0.357ns physical path delay textctrl/SLICE_27 to textctrl/SLICE_27 meets
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0.419ns physical path delay cpu0/SLICE_186 to bios/bios2k_0_1_0 meets
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-0.013ns DIN_HLD and
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0.052ns ADDR_HLD and
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0.000ns delay constraint less
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0.000ns delay constraint less
|
0.000ns skew requirement (totaling -0.013ns) by 0.370ns
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-0.053ns skew requirement (totaling 0.105ns) by 0.314ns
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|
|
Physical Path Details:
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Physical Path Details:
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|
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Data path textctrl/SLICE_27 to textctrl/SLICE_27:
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Data path cpu0/SLICE_186 to bios/bios2k_0_1_0:
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Name Fanout Delay (ns) Site Resource
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Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R25C10C.CLK to R25C10C.Q0 textctrl/SLICE_27 (from cpu_clkgen)
|
REG_DEL --- 0.131 R15C12A.CLK to R15C12A.Q0 cpu0/SLICE_186 (from clk40_i_c)
|
ROUTE 1 0.127 R25C10C.Q0 to R25C10C.A0 textctrl/blink_cnt[3]
|
ROUTE 8 0.288 R15C12A.Q0 to *R_R13C10.ADA8 addr_o_c[6] (to clk40_i_c)
|
CTOF_DEL --- 0.099 R25C10C.A0 to R25C10C.F0 textctrl/SLICE_27
|
|
ROUTE 1 0.000 R25C10C.F0 to R25C10C.DI0 textctrl/blink_cnt_s[3] (to cpu_clkgen)
|
|
--------
|
--------
|
0.357 (64.4% logic, 35.6% route), 2 logic levels.
|
0.419 (31.3% logic, 68.7% route), 1 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to textctrl/SLICE_27:
|
Source Clock Path clk40_i to cpu0/SLICE_186:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 0.828 27.PADDI to R25C10C.CLK cpu_clkgen
|
ROUTE 318 0.846 27.PADDI to R15C12A.CLK clk40_i_c
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/SLICE_27:
|
Destination Clock Path clk40_i to bios/bios2k_0_1_0:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 0.828 27.PADDI to R25C10C.CLK cpu_clkgen
|
ROUTE 318 0.899 27.PADDI to *R_R13C10.CLKA clk40_i_c
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.370ns
|
Passed: The following path meets requirements by 0.322ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q textctrl/blink_cnt[1] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_cpu_addr[5] (from clk40_i_c +)
|
Destination: FF Data in textctrl/blink_cnt[1] (to cpu_clkgen +)
|
Destination: DP8KC Port textctrl/chars/textmem4k_0_2_1(ASIC) (to clk40_i_c +)
|
|
|
Delay: 0.357ns (64.4% logic, 35.6% route), 2 logic levels.
|
Delay: 0.446ns (29.4% logic, 70.6% route), 1 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
|
0.446ns physical path delay cpu0/SLICE_185 to textctrl/chars/textmem4k_0_2_1 meets
|
-0.013ns DIN_HLD and
|
0.071ns ADDR_HLD and
|
0.000ns delay constraint less
|
0.000ns delay constraint less
|
0.000ns skew requirement (totaling -0.013ns) by 0.370ns
|
-0.053ns skew requirement (totaling 0.124ns) by 0.322ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path textctrl/SLICE_28 to textctrl/SLICE_28:
|
Data path cpu0/SLICE_185 to textctrl/chars/textmem4k_0_2_1:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R25C10B.CLK to R25C10B.Q0 textctrl/SLICE_28 (from cpu_clkgen)
|
REG_DEL --- 0.131 R16C13D.CLK to R16C13D.Q1 cpu0/SLICE_185 (from clk40_i_c)
|
ROUTE 1 0.127 R25C10B.Q0 to R25C10B.A0 textctrl/blink_cnt[1]
|
ROUTE 9 0.315 R16C13D.Q1 to *R_R13C13.ADB6 addr_o_c[5] (to clk40_i_c)
|
CTOF_DEL --- 0.099 R25C10B.A0 to R25C10B.F0 textctrl/SLICE_28
|
|
ROUTE 1 0.000 R25C10B.F0 to R25C10B.DI0 textctrl/blink_cnt_s[1] (to cpu_clkgen)
|
|
--------
|
--------
|
0.357 (64.4% logic, 35.6% route), 2 logic levels.
|
0.446 (29.4% logic, 70.6% route), 1 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to textctrl/SLICE_28:
|
Source Clock Path clk40_i to cpu0/SLICE_185:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 0.828 27.PADDI to R25C10B.CLK cpu_clkgen
|
ROUTE 318 0.846 27.PADDI to R16C13D.CLK clk40_i_c
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/SLICE_28:
|
Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 0.828 27.PADDI to R25C10B.CLK cpu_clkgen
|
ROUTE 318 0.899 27.PADDI to *R_R13C13.CLKB clk40_i_c
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.370ns
|
Passed: The following path meets requirements by 0.326ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q textctrl/blink_cnt[2] (from cpu_clkgen +)
|
Source: FF Q textctrl/line_cnt[1] (from clk40_i_c +)
|
Destination: FF Data in textctrl/blink_cnt[2] (to cpu_clkgen +)
|
Destination: DP8KC Port textctrl/font/fontrom_0_0_3(ASIC) (to clk40_i_c +)
|
|
|
Delay: 0.357ns (64.4% logic, 35.6% route), 2 logic levels.
|
Delay: 0.449ns (29.2% logic, 70.8% route), 1 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
|
0.449ns physical path delay textctrl/SLICE_420 to textctrl/font/fontrom_0_0_3 meets
|
-0.013ns DIN_HLD and
|
0.052ns ADDR_HLD and
|
0.000ns delay constraint less
|
0.000ns delay constraint less
|
0.000ns skew requirement (totaling -0.013ns) by 0.370ns
|
-0.071ns skew requirement (totaling 0.123ns) by 0.326ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path textctrl/SLICE_28 to textctrl/SLICE_28:
|
Data path textctrl/SLICE_420 to textctrl/font/fontrom_0_0_3:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R25C10B.CLK to R25C10B.Q1 textctrl/SLICE_28 (from cpu_clkgen)
|
REG_DEL --- 0.131 R22C27D.CLK to R22C27D.Q1 textctrl/SLICE_420 (from clk40_i_c)
|
ROUTE 1 0.127 R25C10B.Q1 to R25C10B.A1 textctrl/blink_cnt[2]
|
ROUTE 9 0.318 R22C27D.Q1 to *R_R20C27.ADA2 textctrl/line_cnt[1] (to clk40_i_c)
|
CTOF_DEL --- 0.099 R25C10B.A1 to R25C10B.F1 textctrl/SLICE_28
|
|
ROUTE 1 0.000 R25C10B.F1 to R25C10B.DI1 textctrl/blink_cnt_s[2] (to cpu_clkgen)
|
|
--------
|
--------
|
0.357 (64.4% logic, 35.6% route), 2 logic levels.
|
0.449 (29.2% logic, 70.8% route), 1 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to textctrl/SLICE_28:
|
Source Clock Path clk40_i to textctrl/SLICE_420:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 0.828 27.PADDI to R25C10B.CLK cpu_clkgen
|
ROUTE 318 0.828 27.PADDI to R22C27D.CLK clk40_i_c
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/SLICE_28:
|
Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 0.828 27.PADDI to R25C10B.CLK cpu_clkgen
|
ROUTE 318 0.899 27.PADDI to *R_R20C27.CLKA clk40_i_c
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.371ns
|
Passed: The following path meets requirements by 0.326ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q textctrl/chars_data[3] (from cpu_clkgen +)
|
Source: FF Q cpu0/k_cpu_addr[9] (from clk40_i_c +)
|
Destination: DP8KC Port textctrl/font/fontrom_0_3_0(ASIC) (to cpu_clkgen +)
|
Destination: DP8KC Port textctrl/chars/textmem4k_0_2_1(ASIC) (to clk40_i_c +)
|
|
|
Delay: 0.476ns (27.5% logic, 72.5% route), 1 logic levels.
|
Delay: 0.450ns (29.1% logic, 70.9% route), 1 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
0.476ns physical path delay textctrl/SLICE_1231 to textctrl/font/fontrom_0_3_0 meets
|
0.450ns physical path delay cpu0/SLICE_187 to textctrl/chars/textmem4k_0_2_1 meets
|
0.052ns ADDR_HLD and
|
0.071ns ADDR_HLD and
|
0.000ns delay constraint less
|
0.000ns delay constraint less
|
-0.053ns skew requirement (totaling 0.105ns) by 0.371ns
|
-0.053ns skew requirement (totaling 0.124ns) by 0.326ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path textctrl/SLICE_1231 to textctrl/font/fontrom_0_3_0:
|
Data path cpu0/SLICE_187 to textctrl/chars/textmem4k_0_2_1:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R19C14D.CLK to R19C14D.Q1 textctrl/SLICE_1231 (from cpu_clkgen)
|
REG_DEL --- 0.131 R15C12B.CLK to R15C12B.Q1 cpu0/SLICE_187 (from clk40_i_c)
|
ROUTE 4 0.345 R19C14D.Q1 to *R_R20C16.ADA8 textctrl/chars_data[3] (to cpu_clkgen)
|
ROUTE 8 0.319 R15C12B.Q1 to *_R13C13.ADB10 addr_o_c[9] (to clk40_i_c)
|
--------
|
--------
|
0.476 (27.5% logic, 72.5% route), 1 logic levels.
|
0.450 (29.1% logic, 70.9% route), 1 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to textctrl/SLICE_1231:
|
Source Clock Path clk40_i to cpu0/SLICE_187:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 0.846 27.PADDI to R19C14D.CLK cpu_clkgen
|
ROUTE 318 0.846 27.PADDI to R15C12B.CLK clk40_i_c
|
--------
|
--------
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
0.846 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/font/fontrom_0_3_0:
|
Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 0.899 27.PADDI to *R_R20C16.CLKA cpu_clkgen
|
ROUTE 318 0.899 27.PADDI to *R_R13C13.CLKB clk40_i_c
|
--------
|
--------
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
Passed: The following path meets requirements by 0.372ns
|
Passed: The following path meets requirements by 0.328ns
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
Source: FF Q textctrl/x_cnt[3] (from cpu_clkgen +)
|
Source: FF Q textctrl/line_cnt[1] (from clk40_i_c +)
|
Destination: FF Data in textctrl/x_cnt[3] (to cpu_clkgen +)
|
Destination: DP8KC Port textctrl/font/fontrom_0_3_0(ASIC) (to clk40_i_c +)
|
|
|
Delay: 0.359ns (64.1% logic, 35.9% route), 2 logic levels.
|
Delay: 0.451ns (29.0% logic, 71.0% route), 1 logic levels.
|
|
|
Constraint Details:
|
Constraint Details:
|
|
|
0.359ns physical path delay textctrl/SLICE_13 to textctrl/SLICE_13 meets
|
0.451ns physical path delay textctrl/SLICE_420 to textctrl/font/fontrom_0_3_0 meets
|
-0.013ns DIN_HLD and
|
0.052ns ADDR_HLD and
|
0.000ns delay constraint less
|
0.000ns delay constraint less
|
0.000ns skew requirement (totaling -0.013ns) by 0.372ns
|
-0.071ns skew requirement (totaling 0.123ns) by 0.328ns
|
|
|
Physical Path Details:
|
Physical Path Details:
|
|
|
Data path textctrl/SLICE_13 to textctrl/SLICE_13:
|
Data path textctrl/SLICE_420 to textctrl/font/fontrom_0_3_0:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
REG_DEL --- 0.131 R22C10C.CLK to R22C10C.Q0 textctrl/SLICE_13 (from cpu_clkgen)
|
REG_DEL --- 0.131 R22C27D.CLK to R22C27D.Q1 textctrl/SLICE_420 (from clk40_i_c)
|
ROUTE 3 0.129 R22C10C.Q0 to R22C10C.A0 textctrl/x_cnt[3]
|
ROUTE 9 0.320 R22C27D.Q1 to *R_R20C24.ADA2 textctrl/line_cnt[1] (to clk40_i_c)
|
CTOF_DEL --- 0.099 R22C10C.A0 to R22C10C.F0 textctrl/SLICE_13
|
|
ROUTE 1 0.000 R22C10C.F0 to R22C10C.DI0 textctrl/x_cnt_s[3] (to cpu_clkgen)
|
|
--------
|
--------
|
0.359 (64.1% logic, 35.9% route), 2 logic levels.
|
0.451 (29.0% logic, 71.0% route), 1 logic levels.
|
|
|
Clock Skew Details:
|
Clock Skew Details:
|
|
|
Source Clock Path clk40_i to textctrl/SLICE_13:
|
Source Clock Path clk40_i to textctrl/SLICE_420:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 0.828 27.PADDI to R22C10C.CLK cpu_clkgen
|
ROUTE 318 0.828 27.PADDI to R22C27D.CLK clk40_i_c
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
Destination Clock Path clk40_i to textctrl/SLICE_13:
|
Destination Clock Path clk40_i to textctrl/font/fontrom_0_3_0:
|
|
|
Name Fanout Delay (ns) Site Resource
|
Name Fanout Delay (ns) Site Resource
|
ROUTE 367 0.828 27.PADDI to R22C10C.CLK cpu_clkgen
|
ROUTE 318 0.899 27.PADDI to *R_R20C24.CLKA clk40_i_c
|
--------
|
--------
|
0.828 (0.0% logic, 100.0% route), 0 logic levels.
|
0.899 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
<A name="ptwr_hold_rs"></A><B><U><big>Report Summary</big></U></B>
|
<A name="ptwr_hold_rs"></A><B><U><big>Report Summary</big></U></B>
|
--------------
|
--------------
|
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
Preference(MIN Delays) | Constraint| Actual|Levels
|
Preference(MIN Delays) | Constraint| Actual|Levels
|
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
| | |
|
| | |
|
FREQUENCY NET "cpu_clkgen" 40.000000 | | |
|
FREQUENCY NET "clk40_i_c" 111.645000 | | |
|
MHz ; | -| -| 1
|
MHz ; | 0.000 ns| 0.199 ns| 1
|
| | |
|
| | |
|
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
|
|
|
|
All preferences were met.
|
All preferences were met.
|
| Line 1363... |
Line 1476... |
<A name="ptwr_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
<A name="ptwr_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
------------------------
|
------------------------
|
|
|
Found 1 clocks:
|
Found 1 clocks:
|
|
|
Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 367
|
Clock Domain: clk40_i_c Source: clk40_i.PAD Loads: 318
|
Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
Covered under: FREQUENCY NET "clk40_i_c" 111.645000 MHz ;
|
|
|
|
|
<A name="ptwr_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
|
<A name="ptwr_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
|
---------------
|
---------------
|
|
|
Timing errors: 0 Score: 0
|
Timing errors: 0 Score: 0
|
Cumulative negative slack: 0
|
Cumulative negative slack: 0
|
|
|
Constraints cover 1107881 paths, 1 nets, and 9532 connections (99.1% coverage)
|
Constraints cover 1430483 paths, 1 nets, and 9633 connections (99.1% coverage)
|
|
|
|
|
|
|
<A name="ptwr_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
|
<A name="ptwr_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
|
---------------
|
---------------
|
|
|
Timing errors: 0 (setup), 0 (hold)
|
Timing errors: 4096 (setup), 0 (hold)
|
Score: 0 (setup), 0 (hold)
|
Score: 88089612 (setup), 0 (hold)
|
Cumulative negative slack: 0 (0+0)
|
Cumulative negative slack: 88089612 (88089612+0)
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
|
|
