Line 1... |
Line 1... |
# Synospys Constraint Checker(syntax only), version maplat, Build 618R, built Mar 14 2013
|
# Synospys Constraint Checker(syntax only), version maplat, Build 618R, built Mar 14 2013
|
# Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
# Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
|
|
# Written on Sun Dec 29 07:16:30 2013
|
# Written on Sun Jun 22 08:17:23 2014
|
|
|
|
|
##### DESIGN INFO #######################################################
|
##### DESIGN INFO #######################################################
|
|
|
Top View: "CC3_top"
|
Top View: "CC3_top"
|
Line 23... |
Line 23... |
|
|
Start Requested Requested Clock Clock
|
Start Requested Requested Clock Clock
|
Clock Frequency Period Type Group
|
Clock Frequency Period Type Group
|
----------------------------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------------------------
|
CC3_top|clk40_i 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0
|
CC3_top|clk40_i 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0
|
|
CC3_top|div_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Autoconstr_clkgroup_0
|
CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Autoconstr_clkgroup_0
|
CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Autoconstr_clkgroup_0
|
======================================================================================================================
|
======================================================================================================================
|