Subversion Repositories 6809_6309_compatible_core

Date:        Mon Dec 30 07:52:25 2013

Date:        Tue Dec 31 08:52:23 2013

Run Time:00h:00m:02s

Run Time:00h:00m:03s

Run Time:00h:00m:00s

Run Time:00h:00m:01s

Run Time:00h:00m:18s

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#Mon Dec 30 07:52:25 2013

#Tue Dec 31 08:52:23 2013

File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v changed - recompiling

File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v changed - recompiling

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":211:0:211:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":244:0:244:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":130:7:130:15|Synthesizing module decode_op

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":131:7:131:15|Synthesizing module decode_op

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":258:7:258:15|Synthesizing module decode_ea

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":259:7:259:15|Synthesizing module decode_ea

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":284:7:284:16|Synthesizing module decode_alu

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":285:7:285:16|Synthesizing module decode_alu

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":357:7:357:20|Synthesizing module test_condition

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":358:7:358:20|Synthesizing module test_condition

@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":419:6:419:13|Ignoring system task $display

@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":429:6:429:13|Ignoring system task $display

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":943:0:943:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":967:0:967:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_pp_active_reg[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_postbyte0[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_pp_active_reg[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Register bit k_mem_dest[0] is always 1, optimizing ...

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Register bit k_mem_dest[1] is always 0, optimizing ...

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Register bit next_mem_state[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Register bit k_mem_dest[0] is always 1, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Register bit next_mem_state[2] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Register bit k_mem_dest[1] is always 0, optimizing ...

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Pruning register bits 2 to 1 of next_mem_state[5:0]

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Register bit next_mem_state[1] is always 0, optimizing ...

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Pruning register bits 5 to 2 of next_push_state[5:0]

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Pruning register bits 5 to 2 of next_push_state[5:0]

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":361:18:361:20|Input port bits 7 to 4 of CCR[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":362:18:362:20|Input port bits 7 to 4 of CCR[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":286:18:286:26|Input port bits 5 to 4 of postbyte0[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":287:18:287:26|Input port bits 5 to 4 of postbyte0[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":259:18:259:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":260:18:260:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused

# Mon Dec 30 07:52:26 2013

# Tue Dec 31 08:52:25 2013

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)

Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

# Mon Dec 30 07:52:27 2013

# Tue Dec 31 08:52:27 2013

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":168:0:168:5|Found counter in view:work.regblock(verilog) inst PC[15:0]

@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Found counter in view:work.regblock(verilog) inst PC[15:0]

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Removing sequential instance k_clear_e in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Removing sequential instance k_set_e in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 159MB)

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 160MB)

@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":205:2:205:3|Pipelining module un1_data_w_1[15:0]

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":168:0:168:5|Register SU[15:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":168:0:168:5|Register ACCB[7:0] pushed in.

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 162MB)

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":168:0:168:5|Register DP[7:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":380:0:380:5|Register regq16[15:0] pushed in.

@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":24:22:24:42|Pipelining module result_size

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Register k_ind_ea[7:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":380:0:380:5|Register regq16[15:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":168:0:168:5|Register vff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register hflag pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":168:0:168:5|Register zff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register intff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":291:0:291:5|Register k_eahi[7:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register vff pushed in.

@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":256:2:256:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.k_new_pc_1[15:0] from cpu0.un1_regs_o_pc[15:0]

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register cff pushed in.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 149MB peak: 159MB)

Starting Early Timing Optimization (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 152MB peak: 162MB)

Finished Early Timing Optimization (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 149MB peak: 159MB)

Finished Early Timing Optimization (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 152MB peak: 162MB)

Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 148MB peak: 159MB)

Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 151MB peak: 162MB)

Finished preparing to map (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 147MB peak: 159MB)

Finished preparing to map (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 149MB peak: 162MB)

Finished technology mapping (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 175MB peak: 226MB)

Finished technology mapping (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 191MB peak: 228MB)

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 175MB peak: 226MB)

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 166MB peak: 228MB)

Finished restoring hierarchy (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 176MB peak: 226MB)

Finished restoring hierarchy (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 167MB peak: 228MB)

1 non-gated/non-generated clock tree(s) driving 408 clock pin(s) of sequential element(s)

1 non-gated/non-generated clock tree(s) driving 577 clock pin(s) of sequential element(s)

212 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks

223 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks

@K:CKID0001       clk40_i             port                   408        cpu_clk

@K:CKID0001       clk40_i             port                   577        cpu_clk

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 177MB peak: 226MB)

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 169MB peak: 228MB)

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 182MB peak: 226MB)

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 173MB peak: 228MB)

# Timing Report written on Mon Dec 30 07:52:44 2013

# Timing Report written on Tue Dec 31 08:52:45 2013

Worst slack in design: 972.475

Worst slack in design: 971.433

CC3_top|clk40_i     1.0 MHz       36.3 MHz      1000.000      27.525        972.475     inferred     Inferred_clkgroup_0

CC3_top|clk40_i     1.0 MHz       35.0 MHz      1000.000      28.567        971.433     inferred     Inferred_clkgroup_0

CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    972.475  |  No paths    -      |  No paths    -      |  No paths    -

CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    971.434  |  No paths    -      |  No paths    -      |  No paths    -

------------------------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------------

cpu0.k_opcode[7]        CC3_top|clk40_i     FD1P3AX     Q       k_opcode[7]        1.341       972.475

cpu0.k_opcode[4]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[4]       1.333       971.433

cpu0.k_opcode[6]        CC3_top|clk40_i     FD1P3AX     Q       k_opcode[6]        1.333       972.482

cpu0.k_opcode[5]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[5]       1.326       971.441

cpu0.k_opcode[2]        CC3_top|clk40_i     FD1P3AX     Q       k_opcode[2]        1.358       972.578

cpu0.k_opcode[0]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[0]       1.358       971.513

cpu0.k_opcode[0]        CC3_top|clk40_i     FD1P3AX     Q       k_opcode[0]        1.350       972.586

cpu0.k_opcode[3]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[3]       1.352       971.519

cpu0.k_postbyte0[7]     CC3_top|clk40_i     FD1P3AX     Q       k_postbyte0[7]     1.284       972.652

cpu0.k_opcode[1]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[1]       1.344       971.527

cpu0.k_postbyte0[1]     CC3_top|clk40_i     FD1P3AX     Q       k_postbyte0[1]     1.280       972.656

cpu0.k_opcode[7]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[7]       1.344       972.368

cpu0.k_postbyte0[2]     CC3_top|clk40_i     FD1P3AX     Q       k_postbyte0[2]     1.260       972.676

cpu0.k_opcode[6]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[6]       1.336       972.416

cpu0.k_opcode[1]        CC3_top|clk40_i     FD1P3AX     Q       k_opcode[1]        1.349       972.763

cpu0.k_opcode[2]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[2]       1.368       972.560

cpu0.k_opcode[4]        CC3_top|clk40_i     FD1P3AX     Q       k_opcode[4]        1.326       972.786

cpu0.k_postbyte[5]     CC3_top|clk40_i     FD1P3AX     Q       k_postbyte[5]     1.276       973.285

cpu0.k_opcode[5]        CC3_top|clk40_i     FD1P3AX     Q       k_opcode[5]        1.312       972.800

cpu0.k_postbyte[4]     CC3_top|clk40_i     FD1P3AX     Q       k_postbyte[4]     1.256       973.306

======================================================================================================

====================================================================================================

------------------------------------------------------------------------------------------------

-----------------------------------------------------------------------------------------------------

cpu0.regs.cff           CC3_top|clk40_i     FD1P3AX     D       cff_6       1000.089     972.475

cpu0.alu.regq16_pipe_124     CC3_top|clk40_i     FD1P3AX     D       N_911       1000.462     971.433

cpu0.alu.regq16[7]      CC3_top|clk40_i     FD1P3AX     D       q16[7]      1000.089     973.138

cpu0.alu.regq16_pipe_28      CC3_top|clk40_i     FD1P3AX     D       N_910_0     1000.462     971.648

cpu0.alu.regq16[5]      CC3_top|clk40_i     FD1P3AX     D       q16[5]      1000.462     973.597

cpu0.alu.regq16_pipe_32      CC3_top|clk40_i     FD1P3AX     D       N_909       1000.462     971.648

cpu0.alu.regq16[6]      CC3_top|clk40_i     FD1P3AX     D       q16[6]      1000.462     973.597

cpu0.alu.regq16_pipe_38      CC3_top|clk40_i     FD1P3AX     D       N_919       1000.462     971.951

cpu0.alu.regq16[15]     CC3_top|clk40_i     FD1P3AX     D       q16[15]     1000.462     973.737

cpu0.alu.regq16_pipe_49      CC3_top|clk40_i     FD1P3AX     D       N_918       1000.462     972.094

cpu0.alu.regq16[13]     CC3_top|clk40_i     FD1P3AX     D       q16[13]     1000.462     973.880

cpu0.alu.regq16_pipe_60      CC3_top|clk40_i     FD1P3AX     D       N_917       1000.462     972.094

cpu0.alu.regq16[14]     CC3_top|clk40_i     FD1P3AX     D       q16[14]     1000.462     973.880

cpu0.alu.regq16_pipe_71      CC3_top|clk40_i     FD1P3AX     D       N_916       1000.462     972.237

cpu0.alu.regq16[11]     CC3_top|clk40_i     FD1P3AX     D       q16[11]     1000.462     974.023

cpu0.alu.regq16_pipe_82      CC3_top|clk40_i     FD1P3AX     D       N_915       1000.462     972.237

cpu0.alu.regq16[12]     CC3_top|clk40_i     FD1P3AX     D       q16[12]     1000.462     974.023

cpu0.alu.regq16_pipe_93      CC3_top|clk40_i     FD1P3AX     D       N_914       1000.462     972.380

cpu0.alu.regq16[9]      CC3_top|clk40_i     FD1P3AX     D       q16[9]      1000.462     974.165

cpu0.alu.regq16_pipe_104     CC3_top|clk40_i     FD1P3AX     D       N_913       1000.462     972.380

================================================================================================

=====================================================================================================

    - Setup time:                            -0.089

    - Setup time:                            -0.462

    = Required time:                         1000.089

    = Required time:                         1000.462

    - Propagation time:                      27.613

    - Propagation time:                      29.029

    = Slack (critical) :                     972.475

    = Slack (critical) :                     971.433

    Number of logic level(s):                26

    Number of logic level(s):                25

    Starting point:                          cpu0.k_opcode[7] / Q

    Starting point:                          cpu0.k_opcode[4] / Q

    Ending point:                            cpu0.regs.cff / D

    Ending point:                            cpu0.alu.regq16_pipe_124 / D

--------------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------------------

cpu0.k_opcode[7]                                           FD1P3AX      Q        Out     1.341      1.341       -

cpu0.k_opcode[4]                                           FD1P3AX      Q        Out     1.333     1.333       -

k_opcode[7]                                                Net          -        -       -          -           42

k_opcode[4]                                                Net          -        -       -         -           38

cpu0.dec_op.mode_4_0_o5[2]                                 ORCALUT4     B        In      0.000      1.341       -

cpu0.dec_regs.state53_2_i_o2                               ORCALUT4     A        In      0.000     1.333       -

cpu0.dec_op.mode_4_0_o5[2]                                 ORCALUT4     Z        Out     1.313      2.653       -

cpu0.dec_regs.state53_2_i_o2                               ORCALUT4     Z        Out     1.193     2.526       -

N_222                                                      Net          -        -       -          -           17

N_76                                                       Net          -        -       -         -           4

cpu0.dec_regs.un1_dest_reg_3_sqmuxa_1_1_2                  ORCALUT4     B        In      0.000      2.653       -

cpu0.dec_regs.un1_dest_reg53_2_0_a2                        ORCALUT4     B        In      0.000     2.526       -

cpu0.dec_regs.un1_dest_reg_3_sqmuxa_1_1_2                  ORCALUT4     Z        Out     1.017      3.670       -

cpu0.dec_regs.un1_dest_reg53_2_0_a2                        ORCALUT4     Z        Out     1.089     3.615       -

un1_dest_reg_3_sqmuxa_1_1_2                                Net          -        -       -          -           1

N_54_mux                                                   Net          -        -       -         -           2

cpu0.dec_regs.un1_dest_reg_3_sqmuxa_1_1                    ORCALUT4     C        In      0.000      3.670       -

cpu0.dec_regs.un1_dest_reg53_2_0                           ORCALUT4     D        In      0.000     3.615       -

cpu0.dec_regs.un1_dest_reg_3_sqmuxa_1_1                    ORCALUT4     Z        Out     1.193      4.863       -

cpu0.dec_regs.un1_dest_reg53_2_0                           ORCALUT4     Z        Out     1.089     4.704       -

un1_dest_reg_3_sqmuxa_1_0                                  Net          -        -       -          -           4

un1_dest_reg53_2                                           Net          -        -       -         -           2

cpu0.dec_regs.un1_path_left_addr29_RNIG19H                 ORCALUT4     A        In      0.000      4.863       -

cpu0.dec_regs.un1_dest_reg44_1_2                           ORCALUT4     C        In      0.000     4.704       -

cpu0.dec_regs.un1_path_left_addr29_RNIG19H                 ORCALUT4     Z        Out     1.089      5.952       -

cpu0.dec_regs.un1_dest_reg44_1_2                           ORCALUT4     Z        Out     1.153     5.857       -

N_491                                                      Net          -        -       -          -           2

un1_dest_reg44_1_2                                         Net          -        -       -         -           3

cpu0.dec_regs.path_left_addr_cnst_0[0]                     ORCALUT4     B        In      0.000      5.952       -

cpu0.dec_regs.un1_dest_reg44_1                             ORCALUT4     B        In      0.000     5.857       -

cpu0.dec_regs.path_left_addr_cnst_0[0]                     ORCALUT4     Z        Out     1.017      6.969       -

cpu0.dec_regs.un1_dest_reg44_1                             ORCALUT4     Z        Out     1.089     6.945       -

path_left_addr_cnst[0]                                     Net          -        -       -          -           1

un1_dest_reg44_1                                           Net          -        -       -         -           2

cpu0.dec_regs.path_left_addr[0]                            ORCALUT4     B        In      0.000      6.969       -

cpu0.dec_regs.path_left_addr_2_sqmuxa                      ORCALUT4     B        In      0.000     6.945       -

cpu0.dec_regs.path_left_addr[0]                            ORCALUT4     Z        Out     0.449      7.417       -

cpu0.dec_regs.path_left_addr_2_sqmuxa                      ORCALUT4     Z        Out     1.233     8.178       -

dec_o_left_path_addr[0]                                    Net          -        -       -          -           2

path_left_addr_2_sqmuxa                                    Net          -        -       -         -           6

cpu0.regs.datamux_o_alu_in_left_path_addr_1_0[0]           ORCALUT4     B        In      0.000      7.417       -

cpu0.dec_regs.un1_dest_reg44_1_RNIU7BO                     ORCALUT4     A        In      0.000     8.178       -

cpu0.regs.datamux_o_alu_in_left_path_addr_1_0[0]           ORCALUT4     Z        Out     1.089      8.506       -

cpu0.dec_regs.un1_dest_reg44_1_RNIU7BO                     ORCALUT4     Z        Out     1.089     9.267       -

N_1048                                                     Net          -        -       -          -           2

N_519                                                      Net          -        -       -         -           2

cpu0.regs.datamux_o_alu_in_left_path_addr_1[0]             ORCALUT4     A        In      0.000      8.506       -

cpu0.dec_regs.path_left_addr_bm[0]                         ORCALUT4     A        In      0.000     9.267       -

cpu0.regs.datamux_o_alu_in_left_path_addr_1[0]             ORCALUT4     Z        Out     1.406      9.913       -

cpu0.dec_regs.path_left_addr_bm[0]                         ORCALUT4     Z        Out     1.017     10.284      -

datamux_o_alu_in_left_path_addr_1[0]                       Net          -        -       -          -           55

path_left_addr_bm[0]                                       Net          -        -       -         -           1

cpu0.regs.datamux_o_alu_in_left_path_addr_1_RNIL7SL[2]     ORCALUT4     A        In      0.000      9.913       -

cpu0.dec_regs.path_left_addr[0]                            PFUMX        ALUT     In      0.000     10.284      -

cpu0.regs.datamux_o_alu_in_left_path_addr_1_RNIL7SL[2]     ORCALUT4     Z        Out     1.297      11.209      -

cpu0.dec_regs.path_left_addr[0]                            PFUMX        Z        Out     0.350     10.634      -

N_339                                                      Net          -        -       -          -           13

dec_o_left_path_addr[0]                                    Net          -        -       -         -           3

cpu0.regs.path_left_data_6[0]                              ORCALUT4     B        In      0.000      11.209      -

cpu0.regs.datamux_o_alu_in_left_path_addr_1_0[0]           ORCALUT4     B        In      0.000     10.634      -

cpu0.regs.path_left_data_6[0]                              ORCALUT4     Z        Out     1.017      12.226      -

cpu0.regs.datamux_o_alu_in_left_path_addr_1_0[0]           ORCALUT4     Z        Out     1.017     11.651      -

N_375                                                      Net          -        -       -          -           1

N_1062                                                     Net          -        -       -         -           1

cpu0.regs.path_left_data[0]                                PFUMX        ALUT     In      0.000      12.226      -

cpu0.regs.datamux_o_alu_in_left_path_addr_1[0]             ORCALUT4     A        In      0.000     11.651      -

cpu0.regs.path_left_data[0]                                PFUMX        Z        Out     0.350      12.576      -

cpu0.regs.datamux_o_alu_in_left_path_addr_1[0]             ORCALUT4     Z        Out     1.384     13.035      -

regs_o_left_path_data[0]                                   Net          -        -       -          -           3

datamux_o_alu_in_left_path_addr_1[0]                       Net          -        -       -         -           41

cpu0.alu.datamux_o_alu_in_left_path_data[0]                ORCALUT4     C        In      0.000      12.576      -

cpu0.regs.datamux_o_alu_in_left_path_addr_1_RNIUM5T[1]     ORCALUT4     A        In      0.000     13.035      -

cpu0.alu.datamux_o_alu_in_left_path_data[0]                ORCALUT4     Z        Out     1.386      13.962      -

cpu0.regs.datamux_o_alu_in_left_path_addr_1_RNIUM5T[1]     ORCALUT4     Z        Out     1.313     14.348      -

datamux_o_alu_in_left_path_data[0]                         Net          -        -       -          -           42

N_873                                                      Net          -        -       -         -           17

cpu0.alu.mul16_w_madd_0_cry_0_0                            CCU2D        C1       In      0.000      13.962      -

cpu0.regs.path_left_data_bm[0]                             ORCALUT4     C        In      0.000     14.348      -

cpu0.alu.mul16_w_madd_0_cry_0_0                            CCU2D        COUT     Out     1.544      15.507      -

cpu0.regs.path_left_data_bm[0]                             ORCALUT4     Z        Out     1.017     15.364      -

cpu0.alu.mul16_w_madd_0_cry_1_0                            CCU2D        CIN      In      0.000      15.507      -

cpu0.alu.mul16_w_madd_0_cry_1_0                            CCU2D        CIN      In      0.000     18.686      -

cpu0.alu.mul16_w_madd_0_cry_1_0                            CCU2D        S0       Out     1.621      17.128      -

cpu0.alu.mul16_w_madd_0_cry_1_0                            CCU2D        S0       Out     1.621     20.307      -

mul16_w_madd_4                                             Net          -        -       -          -           2

mul16_w_madd_0[2]                                          Net          -        -       -         -           2

cpu0.alu.mul16_w_madd_4_cry_0_0                            CCU2D        A1       In      0.000      17.128      -

cpu0.alu.mul16_w_madd_4_cry_0_0                            CCU2D        C1       In      0.000     20.307      -

cpu0.alu.mul16_w_madd_4_cry_0_0                            CCU2D        COUT     Out     1.544      18.672      -

cpu0.alu.mul16_w_madd_4_cry_0_0                            CCU2D        COUT     Out     1.544     21.852      -

cpu0.alu.mul16_w_madd_4_cry_1_0                            CCU2D        CIN      In      0.000      18.672      -

cpu0.alu.mul16_w_madd_4_cry_1_0                            CCU2D        CIN      In      0.000     21.852      -

cpu0.alu.mul16_w_madd_4_cry_1_0                            CCU2D        S1       Out     1.621      20.293      -

cpu0.alu.mul16_w_madd_4_cry_1_0                            CCU2D        S1       Out     1.621     23.473      -

cpu0.alu.mul16_w_madd_cry_0_0                              CCU2D        A1       In      0.000      20.293      -

cpu0.alu.mul16_w_madd_cry_0_0                              CCU2D        A1       In      0.000     23.473      -

cpu0.alu.mul16_w_madd_cry_0_0                              CCU2D        COUT     Out     1.544      21.837      -

cpu0.alu.mul16_w_madd_cry_0_0                              CCU2D        COUT     Out     1.544     25.017      -

cpu0.alu.mul16_w_madd_cry_1_0                              CCU2D        CIN      In      0.000      21.837      -

cpu0.alu.mul16_w_madd_cry_1_0                              CCU2D        CIN      In      0.000     25.017      -

cpu0.alu.mul16_w_madd_cry_1_0                              CCU2D        COUT     Out     0.143      21.980      -

cpu0.alu.mul16_w_madd_cry_1_0                              CCU2D        COUT     Out     0.143     25.160      -

cpu0.alu.mul16_w_madd_cry_3_0                              CCU2D        CIN      In      0.000      21.980      -

cpu0.alu.mul16_w_madd_cry_3_0                              CCU2D        CIN      In      0.000     25.160      -

cpu0.alu.mul16_w_madd_cry_3_0                              CCU2D        S0       Out     1.621      23.601      -

cpu0.alu.mul16_w_madd_cry_3_0                              CCU2D        S0       Out     1.621     26.781      -

cpu0.alu.c16_12_bm                                         ORCALUT4     A        In      0.000      23.601      -

cpu0.alu.q16_20[7]                                         ORCALUT4     A        In      0.000     26.781      -

cpu0.alu.c16_12_bm                                         ORCALUT4     Z        Out     1.017      24.618      -

cpu0.alu.q16_20[7]                                         ORCALUT4     Z        Out     1.017     27.798      -

c16_12_bm                                                  Net          -        -       -          -           1

N_847                                                      Net          -        -       -         -           1

cpu0.alu.c16_12                                            PFUMX        ALUT     In      0.000      24.618      -

cpu0.alu.q16_24_am[7]                                      ORCALUT4     A        In      0.000     27.798      -

cpu0.alu.c16_12                                            PFUMX        Z        Out     0.214      24.832      -

cpu0.alu.q16_24_am[7]                                      ORCALUT4     Z        Out     1.017     28.815      -

N_1001                                                     Net          -        -       -          -           1

q16_24_am[7]                                               Net          -        -       -         -           1

cpu0.alu.c16_19_am                                         ORCALUT4     B        In      0.000      24.832      -

cpu0.alu.q16_24[7]                                         PFUMX        BLUT     In      0.000     28.815      -

cpu0.alu.c16_19_am                                         ORCALUT4     Z        Out     1.017      25.849      -

cpu0.alu.q16_24[7]                                         PFUMX        Z        Out     0.214     29.029      -

c16_19_am                                                  Net          -        -       -          -           1

N_911                                                      Net          -        -       -         -           1

cpu0.alu.c16_19                                            PFUMX        BLUT     In      0.000      25.849      -

cpu0.alu.regq16_pipe_124                                   FD1P3AX      D        In      0.000     29.029      -

cpu0.alu.c16_19                                            PFUMX        Z        Out     -0.033     25.816      -

=========================================================================================================================

Register bits: 404 of 6864 (6%)

Register bits: 573 of 6864 (8%)

FD1P3AX:        384

FD1P3AX:        552

FD1P3IX:        1

FD1P3IX:        2

INV:            4

INV:            11

L6MUX21:        12

L6MUX21:        22

ORCALUT4:       1771

ORCALUT4:       2177

PFUMX:          235

PFUMX:          315

At Mapper Exit (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 43MB peak: 226MB)

At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 44MB peak: 228MB)

Process took 0h:00m:17s realtime, 0h:00m:17s cputime

Process took 0h:00m:18s realtime, 0h:00m:18s cputime

# Mon Dec 30 07:52:44 2013

# Tue Dec 31 08:52:45 2013

  On or above line 549 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 610 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 2250 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 1405 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 3439 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 1481 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 4857 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 2852 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 6946 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 6393 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 15891 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 18874 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 28347 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 33610 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 28765 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 34028 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 33148 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 38347 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 33818 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 39078 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_7_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_s_11_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_7_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_s_11_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_5_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_5_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_3_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_5_s_11_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_3_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_5_s_11_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_1_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_5_cry_2_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_1_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_5_cry_2_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_4_cry_9_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/mul16_w_madd_4_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_7_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_7_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_7_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_7_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_5_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_5_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_5_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_5_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_3_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_3_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_3_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_3_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_1_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_1_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_1_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_1_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sub8_w_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/add8_w_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sbc8_w_cry_7_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/k_new_pc_4_s_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sbc8_w_cry_7_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/k_new_pc_4_s_15_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sbc8_w_cry_5_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/k_new_pc_4_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/sbc8_w_cry_5_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/k_new_pc_4_cry_0_0_S1' has no load

   2654 blocks expanded

   3326 blocks expanded

WARNING - map: Using local reset signal 'cpu0.cpu_reset_i_3_i' to infer global GSR net.

WARNING - map: Using local reset signal 'cpu0.cpu_reset_i_2_i' to infer global GSR net.

   Number of registers:    404

   Number of registers:    573

      PFU registers:    396

      PFU registers:    565

   Number of SLICEs:          1051 out of  3432 (31%)

   Number of SLICEs:          1259 out of  3432 (37%)

      SLICEs(logic/ROM/RAM):   193 out of  2574 (7%)

      SLICEs(logic/ROM/RAM):   401 out of  2574 (16%)

          As Logic/ROM:    193 out of  2574 (7%)

          As Logic/ROM:    401 out of  2574 (16%)

   Number of logic LUT4s:     1775

   Number of logic LUT4s:     2189

   Total number of LUT4s:     2099

   Total number of LUT4s:     2513

     Net cpu_clkgen: 251 loads, 251 rising, 0 falling (Driver: PIO clk40_i )

     Net cpu_clkgen: 374 loads, 374 rising, 0 falling (Driver: PIO clk40_i )

   Number of Clock Enables:  26

   Number of Clock Enables:  27

     Net cpu_clk: 84 loads, 84 LSLICEs

     Net cpu_clk: 187 loads, 187 LSLICEs

     Net leds_r_cnv[0]: 8 loads, 0 LSLICEs

     Net k_cpu_we_RNIKJPB: 8 loads, 0 LSLICEs

     Net cpu0/un1_state_53_0_a2_RNIA03MC: 5 loads, 5 LSLICEs

     Net cpu0/k_ealo_0_sqmuxa_RNICERE1: 5 loads, 5 LSLICEs

     Net cpu0/un1_state_116_i_a4_RNIUVE1B: 3 loads, 3 LSLICEs

     Net cpu0/k_new_pc26_RNICEI54: 3 loads, 3 LSLICEs

     Net cpu0/state_cnst_0_a2_8_RNINHMI3[1]: 1 loads, 1 LSLICEs

     Net cpu0/k_ealo_cnv_0[0]: 13 loads, 13 LSLICEs

     Net cpu0/un1_state_32_RNIMUU2H: 4 loads, 4 LSLICEs

     Net cpu0/k_eahi_0_sqmuxa_2_RNIC7377: 4 loads, 4 LSLICEs

     Net cpu0/k_ealo_cnv_0[0]: 9 loads, 9 LSLICEs

     Net cpu0/k_pp_regs55_RNIJTK99: 2 loads, 2 LSLICEs

     Net cpu0/un1_state_86_1_RNIK6NAG: 2 loads, 2 LSLICEs

     Net cpu0/un1_state_31_RNIDQAP: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_23_1_RNIUF382: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_28_0_a2_RNIKHLH: 5 loads, 5 LSLICEs

     Net cpu0/un1_state_31_RNINL5R: 4 loads, 4 LSLICEs

     Net cpu0/un1_k_opcode_4_RNII2FP8: 8 loads, 8 LSLICEs

     Net cpu0/un1_state_28_2_RNIGSC31: 5 loads, 5 LSLICEs

     Net cpu0/k_ofshi_1_sqmuxa_RNI9N8V: 4 loads, 4 LSLICEs

     Net cpu0/un3_cpu_reset_RNIF4SQ3: 5 loads, 5 LSLICEs

     Net cpu0/state79_RNICDUH4: 1 loads, 1 LSLICEs

     Net cpu0/k_new_pc29_RNIT8401: 4 loads, 4 LSLICEs

     Net cpu0/cff_0_sqmuxa_1_i_0_0_RNIAM8L: 44 loads, 44 LSLICEs

     Net cpu0/un3_cpu_reset_RNIB1387: 4 loads, 4 LSLICEs

     Net cpu0/regs/eflag_RNO: 1 loads, 1 LSLICEs

     Net cpu0/un1_k_opcode_3_RNIA4FBB: 8 loads, 8 LSLICEs

     Net cpu0/regs/IY_0_sqmuxa_i_a3_0_RNI01N31: 18 loads, 18 LSLICEs

     Net cpu0/un1_state_74_RNIGHLC3: 4 loads, 4 LSLICEs

     Net cpu0/regs/IX_0_sqmuxa_1_i_a2_RNIKUBD1: 17 loads, 17 LSLICEs

     Net cpu0/regs/datamux_o_dest_reg_addr_RNITQPK1[0]: 9 loads, 9 LSLICEs

     Net cpu0/regs/DP_0_sqmuxa_i_a3_0_RNIV3T11: 7 loads, 7 LSLICEs

     Net cpu0/datamux_o_dest_reg_addr_RNIEAM92[3]: 27 loads, 27 LSLICEs

     Net cpu0/regs/ACCB_0_sqmuxa_1_RNIGOBV: 7 loads, 7 LSLICEs

     Net cpu0/regs/IY_1_sqmuxa_1_RNIRVQM1: 17 loads, 17 LSLICEs

     Net cpu0/regs/ACCB45_RNI83PT2: 4 loads, 4 LSLICEs

     Net cpu0/regs/IX_0_sqmuxa_1_i_a3_0_RNI5MLM1: 17 loads, 17 LSLICEs

     Net cpu0/k_memlo_1_sqmuxa_RNIT89Q: 4 loads, 4 LSLICEs

     Net cpu0/regs/datamux_o_dest_reg_addr_RNI537B1_0[3]: 4 loads, 4 LSLICEs

     Net cpu0/next_state_0_sqmuxa_2_0_a2_RNII5VUC1: 3 loads, 3 LSLICEs

     Net cpu0/regs/datamux_o_dest_reg_addr_RNI537B1[3]: 6 loads, 6 LSLICEs

     Net cpu0/k_new_pc29_RNIV0H41: 4 loads, 4 LSLICEs

     Net cpu0/k_new_pc28_RNIL0CFA: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_74_RNIID554: 4 loads, 4 LSLICEs

     Net cpu0/k_ofshi_1_sqmuxa_RNIAOQN: 4 loads, 4 LSLICEs

     Net cpu0/un3_cpu_reset_RNIO5453: 4 loads, 4 LSLICEs

     Net cpu0/k_memhi_0_sqmuxa_RNILK7P1: 4 loads, 4 LSLICEs

     Net cpu0/un3_cpu_reset_RNIT72KK: 4 loads, 4 LSLICEs

   Number of local set/reset loads for net cpu0.cpu_reset_i_3_i merged into GSR:  6

     Net cpu0/un3_cpu_reset_RNIRKP92: 4 loads, 4 LSLICEs

   Number of LSRs:  1

   Number of local set/reset loads for net cpu0.cpu_reset_i_2_i merged into GSR:  6

     Net cpu0/state_RNIUN03D[5]: 3 loads, 3 LSLICEs

   Number of LSRs:  2

     Net cpu0/dec_o_alu_opcode[0]: 210 loads

     Net cpu_clk: 211 loads

     Net cpu0/dec_o_alu_opcode[2]: 161 loads

     Net cpu0/dec_o_alu_opcode[0]: 192 loads

     Net cpu0/dec_o_alu_opcode[3]: 130 loads

     Net cpu0/dec_o_alu_opcode[2]: 124 loads

     Net cpu_clk: 103 loads

     Net cpu0/dec_o_alu_opcode[3]: 104 loads

     Net state_o_c[0]: 73 loads

     Net state_o_c[1]: 75 loads

     Net state_o_c[3]: 64 loads

     Net cpu0/dec_o_p1_mode[0]: 68 loads

     Net state_o_c[4]: 59 loads

     Net state_o_c[4]: 65 loads

Total CPU Time: 0 secs

Total CPU Time: 1 secs

Peak Memory Usage: 192 MB

Peak Memory Usage: 195 MB

Mon Dec 30 07:52:48 2013

Tue Dec 31 08:52:49 2013

Timing errors: 4096  Score: 36144319

Timing errors: 4096  Score: 43964214

Cumulative negative slack: 36144319

Cumulative negative slack: 43964214

Constraints cover 34676514 paths, 1 nets, and 7843 connections (96.2% coverage)

Constraints cover 130482274 paths, 1 nets, and 9545 connections (95.7% coverage)

Mon Dec 30 07:52:48 2013

Tue Dec 31 08:52:49 2013

Constraints cover 34676514 paths, 1 nets, and 8082 connections (99.1% coverage)

Constraints cover 130482274 paths, 1 nets, and 9903 connections (99.2% coverage)