Subversion Repositories 6809_6309_compatible_core

Date:        Tue Dec 31 08:52:23 2013

Date:        Wed Jan  1 11:05:21 2014

Run Time:00h:00m:03s

Run Time:00h:00m:04s

Run Time:00h:00m:01s

Run Time:00h:00m:00s

Run Time:00h:00m:19s

Run Time:00h:00m:16s

#Tue Dec 31 08:52:23 2013

#Wed Jan  1 11:05:21 2014

File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v changed - recompiling

Options changed - recompiling

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":13:7:13:11|Synthesizing module alu16

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":57:7:57:10|Synthesizing module alu8

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":500:0:500:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":319:0:319:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":244:0:244:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":243:0:243:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":429:6:429:13|Ignoring system task $display

@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":445:6:445:13|Ignoring system task $display

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":967:0:967:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1017:0:1017:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":64:11:64:23|No assignment to wire alu8_o_result

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":65:11:65:20|No assignment to wire alu8_o_CCR

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_pp_active_reg[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Register bit k_mem_dest[0] is always 1, optimizing ...

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Register bit k_mem_dest[1] is always 0, optimizing ...

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Register bit next_mem_state[1] is always 0, optimizing ...

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Register bit next_mem_state[2] is always 0, optimizing ...

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Pruning register bits 2 to 1 of next_mem_state[5:0]

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Pruning register bits 5 to 2 of next_push_state[5:0]

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Pruning register bits 5 to 3 of next_push_state[5:0]

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process took 0h:00m:02s realtime, 0h:00m:02s cputime

# Tue Dec 31 08:52:25 2013

# Wed Jan  1 11:05:23 2014

# Tue Dec 31 08:52:27 2013

# Wed Jan  1 11:05:25 2014

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 156MB peak: 157MB)

Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 153MB peak: 156MB)

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":299:0:299:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":315:0:315:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 160MB)

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 156MB)

@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":24:22:24:42|Pipelining module result_size

@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":237:2:237:3|Pipelining module un1_ea_reg_2[15:0]

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":380:0:380:5|Register regq8[7:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register SU[15:0] pushed in.

@N: MF169 :|Register NoName pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register DP[7:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register SU[15:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register cff pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":380:0:380:5|Register regq16[15:0] pushed in.

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":35:0:35:5|Register rb_in[15:0] pushed in.

@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":264:2:264:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.k_new_pc_4[15:0] from cpu0.un1_regs_o_pc[15:0]

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register nff pushed in.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 152MB peak: 162MB)

Starting Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 150MB peak: 162MB)

Finished Early Timing Optimization (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 152MB peak: 162MB)

Finished Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 150MB peak: 162MB)

Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 151MB peak: 162MB)

Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 162MB)

Finished preparing to map (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 149MB peak: 162MB)

Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 148MB peak: 162MB)

Finished technology mapping (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 191MB peak: 228MB)

Finished technology mapping (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 189MB peak: 227MB)

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 166MB peak: 228MB)

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 164MB peak: 227MB)

Finished restoring hierarchy (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 167MB peak: 228MB)

Finished restoring hierarchy (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 166MB peak: 227MB)

1 non-gated/non-generated clock tree(s) driving 577 clock pin(s) of sequential element(s)

1 non-gated/non-generated clock tree(s) driving 504 clock pin(s) of sequential element(s)

223 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks

233 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks

@K:CKID0001       clk40_i             port                   577        cpu_clk

@K:CKID0001       clk40_i             port                   504        cpu_clk

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 169MB peak: 228MB)

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 169MB peak: 227MB)

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 173MB peak: 228MB)

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 173MB peak: 227MB)

# Timing Report written on Tue Dec 31 08:52:45 2013

# Timing Report written on Wed Jan  1 11:05:41 2014

Worst slack in design: 971.433

Worst slack in design: 978.215

CC3_top|clk40_i     1.0 MHz       35.0 MHz      1000.000      28.567        971.433     inferred     Inferred_clkgroup_0

CC3_top|clk40_i     1.0 MHz       45.9 MHz      1000.000      21.785        978.215     inferred     Inferred_clkgroup_0

CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    971.434  |  No paths    -      |  No paths    -      |  No paths    -

CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    978.215  |  No paths    -      |  No paths    -      |  No paths    -

----------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------------------

cpu0.k_opcode[4]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[4]       1.333       971.433

cpu0.k_opcode[2]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[2]               1.374       978.215

cpu0.k_opcode[5]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[5]       1.326       971.441

cpu0.k_opcode[0]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[0]               1.361       978.228

cpu0.k_opcode[0]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[0]       1.358       971.513

cpu0.k_opcode[1]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[1]               1.366       978.263

cpu0.k_opcode[3]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[3]       1.352       971.519

cpu0.k_opcode[6]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[6]               1.336       978.293

cpu0.k_opcode[1]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[1]       1.344       971.527

cpu0.k_opcode[7]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[7]               1.352       978.341

cpu0.k_opcode[7]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[7]       1.344       972.368

cpu0.regs.SU_pipe_100     CC3_top|clk40_i     FD1P3AX     Q       un1_SU_4_sqmuxaf          1.268       978.356

cpu0.k_opcode[6]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[6]       1.336       972.416

cpu0.regs.SU_pipe_102     CC3_top|clk40_i     FD1P3AX     Q       SU_1_sqmuxa_5f            1.268       978.356

cpu0.k_opcode[2]       CC3_top|clk40_i     FD1P3AX     Q       k_opcode[2]       1.368       972.560

cpu0.regs.SS_pipe_100     CC3_top|clk40_i     FD1P3AX     Q       SS_1_sqmuxa_2f            1.268       978.420

cpu0.k_postbyte[5]     CC3_top|clk40_i     FD1P3AX     Q       k_postbyte[5]     1.276       973.285

cpu0.regs.SS_pipe_102     CC3_top|clk40_i     FD1P3AX     Q       un1_SU_0_sqmuxa_1_snf     1.268       978.420

cpu0.k_postbyte[4]     CC3_top|clk40_i     FD1P3AX     Q       k_postbyte[4]     1.256       973.306

cpu0.k_opcode[3]          CC3_top|clk40_i     FD1P3AX     Q       k_opcode[3]               1.385       978.484

====================================================================================================

===============================================================================================================

-----------------------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------

cpu0.alu.regq16_pipe_124     CC3_top|clk40_i     FD1P3AX     D       N_911       1000.462     971.433

cpu0.regs.PC[14]     CC3_top|clk40_i     FD1P3AX     D       PC_s[14]     999.894      978.215

cpu0.alu.regq16_pipe_28      CC3_top|clk40_i     FD1P3AX     D       N_910_0     1000.462     971.648

cpu0.regs.PC[15]     CC3_top|clk40_i     FD1P3AX     D       PC_s[15]     999.894      978.215

cpu0.alu.regq16_pipe_32      CC3_top|clk40_i     FD1P3AX     D       N_909       1000.462     971.648

cpu0.regs.PC[12]     CC3_top|clk40_i     FD1P3AX     D       PC_s[12]     999.894      978.358

cpu0.alu.regq16_pipe_38      CC3_top|clk40_i     FD1P3AX     D       N_919       1000.462     971.951

cpu0.regs.PC[13]     CC3_top|clk40_i     FD1P3AX     D       PC_s[13]     999.894      978.358

cpu0.alu.regq16_pipe_49      CC3_top|clk40_i     FD1P3AX     D       N_918       1000.462     972.094

cpu0.regs.PC[10]     CC3_top|clk40_i     FD1P3AX     D       PC_s[10]     999.894      978.501

cpu0.alu.regq16_pipe_60      CC3_top|clk40_i     FD1P3AX     D       N_917       1000.462     972.094

cpu0.regs.PC[11]     CC3_top|clk40_i     FD1P3AX     D       PC_s[11]     999.894      978.501

cpu0.alu.regq16_pipe_71      CC3_top|clk40_i     FD1P3AX     D       N_916       1000.462     972.237

cpu0.regs.PC[8]      CC3_top|clk40_i     FD1P3AX     D       PC_s[8]      999.894      978.644

cpu0.alu.regq16_pipe_82      CC3_top|clk40_i     FD1P3AX     D       N_915       1000.462     972.237

cpu0.regs.PC[9]      CC3_top|clk40_i     FD1P3AX     D       PC_s[9]      999.894      978.644

cpu0.alu.regq16_pipe_93      CC3_top|clk40_i     FD1P3AX     D       N_914       1000.462     972.380

cpu0.regs.PC[6]      CC3_top|clk40_i     FD1P3AX     D       PC_s[6]      999.894      978.786

cpu0.alu.regq16_pipe_104     CC3_top|clk40_i     FD1P3AX     D       N_913       1000.462     972.380

cpu0.regs.PC[7]      CC3_top|clk40_i     FD1P3AX     D       PC_s[7]      999.894      978.786

=====================================================================================================

==============================================================================================

    - Setup time:                            -0.462

    - Setup time:                            0.106

    = Required time:                         1000.462

    = Required time:                         999.894

    - Propagation time:                      29.029

    - Propagation time:                      21.679

    = Slack (critical) :                     971.433

    = Slack (critical) :                     978.215

    Number of logic level(s):                25

    Number of logic level(s):                22

    Starting point:                          cpu0.k_opcode[4] / Q

    Starting point:                          cpu0.k_opcode[2] / Q

    Ending point:                            cpu0.alu.regq16_pipe_124 / D

    Ending point:                            cpu0.regs.PC[15] / D

-------------------------------------------------------------------------------------------------------------------------

------------------------------------------------------------------------------------------------------------------------

cpu0.k_opcode[4]                                           FD1P3AX      Q        Out     1.333     1.333       -

cpu0.k_opcode[2]                                          FD1P3AX      Q        Out     1.374     1.374       -

k_opcode[4]                                                Net          -        -       -         -           38

k_opcode[2]                                               Net          -        -       -         -           63

cpu0.dec_regs.state53_2_i_o2                               ORCALUT4     A        In      0.000     1.333       -

cpu0.dec_regs.state_3_sqmuxa_1                            ORCALUT4     B        In      0.000     1.374       -

cpu0.dec_regs.state53_2_i_o2                               ORCALUT4     Z        Out     1.193     2.526       -

cpu0.dec_regs.state_3_sqmuxa_1                            ORCALUT4     Z        Out     1.193     2.567       -

N_76                                                       Net          -        -       -         -           4

state_3_sqmuxa_1                                          Net          -        -       -         -           4

cpu0.dec_regs.un1_dest_reg53_2_0_a2                        ORCALUT4     B        In      0.000     2.526       -

cpu0.dec_op.mode_4_i_a2[0]                                ORCALUT4     C        In      0.000     2.567       -

cpu0.dec_regs.un1_dest_reg53_2_0_a2                        ORCALUT4     Z        Out     1.089     3.615       -

cpu0.dec_op.mode_4_i_a2[0]                                ORCALUT4     Z        Out     1.193     3.760       -

N_54_mux                                                   Net          -        -       -         -           2

dest_reg_5_sqmuxa                                         Net          -        -       -         -           4

cpu0.dec_regs.un1_dest_reg53_2_0                           ORCALUT4     D        In      0.000     3.615       -

cpu0.dec_regs.un1_dest_reg44_1_1                          ORCALUT4     B        In      0.000     3.760       -

cpu0.dec_regs.un1_dest_reg53_2_0                           ORCALUT4     Z        Out     1.089     4.704       -

cpu0.dec_regs.un1_dest_reg44_1_1                          ORCALUT4     Z        Out     1.017     4.777       -

un1_dest_reg53_2                                           Net          -        -       -         -           2

un1_dest_reg44_1_1                                        Net          -        -       -         -           1

cpu0.dec_regs.un1_dest_reg44_1_2                           ORCALUT4     C        In      0.000     4.704       -

cpu0.dec_regs.un1_dest_reg44_1_2                          ORCALUT4     D        In      0.000     4.777       -

cpu0.dec_regs.un1_dest_reg44_1_2                           ORCALUT4     Z        Out     1.153     5.857       -

cpu0.dec_regs.un1_dest_reg44_1_2                          ORCALUT4     Z        Out     1.017     5.793       -

un1_dest_reg44_1_2                                         Net          -        -       -         -           3

un1_dest_reg44_1_2                                        Net          -        -       -         -           1

cpu0.dec_regs.un1_dest_reg44_1                             ORCALUT4     B        In      0.000     5.857       -

cpu0.dec_regs.un1_dest_reg44_1                            ORCALUT4     A        In      0.000     5.793       -

cpu0.dec_regs.un1_dest_reg44_1                             ORCALUT4     Z        Out     1.089     6.945       -

cpu0.dec_regs.un1_dest_reg44_1                            ORCALUT4     Z        Out     1.153     6.946       -

un1_dest_reg44_1                                           Net          -        -       -         -           2

un1_dest_reg44_1                                          Net          -        -       -         -           3

cpu0.dec_regs.path_left_addr_2_sqmuxa                      ORCALUT4     B        In      0.000     6.945       -

cpu0.dec_regs.path_left_addr_2_sqmuxa                     ORCALUT4     B        In      0.000     6.946       -

cpu0.dec_regs.path_left_addr_2_sqmuxa                      ORCALUT4     Z        Out     1.233     8.178       -

cpu0.dec_regs.path_left_addr_2_sqmuxa                     ORCALUT4     Z        Out     1.089     8.035       -

path_left_addr_2_sqmuxa                                    Net          -        -       -         -           6

path_left_addr_2_sqmuxa                                   Net          -        -       -         -           2

cpu0.dec_regs.un1_dest_reg44_1_RNIU7BO                     ORCALUT4     A        In      0.000     8.178       -

cpu0.dec_regs.path_left_addr_1_sqmuxa_2                   ORCALUT4     A        In      0.000     8.035       -

cpu0.dec_regs.un1_dest_reg44_1_RNIU7BO                     ORCALUT4     Z        Out     1.089     9.267       -

cpu0.dec_regs.path_left_addr_1_sqmuxa_2                   ORCALUT4     Z        Out     1.225     9.260       -

N_519                                                      Net          -        -       -         -           2

path_left_addr_1_sqmuxa_2                                 Net          -        -       -         -           5

cpu0.dec_regs.path_left_addr_bm[0]                         ORCALUT4     A        In      0.000     9.267       -

cpu0.dec_regs.k_write_exg10_1_RNITDRD5                    ORCALUT4     A        In      0.000     9.260       -

cpu0.dec_regs.path_left_addr_bm[0]                         ORCALUT4     Z        Out     1.017     10.284      -

cpu0.dec_regs.k_write_exg10_1_RNITDRD5                    ORCALUT4     Z        Out     1.193     10.453      -

path_left_addr_bm[0]                                       Net          -        -       -         -           1

path_left_addr_sn_N_2                                     Net          -        -       -         -           4

cpu0.dec_regs.path_left_addr[0]                            PFUMX        ALUT     In      0.000     10.284      -

cpu0.dec_regs.path_left_addr[3]                           PFUMX        C0       In      0.000     10.453      -

cpu0.dec_regs.path_left_addr[0]                            PFUMX        Z        Out     0.350     10.634      -

cpu0.dec_regs.path_left_addr[3]                           PFUMX        Z        Out     1.089     11.542      -

dec_o_left_path_addr[0]                                    Net          -        -       -         -           3

dec_o_left_path_addr[3]                                   Net          -        -       -         -           4

cpu0.regs.datamux_o_alu_in_left_path_addr_1_0[0]           ORCALUT4     B        In      0.000     10.634      -

cpu0.regs.datamux_o_alu_in_left_path_addr[3]              ORCALUT4     A        In      0.000     11.542      -

cpu0.regs.datamux_o_alu_in_left_path_addr_1_0[0]           ORCALUT4     Z        Out     1.017     11.651      -

cpu0.regs.datamux_o_alu_in_left_path_addr[3]              ORCALUT4     Z        Out     1.369     12.910      -

N_1062                                                     Net          -        -       -         -           1

datamux_o_alu_in_left_path_addr[3]                        Net          -        -       -         -           34

cpu0.regs.datamux_o_alu_in_left_path_addr_1[0]             ORCALUT4     A        In      0.000     11.651      -

cpu0.regs.datamux_o_alu_in_left_path_addr_RNIUORB1[1]     ORCALUT4     D        In      0.000     12.910      -

cpu0.regs.datamux_o_alu_in_left_path_addr_1[0]             ORCALUT4     Z        Out     1.384     13.035      -

cpu0.regs.datamux_o_alu_in_left_path_addr_RNIUORB1[1]     ORCALUT4     Z        Out     1.313     14.223      -

datamux_o_alu_in_left_path_addr_1[0]                       Net          -        -       -         -           41

N_784                                                     Net          -        -       -         -           16

cpu0.regs.datamux_o_alu_in_left_path_addr_1_RNIUM5T[1]     ORCALUT4     A        In      0.000     13.035      -

cpu0.regs.path_left_data_bm[3]                            ORCALUT4     C        In      0.000     14.223      -

cpu0.regs.datamux_o_alu_in_left_path_addr_1_RNIUM5T[1]     ORCALUT4     Z        Out     1.313     14.348      -

cpu0.regs.path_left_data_bm[3]                            ORCALUT4     Z        Out     1.017     15.240      -

N_873                                                      Net          -        -       -         -           17

path_left_data_bm[3]                                      Net          -        -       -         -           1

cpu0.regs.path_left_data_bm[0]                             ORCALUT4     C        In      0.000     14.348      -

cpu0.regs.path_left_data[3]                               PFUMX        ALUT     In      0.000     15.240      -

cpu0.regs.path_left_data_bm[0]                             ORCALUT4     Z        Out     1.017     15.364      -

cpu0.regs.path_left_data[3]                               PFUMX        Z        Out     0.350     15.590      -

path_left_data_bm[0]                                       Net          -        -       -         -           1

regs_o_left_path_data[3]                                  Net          -        -       -         -           3

cpu0.regs.path_left_data[0]                                PFUMX        ALUT     In      0.000     15.364      -

cpu0.regs.path_left_data_RNIU3J91[3]                      ORCALUT4     A        In      0.000     15.590      -

cpu0.regs.path_left_data[0]                                PFUMX        Z        Out     0.390     15.755      -

cpu0.regs.path_left_data_RNIU3J91[3]                      ORCALUT4     Z        Out     1.265     16.855      -

regs_o_left_path_data[0]                                   Net          -        -       -         -           4

left_1[3]                                                 Net          -        -       -         -           8

cpu0.alu.datamux_o_alu_in_left_path_data[0]                ORCALUT4     A        In      0.000     15.755      -

cpu0.regs.PC_11[3]                                        ORCALUT4     C        In      0.000     16.855      -

cpu0.alu.datamux_o_alu_in_left_path_data[0]                ORCALUT4     Z        Out     1.387     17.142      -

cpu0.regs.PC_11[3]                                        ORCALUT4     Z        Out     1.017     17.872      -

datamux_o_alu_in_left_path_data[0]                         Net          -        -       -         -           43

PC_11[3]                                                  Net          -        -       -         -           1

cpu0.alu.mul16_w_madd_0_cry_0_0                            CCU2D        C1       In      0.000     17.142      -

cpu0.regs.PC_cry_0[2]                                     CCU2D        B1       In      0.000     17.872      -

cpu0.alu.mul16_w_madd_0_cry_0_0                            CCU2D        COUT     Out     1.544     18.686      -

cpu0.regs.PC_cry_0[2]                                     CCU2D        COUT     Out     1.544     19.416      -

mul16_w_madd_0_cry_0                                       Net          -        -       -         -           1

PC_cry[3]                                                 Net          -        -       -         -           1

cpu0.alu.mul16_w_madd_0_cry_1_0                            CCU2D        CIN      In      0.000     18.686      -

cpu0.regs.PC_cry_0[4]                                     CCU2D        CIN      In      0.000     19.416      -

cpu0.alu.mul16_w_madd_0_cry_1_0                            CCU2D        S0       Out     1.621     20.307      -

cpu0.regs.PC_cry_0[4]                                     CCU2D        COUT     Out     0.143     19.559      -

mul16_w_madd_0[2]                                          Net          -        -       -         -           2

PC_cry[5]                                                 Net          -        -       -         -           1

cpu0.alu.mul16_w_madd_4_cry_0_0                            CCU2D        C1       In      0.000     20.307      -

cpu0.regs.PC_cry_0[6]                                     CCU2D        CIN      In      0.000     19.559      -

cpu0.alu.mul16_w_madd_4_cry_0_0                            CCU2D        COUT     Out     1.544     21.852      -

cpu0.regs.PC_cry_0[6]                                     CCU2D        COUT     Out     0.143     19.702      -

mul16_w_madd_4_cry_0                                       Net          -        -       -         -           1

PC_cry[7]                                                 Net          -        -       -         -           1

cpu0.alu.mul16_w_madd_4_cry_1_0                            CCU2D        CIN      In      0.000     21.852      -

cpu0.regs.PC_cry_0[8]                                     CCU2D        CIN      In      0.000     19.702      -

cpu0.alu.mul16_w_madd_4_cry_1_0                            CCU2D        S1       Out     1.621     23.473      -

cpu0.regs.PC_cry_0[8]                                     CCU2D        COUT     Out     0.143     19.845      -

mul16_w_madd                                               Net          -        -       -         -           2

PC_cry[9]                                                 Net          -        -       -         -           1

cpu0.alu.mul16_w_madd_cry_0_0                              CCU2D        A1       In      0.000     23.473      -

cpu0.regs.PC_cry_0[10]                                    CCU2D        CIN      In      0.000     19.845      -

cpu0.alu.mul16_w_madd_cry_0_0                              CCU2D        COUT     Out     1.544     25.017      -

cpu0.regs.PC_cry_0[10]                                    CCU2D        COUT     Out     0.143     19.988      -

mul16_w_madd_cry_0                                         Net          -        -       -         -           1

PC_cry[11]                                                Net          -        -       -         -           1

cpu0.alu.mul16_w_madd_cry_1_0                              CCU2D        CIN      In      0.000     25.017      -

cpu0.regs.PC_cry_0[12]                                    CCU2D        CIN      In      0.000     19.988      -

cpu0.alu.mul16_w_madd_cry_1_0                              CCU2D        COUT     Out     0.143     25.160      -

cpu0.regs.PC_cry_0[12]                                    CCU2D        COUT     Out     0.143     20.130      -

mul16_w_madd_cry_2                                         Net          -        -       -         -           1

PC_cry[13]                                                Net          -        -       -         -           1

cpu0.alu.mul16_w_madd_cry_3_0                              CCU2D        CIN      In      0.000     25.160      -

cpu0.regs.PC_cry_0[14]                                    CCU2D        CIN      In      0.000     20.130      -

cpu0.alu.mul16_w_madd_cry_3_0                              CCU2D        S0       Out     1.621     26.781      -

cpu0.regs.PC_cry_0[14]                                    CCU2D        S1       Out     1.549     21.679      -

mul16_w[7]                                                 Net          -        -       -         -           2

PC_s[15]                                                  Net          -        -       -         -           1

cpu0.alu.q16_20[7]                                         ORCALUT4     A        In      0.000     26.781      -

cpu0.regs.PC[15]                                          FD1P3AX      D        In      0.000     21.679      -

cpu0.alu.q16_20[7]                                         ORCALUT4     Z        Out     1.017     27.798      -

========================================================================================================================

Register bits: 573 of 6864 (8%)

Register bits: 500 of 6864 (7%)

CCU2D:          162

CCU2D:          160

FD1P3AX:        552

FD1P3AX:        484

FD1P3IX:        2

FD1P3IX:        1

INV:            11

INV:            13

L6MUX21:        22

L6MUX21:        31

ORCALUT4:       2177

ORCALUT4:       1933

PFUMX:          315

PFUMX:          308

VHI:            4

VHI:            8

VLO:            10

VLO:            13

true:           6

true:           5

At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 44MB peak: 228MB)

At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 44MB peak: 227MB)

Process took 0h:00m:18s realtime, 0h:00m:18s cputime

Process took 0h:00m:15s realtime, 0h:00m:15s cputime

# Tue Dec 31 08:52:45 2013

# Wed Jan  1 11:05:41 2014

  On or above line 291 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 280 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 299 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 288 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 610 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 10297 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 1405 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 11284 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 1481 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 11361 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 2852 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 12803 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 6393 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 15684 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 18874 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 29797 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 33610 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 32207 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 34028 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 32625 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 38347 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 38016 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 39078 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 38686 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - ngdbuild: DRC complete with 108 warnings

WARNING - ngdbuild: DRC complete with 96 warnings

   3326 blocks expanded

   3018 blocks expanded

WARNING - map: Using local reset signal 'cpu0.cpu_reset_i_2_i' to infer global GSR net.

WARNING - map: Using local reset signal 'cpu0.cpu_reset_i_3_i' to infer global GSR net.

   Number of registers:    573

   Number of registers:    500

      PFU registers:    565

      PFU registers:    492

   Number of SLICEs:          1259 out of  3432 (37%)

   Number of SLICEs:          1135 out of  3432 (33%)

      SLICEs(logic/ROM/RAM):   401 out of  2574 (16%)

      SLICEs(logic/ROM/RAM):   277 out of  2574 (11%)

          As Logic/ROM:    401 out of  2574 (16%)

          As Logic/ROM:    277 out of  2574 (11%)

   Number of logic LUT4s:     2189

   Number of logic LUT4s:     1946

   Number of ripple logic:    162 (324 LUT4s)

   Number of ripple logic:    160 (320 LUT4s)

   Total number of LUT4s:     2513

   Total number of LUT4s:     2266

     Net cpu_clkgen: 374 loads, 374 rising, 0 falling (Driver: PIO clk40_i )

     Net cpu_clkgen: 312 loads, 312 rising, 0 falling (Driver: PIO clk40_i )

     Net cpu_clk: 187 loads, 187 LSLICEs

     Net cpu_clk: 127 loads, 127 LSLICEs

     Net k_cpu_we_RNIKJPB: 8 loads, 0 LSLICEs

     Net leds_r_cnv[0]: 8 loads, 0 LSLICEs

     Net cpu0/k_ealo_0_sqmuxa_RNICERE1: 5 loads, 5 LSLICEs

     Net cpu0/state_9_sqmuxa_RNILUGF3: 3 loads, 3 LSLICEs

     Net cpu0/k_new_pc26_RNICEI54: 3 loads, 3 LSLICEs

     Net cpu0/un1_state_21_RNI2O3K: 4 loads, 4 LSLICEs

     Net cpu0/k_ealo_cnv_0[0]: 13 loads, 13 LSLICEs

     Net cpu0/mode52_3_RNIE4HVB: 4 loads, 4 LSLICEs

     Net cpu0/k_eahi_0_sqmuxa_2_RNIC7377: 4 loads, 4 LSLICEs

     Net cpu0/k_ealo_cnv_0[0]: 16 loads, 16 LSLICEs

     Net cpu0/k_pp_regs55_RNIJTK99: 2 loads, 2 LSLICEs

     Net cpu0/un1_state_77_RNIJP1NM: 2 loads, 2 LSLICEs

     Net cpu0/un1_state_31_RNIDQAP: 4 loads, 4 LSLICEs

     Net cpu0/un1_k_opcode_3_RNIGMC4I: 8 loads, 8 LSLICEs

     Net cpu0/un1_state_28_0_a2_RNIKHLH: 5 loads, 5 LSLICEs

     Net cpu0/k_new_pc27_0_RNI0JKSH: 4 loads, 4 LSLICEs

     Net cpu0/un1_k_opcode_4_RNII2FP8: 8 loads, 8 LSLICEs

     Net cpu0/un1_state_66_RNIVV3L4: 2 loads, 2 LSLICEs

     Net cpu0/k_ofshi_1_sqmuxa_RNI9N8V: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_92_i_o4_RNIGQ812: 4 loads, 4 LSLICEs

     Net cpu0/regs/IY_0_sqmuxa_i_a3_0_RNI01N31: 18 loads, 18 LSLICEs

     Net cpu0/un1_state_18_2_RNITPBJ: 4 loads, 4 LSLICEs

     Net cpu0/regs/IX_0_sqmuxa_1_i_a2_RNIKUBD1: 17 loads, 17 LSLICEs

     Net cpu0/k_cpu_we_3_RNIIAUK: 8 loads, 8 LSLICEs

     Net cpu0/regs/DP_0_sqmuxa_i_a3_0_RNIV3T11: 7 loads, 7 LSLICEs

     Net cpu0/cff_0_sqmuxa_1_RNIICN5: 18 loads, 18 LSLICEs

     Net cpu0/regs/ACCB_0_sqmuxa_1_RNIGOBV: 7 loads, 7 LSLICEs

     Net cpu0/regs/IY_1_sqmuxa_1_1_RNIHDTU1: 25 loads, 25 LSLICEs

     Net cpu0/regs/ACCB45_RNI83PT2: 4 loads, 4 LSLICEs

     Net cpu0/regs/IX_0_sqmuxa_1_1_RNISEKK1: 25 loads, 25 LSLICEs

     Net cpu0/k_memlo_1_sqmuxa_RNIT89Q: 4 loads, 4 LSLICEs

     Net cpu0/regs/DP_1_sqmuxa_0_0_RNIBPP91: 9 loads, 9 LSLICEs

     Net cpu0/next_state_0_sqmuxa_2_0_a2_RNII5VUC1: 3 loads, 3 LSLICEs

     Net cpu0/regs/ACCB_0_sqmuxa_1_RNIHOBV: 9 loads, 9 LSLICEs

     Net cpu0/k_new_pc29_RNIV0H41: 4 loads, 4 LSLICEs

     Net cpu0/regs/un1_exg_dest_r_4_RNIA9G72: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_74_RNIID554: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_74_1_RNIUBKOG: 4 loads, 4 LSLICEs

     Net cpu0/un3_cpu_reset_RNIO5453: 4 loads, 4 LSLICEs

     Net cpu0/state81_RNID4BE4: 2 loads, 2 LSLICEs

     Net cpu0/un3_cpu_reset_RNIT72KK: 4 loads, 4 LSLICEs

     Net cpu0/un3_cpu_reset_RNIGK359: 4 loads, 4 LSLICEs

     Net cpu0/un3_cpu_reset_RNIRKP92: 4 loads, 4 LSLICEs

     Net cpu0/un3_cpu_reset_RNI57TP9: 4 loads, 4 LSLICEs

   Number of local set/reset loads for net cpu0.cpu_reset_i_2_i merged into GSR:  6

     Net cpu0/k_memlo_1_sqmuxa_RNI6AUQ: 4 loads, 4 LSLICEs

   Number of LSRs:  2

     Net cpu0/k_memhi_0_sqmuxa_RNI0T301: 4 loads, 4 LSLICEs

     Net cpu0/state_RNI06PR1[5]: 3 loads, 3 LSLICEs

   Number of local set/reset loads for net cpu0.cpu_reset_i_3_i merged into GSR:  6

     Net cpu0/regs/eflag_RNO_0: 1 loads, 1 LSLICEs

   Number of LSRs:  1

     Net cpu_clk: 211 loads

     Net cpu_clk: 149 loads

     Net cpu0/dec_o_alu_opcode[0]: 192 loads

     Net cpu0/dec_o_alu_opcode[0]: 95 loads

     Net cpu0/dec_o_alu_opcode[2]: 124 loads

     Net state_o_c[1]: 95 loads

     Net cpu0/dec_o_alu_opcode[3]: 104 loads

     Net state_o_c[4]: 77 loads

     Net state_o_c[5]: 76 loads

     Net state_o_c[2]: 73 loads

     Net state_o_c[1]: 75 loads

     Net cpu0/k_opcode[3]: 70 loads

     Net cpu0/dec_o_p1_mode[0]: 68 loads

     Net cpu0/dec_o_p1_mode[2]: 67 loads

     Net state_o_c[4]: 65 loads

     Net state_o_c[0]: 67 loads

     Net state_o_c[0]: 63 loads

     Net cpu0/dec_o_alu_opcode[4]: 66 loads

     Net state_o_c[3]: 61 loads

     Net cpu0/dec_o_p1_mode[0]: 66 loads

Total CPU Time: 1 secs

Total CPU Time: 0 secs

Peak Memory Usage: 195 MB

Peak Memory Usage: 193 MB

Tue Dec 31 08:52:49 2013

Wed Jan  1 11:05:44 2014

Timing errors: 4096  Score: 43964214

Timing errors: 4096  Score: 10215342

Cumulative negative slack: 43964214

Cumulative negative slack: 10215342

Constraints cover 130482274 paths, 1 nets, and 9545 connections (95.7% coverage)

Constraints cover 3952043 paths, 1 nets, and 8655 connections (95.9% coverage)

Tue Dec 31 08:52:49 2013

Wed Jan  1 11:05:44 2014

Constraints cover 130482274 paths, 1 nets, and 9903 connections (99.2% coverage)

Constraints cover 3952043 paths, 1 nets, and 8953 connections (99.2% coverage)

Score: 43964214 (setup), 0 (hold)

Score: 10215342 (setup), 0 (hold)

Cumulative negative slack: 43964214 (43964214+0)

Cumulative negative slack: 10215342 (10215342+0)