Line 14... |
Line 14... |
Running in Lattice mode
|
Running in Lattice mode
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Starting: /usr/local/diamond/2.2_x64/synpbase/linux_a_64/mbin/synbatch
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Starting: /usr/local/diamond/2.2_x64/synpbase/linux_a_64/mbin/synbatch
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Install: /usr/local/diamond/2.2_x64/synpbase
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Install: /usr/local/diamond/2.2_x64/synpbase
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Date: Sun Jan 5 08:22:47 2014
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Date: Mon Jan 6 06:54:11 2014
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Version: G-2012.09L-SP1
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Version: G-2012.09L-SP1
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Arguments: -product synplify_pro -batch P6809_P6809_synplify.tcl
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Arguments: -product synplify_pro -batch P6809_P6809_synplify.tcl
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ProductType: synplify_pro
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ProductType: synplify_pro
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Line 40... |
Line 40... |
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Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/synwork/P6809_P6809_compiler.srs to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srs
|
Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/synwork/P6809_P6809_compiler.srs to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srs
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|
compiler Completed with warnings
|
compiler Completed with warnings
|
Return Code: 1
|
Return Code: 1
|
Run Time:00h:00m:04s
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Run Time:00h:00m:03s
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Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf
|
Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf
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Job Compile Process completed on proj_1|P6809
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Job Compile Process completed on proj_1|P6809
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Line 62... |
Line 62... |
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Running Map & Optimize on proj_1|P6809
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Running Map & Optimize on proj_1|P6809
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fpga_mapper Completed with warnings
|
fpga_mapper Completed with warnings
|
Return Code: 1
|
Return Code: 1
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Run Time:00h:00m:17s
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Run Time:00h:00m:14s
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Job Map completed on proj_1|P6809
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Job Map completed on proj_1|P6809
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Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf
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Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf
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Line 89... |
Line 89... |
#Hostname: node01.pacito.sys
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#Hostname: node01.pacito.sys
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#Implementation: P6809
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#Implementation: P6809
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$ Start of Compile
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$ Start of Compile
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#Sun Jan 5 08:22:47 2014
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#Mon Jan 6 06:54:11 2014
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Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
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Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
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@N|Running in 64-bit mode
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@N|Running in 64-bit mode
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Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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Line 107... |
Line 107... |
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
|
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
|
@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
|
@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
|
@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":698:23:698:27|Specified digits overflow the number's size
|
@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":699:23:699:27|Specified digits overflow the number's size
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
|
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"
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Verilog syntax check successful!
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Verilog syntax check successful!
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File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v changed - recompiling
|
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File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v changed - recompiling
|
File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v changed - recompiling
|
Selecting top level module CC3_top
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Selecting top level module CC3_top
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":57:7:57:10|Synthesizing module alu8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":62:7:62:12|Synthesizing module logic8
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":319:0:319:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:7:85:12|Synthesizing module arith8
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:5:85:12|No assignment to wire cadd16_w
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:15:85:22|No assignment to wire cadc16_w
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:25:85:32|No assignment to wire csub16_w
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":157:7:157:12|Synthesizing module shift8
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:35:85:42|No assignment to wire csbc16_w
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":197:7:197:10|Synthesizing module alu8
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":184:12:184:13|No assignment to n8
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":319:0:319:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
|
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":184:20:184:21|No assignment to z8
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":240:12:240:13|No assignment to n8
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":240:20:240:21|No assignment to z8
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":301:0:301:5|Pruning register regq8[7:0]
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":301:0:301:5|Pruning register regq8[7:0]
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":650:7:650:12|Synthesizing module mul8x8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":603:7:603:12|Synthesizing module mul8x8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":128:7:128:13|Synthesizing module arith16
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":325:7:325:11|Synthesizing module alu16
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":325:7:325:11|Synthesizing module alu16
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":645:0:645:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":411:23:411:29|No assignment to wire arith_h
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":433:12:433:18|No assignment to wire q16_mul
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":561:0:561:5|Pruning register regq16[15:0]
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":517:0:517:5|Pruning register regq16[15:0]
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu
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@W: CS263 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":32:18:32:28|Port-width mismatch for port a_in. Formal has width 16, Actual 8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":191:7:191:13|Synthesizing module calc_ea
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@W: CS263 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":32:30:32:40|Port-width mismatch for port b_in. Formal has width 16, Actual 8
|
|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":243:0:243:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
|
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs
|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":131:7:131:15|Synthesizing module decode_op
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":138:7:138:15|Synthesizing module decode_op
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|
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":259:7:259:15|Synthesizing module decode_ea
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":266:7:266:15|Synthesizing module decode_ea
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|
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":285:7:285:16|Synthesizing module decode_alu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":292:7:292:16|Synthesizing module decode_alu
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|
|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":358:7:358:20|Synthesizing module test_condition
|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":365:7:365:20|Synthesizing module test_condition
|
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|
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
|
|
|
@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":417:6:417:13|Ignoring system task $display
|
@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":418:6:418:13|Ignoring system task $display
|
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1033:0:1033:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
|
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1039:0:1039:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
|
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":64:11:64:23|No assignment to wire alu8_o_result
|
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":64:11:64:23|No assignment to wire alu8_o_result
|
|
|
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":65:11:65:20|No assignment to wire alu8_o_CCR
|
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":65:11:65:20|No assignment to wire alu8_o_CCR
|
|
|
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[0] is always 1, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit k_mem_dest[0] is always 1, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit k_mem_dest[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit next_mem_state[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit next_mem_state[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit next_mem_state[2] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit next_mem_state[2] is always 0, optimizing ...
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
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Line 266... |
Line 264... |
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Pruning register bits 5 to 3 of next_push_state[5:0]
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Pruning register bits 5 to 3 of next_push_state[5:0]
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":362:18:362:20|Input port bits 7 to 4 of CCR[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":369:18:369:20|Input port bits 7 to 4 of CCR[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":287:18:287:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":294:18:294:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":260:18:260:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":267:18:267:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":329:18:329:20|Input port bits 7 to 4 of CCR[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":329:18:329:20|Input port bits 7 to 4 of CCR[7:0] are unused
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":660:0:660:5|Pruning register bits 15 to 13 of pipe0[15:0]
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Pruning register bits 15 to 13 of pipe0[15:0]
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":660:0:660:5|Register bit pipe0[12] is always 0, optimizing ...
|
|
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":660:0:660:5|Pruning register bit 12 of pipe0[12:0]
|
|
|
|
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":59:19:59:22|Input port bits 15 to 8 of a_in[15:0] are unused
|
|
|
|
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":60:19:60:22|Input port bits 15 to 8 of b_in[15:0] are unused
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Register bit pipe0[12] is always 0, optimizing ...
|
|
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Pruning register bit 12 of pipe0[12:0]
|
|
|
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":58:12:58:17|Input clk_in is unused
|
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":198:12:198:17|Input clk_in is unused
|
|
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":159:18:159:21|Input b_in is unused
|
@END
|
@END
|
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
# Sun Jan 5 08:22:49 2014
|
# Mon Jan 6 06:54:13 2014
|
|
|
###########################################################]
|
###########################################################]
|
Premap Report
|
Premap Report
|
|
|
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
|
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
|
Line 304... |
Line 299... |
@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt
|
@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt
|
Printing clock summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt" file
|
Printing clock summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt" file
|
@N: MF248 |Running in 64-bit mode.
|
@N: MF248 |Running in 64-bit mode.
|
@N: MF666 |Clock conversion enabled
|
@N: MF666 |Clock conversion enabled
|
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 95MB)
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)
|
|
|
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 95MB)
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)
|
|
|
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
|
|
|
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 111MB)
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB)
|
|
|
|
|
|
|
Clock Summary
|
Clock Summary
|
**************
|
**************
|
Line 332... |
Line 327... |
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 83 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 83 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
|
|
syn_allowed_resources : blockrams=26 set on top level netlist CC3_top
|
syn_allowed_resources : blockrams=26 set on top level netlist CC3_top
|
Finished Pre Mapping Phase.Pre-mapping successful!
|
Finished Pre Mapping Phase.Pre-mapping successful!
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 136MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 137MB)
|
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
# Sun Jan 5 08:22:51 2014
|
# Mon Jan 6 06:54:14 2014
|
|
|
###########################################################]
|
###########################################################]
|
Map & Optimize Report
|
Map & Optimize Report
|
|
|
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
|
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
|
Line 371... |
Line 366... |
None Found
|
None Found
|
|
|
|
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
|
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Found counter in view:work.regblock(verilog) inst PC[15:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
|
|
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 154MB peak: 157MB)
|
Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 161MB)
|
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
|
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 158MB)
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 163MB)
|
|
|
|
|
|
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 158MB)
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 165MB)
|
|
|
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":237:2:237:3|Pipelining module un1_ea_reg_2[15:0]
|
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":883:11:883:29|Pipelining module un75
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register SU[15:0] pushed in.
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register k_pp_regs[7:0] pushed in.
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register k_ind_ea[7:0] pushed in.
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":143:35:143:85|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register SS[15:0] pushed in.
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":100:35:100:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.a8.q_out_2[8:0] from cpu0.alu.alu8.a8.un26_q_out[8:0]
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register IX[15:0] pushed in.
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":140:35:140:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_1_0[16:0] from cpu0.alu.alu16.a16.un17_q_out[16:0]
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register IY[15:0] pushed in.
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":99:35:99:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.a8.q_out_1_0[8:0] from cpu0.alu.alu8.a8.un17_q_out[8:0]
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":253:2:253:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.k_new_pc_4[15:0] from cpu0.un1_regs_o_pc[15:0]
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":254:2:254:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.ea.k_new_pc_4[15:0] from cpu0.un1_regs_o_pc[15:0]
|
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]
|
|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 158MB)
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 165MB)
|
|
|
|
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 158MB)
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 165MB)
|
|
|
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 158MB)
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 151MB peak: 165MB)
|
|
|
|
|
Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 148MB peak: 158MB)
|
Finished preparing to map (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 151MB peak: 165MB)
|
|
|
|
|
Finished technology mapping (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 197MB peak: 226MB)
|
Finished technology mapping (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 212MB peak: 229MB)
|
|
|
Pass CPU time Worst Slack Luts / Registers
|
Pass CPU time Worst Slack Luts / Registers
|
------------------------------------------------------------
|
------------------------------------------------------------
|
Pass CPU time Worst Slack Luts / Registers
|
Pass CPU time Worst Slack Luts / Registers
|
------------------------------------------------------------
|
------------------------------------------------------------
|
------------------------------------------------------------
|
------------------------------------------------------------
|
|
|
|
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 165MB peak: 226MB)
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 167MB peak: 229MB)
|
|
|
@N: FX164 |The option to pack flops in the IOB has not been specified
|
@N: FX164 |The option to pack flops in the IOB has not been specified
|
|
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 166MB peak: 226MB)
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 169MB peak: 229MB)
|
|
|
|
|
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
|
|
1 non-gated/non-generated clock tree(s) driving 504 clock pin(s) of sequential element(s)
|
1 non-gated/non-generated clock tree(s) driving 455 clock pin(s) of sequential element(s)
|
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
281 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
|
342 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
|
|
|
=========================== Non-Gated/Non-Generated Clocks ============================
|
=========================== Non-Gated/Non-Generated Clocks ============================
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
---------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------
|
@K:CKID0001 clk40_i port 504 cpu_clk
|
@K:CKID0001 clk40_i port 455 cpu_clk
|
=======================================================================================
|
=======================================================================================
|
===== Gated/Generated Clocks =====
|
===== Gated/Generated Clocks =====
|
************** None **************
|
************** None **************
|
----------------------------------
|
----------------------------------
|
==================================
|
==================================
|
Line 455... |
Line 452... |
|
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##### END OF CLOCK OPTIMIZATION REPORT ######]
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##### END OF CLOCK OPTIMIZATION REPORT ######]
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Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srm
|
Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srm
|
|
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 169MB peak: 226MB)
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 172MB peak: 229MB)
|
|
|
Writing EDIF Netlist and constraint files
|
Writing EDIF Netlist and constraint files
|
G-2012.09L-SP1
|
G-2012.09L-SP1
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
|
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 173MB peak: 226MB)
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 176MB peak: 229MB)
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|
|
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"
|
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"
|
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|
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|
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|
##### START OF TIMING REPORT #####[
|
##### START OF TIMING REPORT #####[
|
# Timing Report written on Sun Jan 5 08:23:08 2014
|
# Timing Report written on Mon Jan 6 06:54:29 2014
|
#
|
#
|
|
|
|
|
Top view: CC3_top
|
Top view: CC3_top
|
Requested Frequency: 1.0 MHz
|
Requested Frequency: 1.0 MHz
|
Line 487... |
Line 484... |
|
|
Performance Summary
|
Performance Summary
|
*******************
|
*******************
|
|
|
|
|
Worst slack in design: 979.333
|
Worst slack in design: 978.474
|
|
|
Requested Estimated Requested Estimated Clock Clock
|
Requested Estimated Requested Estimated Clock Clock
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
------------------------------------------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------------------------------------------
|
CC3_top|clk40_i 1.0 MHz 48.4 MHz 1000.000 20.667 979.333 inferred Inferred_clkgroup_0
|
CC3_top|clk40_i 1.0 MHz 46.5 MHz 1000.000 21.526 978.474 inferred Inferred_clkgroup_0
|
========================================================================================================================
|
========================================================================================================================
|
|
|
|
|
|
|
|
|
Line 506... |
Line 503... |
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
--------------------------------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------------------------------
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
--------------------------------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------------------------------
|
CC3_top|clk40_i CC3_top|clk40_i | 1000.000 979.333 | No paths - | No paths - | No paths -
|
CC3_top|clk40_i CC3_top|clk40_i | 1000.000 978.474 | No paths - | No paths - | No paths -
|
==========================================================================================================================
|
==========================================================================================================================
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
|
|
|
|
Line 532... |
Line 529... |
********************************
|
********************************
|
|
|
Starting Arrival
|
Starting Arrival
|
Instance Reference Type Pin Net Time Slack
|
Instance Reference Type Pin Net Time Slack
|
Clock
|
Clock
|
-----------------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------
|
cpu0.regs.SU_pipe_21 CC3_top|clk40_i FD1P3AX Q un1_ea_reg_sn_N_3f 1.268 979.333
|
cpu0.alu.rb_in[0] CC3_top|clk40_i FD1P3AX Q rb_in[0] 1.302 978.474
|
cpu0.regs.SS_pipe_20 CC3_top|clk40_i FD1P3AX Q SS_pipe_20 1.268 979.397
|
cpu0.alu.rb_in[1] CC3_top|clk40_i FD1P3AX Q rb_in[1] 1.302 978.617
|
cpu0.regs.SU_pipe_19 CC3_top|clk40_i FD1P3AX Q SU_pipe_19 1.044 979.557
|
cpu0.alu.rb_in[2] CC3_top|clk40_i FD1P3AX Q rb_in[2] 1.292 978.627
|
cpu0.regs.SU_pipe_20 CC3_top|clk40_i FD1P3AX Q SU_pipe_20 1.044 979.557
|
cpu0.alu.rb_in[3] CC3_top|clk40_i FD1P3AX Q rb_in[3] 1.296 978.766
|
cpu0.k_opcode[1] CC3_top|clk40_i FD1P3AX Q k_opcode[1] 1.387 979.562
|
cpu0.alu.rb_in[4] CC3_top|clk40_i FD1P3AX Q rb_in[4] 1.292 978.770
|
cpu0.k_opcode[0] CC3_top|clk40_i FD1P3AX Q k_opcode[0] 1.358 979.591
|
cpu0.alu.ra_in[0] CC3_top|clk40_i FD1P3AX Q ra_in[0] 1.305 979.039
|
cpu0.regs.SS_pipe_18 CC3_top|clk40_i FD1P3AX Q un1_SS_m1f[0] 1.044 979.621
|
cpu0.alu.ra_in[1] CC3_top|clk40_i FD1P3AX Q ra_in[1] 1.309 979.178
|
cpu0.regs.SS_pipe_19 CC3_top|clk40_i FD1P3AX Q un1_SS_m0f[0] 1.044 979.621
|
cpu0.alu.ra_in[2] CC3_top|clk40_i FD1P3AX Q ra_in[2] 1.309 979.178
|
cpu0.regs.SS_pipe_21 CC3_top|clk40_i FD1P3AX Q un1_SS_m1f[1] 0.972 979.908
|
cpu0.alu.ra_in[3] CC3_top|clk40_i FD1P3AX Q ra_in[3] 1.305 979.324
|
cpu0.regs.SS_pipe_22 CC3_top|clk40_i FD1P3AX Q un1_SS_m0f[1] 0.972 979.908
|
cpu0.alu.ra_in[4] CC3_top|clk40_i FD1P3AX Q ra_in[4] 1.292 979.338
|
===========================================================================================================
|
==============================================================================================
|
|
|
|
|
Ending Points with Worst Slack
|
Ending Points with Worst Slack
|
******************************
|
******************************
|
|
|
Starting Required
|
Starting Required
|
Instance Reference Type Pin Net Time Slack
|
Instance Reference Type Pin Net Time Slack
|
Clock
|
Clock
|
----------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------
|
cpu0.regs.PC[14] CC3_top|clk40_i FD1P3AX D PC_s[14] 999.894 979.333
|
cpu0.regs.SS[14] CC3_top|clk40_i FD1P3AX D SS_s[14] 999.894 978.474
|
cpu0.regs.PC[15] CC3_top|clk40_i FD1P3AX D PC_s[15] 999.894 979.333
|
cpu0.regs.SS[15] CC3_top|clk40_i FD1P3AX D SS_s[15] 999.894 978.474
|
cpu0.regs.PC[12] CC3_top|clk40_i FD1P3AX D PC_s[12] 999.894 979.476
|
cpu0.regs.SU[14] CC3_top|clk40_i FD1P3AX D SU_s[14] 999.894 978.474
|
cpu0.regs.PC[13] CC3_top|clk40_i FD1P3AX D PC_s[13] 999.894 979.476
|
cpu0.regs.SU[15] CC3_top|clk40_i FD1P3AX D SU_s[15] 999.894 978.474
|
cpu0.regs.PC[10] CC3_top|clk40_i FD1P3AX D PC_s[10] 999.894 979.619
|
cpu0.regs.SS[12] CC3_top|clk40_i FD1P3AX D SS_s[12] 999.894 978.617
|
cpu0.regs.PC[11] CC3_top|clk40_i FD1P3AX D PC_s[11] 999.894 979.619
|
cpu0.regs.SS[13] CC3_top|clk40_i FD1P3AX D SS_s[13] 999.894 978.617
|
cpu0.regs.PC[8] CC3_top|clk40_i FD1P3AX D PC_s[8] 999.894 979.794
|
cpu0.regs.SU[12] CC3_top|clk40_i FD1P3AX D SU_s[12] 999.894 978.617
|
cpu0.regs.PC[9] CC3_top|clk40_i FD1P3AX D PC_s[9] 999.894 979.794
|
cpu0.regs.SU[13] CC3_top|clk40_i FD1P3AX D SU_s[13] 999.894 978.617
|
cpu0.regs.PC[6] CC3_top|clk40_i FD1P3AX D PC_s[6] 999.894 979.937
|
cpu0.regs.SS[10] CC3_top|clk40_i FD1P3AX D SS_s[10] 999.894 978.760
|
cpu0.regs.PC[7] CC3_top|clk40_i FD1P3AX D PC_s[7] 999.894 979.937
|
cpu0.regs.SS[11] CC3_top|clk40_i FD1P3AX D SS_s[11] 999.894 978.760
|
==============================================================================================
|
==============================================================================================
|
|
|
|
|
|
|
Worst Path Information
|
Worst Path Information
|
Line 577... |
Line 574... |
Requested Period: 1000.000
|
Requested Period: 1000.000
|
- Setup time: 0.106
|
- Setup time: 0.106
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 999.894
|
= Required time: 999.894
|
|
|
- Propagation time: 20.561
|
- Propagation time: 21.420
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : 979.333
|
= Slack (critical) : 978.474
|
|
|
Number of logic level(s): 21
|
Number of logic level(s): 23
|
Starting point: cpu0.regs.SU_pipe_21 / Q
|
Starting point: cpu0.alu.rb_in[0] / Q
|
Ending point: cpu0.regs.PC[15] / D
|
Ending point: cpu0.regs.SS[15] / D
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
-------------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------------
|
cpu0.regs.SU_pipe_21 FD1P3AX Q Out 1.268 1.268 -
|
cpu0.alu.rb_in[0] FD1P3AX Q Out 1.302 1.302 -
|
un1_ea_reg_sn_N_3f Net - - - - 17
|
rb_in[0] Net - - - - 26
|
cpu0.regs.un1_ea_reg[0] ORCALUT4 C In 0.000 1.268 -
|
cpu0.alu.alu8.a8.un8_q_out_cry_0_0_RNO INV A In 0.000 1.302 -
|
cpu0.regs.un1_ea_reg[0] ORCALUT4 Z Out 1.153 2.421 -
|
cpu0.alu.alu8.a8.un8_q_out_cry_0_0_RNO INV Z Out 0.568 1.870 -
|
N_289 Net - - - - 3
|
rb_in_i[0] Net - - - - 1
|
cpu0.regs.un1_ea_reg_2_cry_0_0 CCU2D B1 In 0.000 2.421 -
|
cpu0.alu.alu8.a8.un8_q_out_cry_0_0 CCU2D A1 In 0.000 1.870 -
|
cpu0.regs.un1_ea_reg_2_cry_0_0 CCU2D COUT Out 1.544 3.965 -
|
cpu0.alu.alu8.a8.un8_q_out_cry_0_0 CCU2D COUT Out 1.544 3.415 -
|
un1_ea_reg_2_cry_0 Net - - - - 1
|
un8_q_out_cry_0 Net - - - - 1
|
cpu0.regs.un1_ea_reg_2_cry_1_0 CCU2D CIN In 0.000 3.965 -
|
cpu0.alu.alu8.a8.un8_q_out_cry_1_0 CCU2D CIN In 0.000 3.415 -
|
cpu0.regs.un1_ea_reg_2_cry_1_0 CCU2D S1 Out 1.765 5.730 -
|
cpu0.alu.alu8.a8.un8_q_out_cry_1_0 CCU2D S1 Out 1.549 4.964 -
|
SU[2] Net - - - - 6
|
un8_q_out[2] Net - - - - 1
|
cpu0.regs.ea_reg_3_am[2] ORCALUT4 C In 0.000 5.730 -
|
cpu0.alu.alu8.a8.q_out_2_cry_1_0_RNO_0 ORCALUT4 A In 0.000 4.964 -
|
cpu0.regs.ea_reg_3_am[2] ORCALUT4 Z Out 1.017 6.747 -
|
cpu0.alu.alu8.a8.q_out_2_cry_1_0_RNO_0 ORCALUT4 Z Out 1.017 5.981 -
|
ea_reg_3_am[2] Net - - - - 1
|
q_out_2_cry_1_0_RNO_0 Net - - - - 1
|
cpu0.regs.ea_reg_3[2] PFUMX BLUT In 0.000 6.747 -
|
cpu0.alu.alu8.a8.q_out_2_cry_1_0 CCU2D C1 In 0.000 5.981 -
|
cpu0.regs.ea_reg_3[2] PFUMX Z Out 0.390 7.137 -
|
cpu0.alu.alu8.a8.q_out_2_cry_1_0 CCU2D COUT Out 1.544 7.525 -
|
ea_reg[2] Net - - - - 4
|
q_out_2_cry_2 Net - - - - 1
|
cpu0.regs.un1_PC_1_0[2] ORCALUT4 A In 0.000 7.137 -
|
cpu0.alu.alu8.a8.q_out_2_cry_3_0 CCU2D CIN In 0.000 7.525 -
|
cpu0.regs.un1_PC_1_0[2] ORCALUT4 Z Out 1.017 8.154 -
|
cpu0.alu.alu8.a8.q_out_2_cry_3_0 CCU2D COUT Out 0.143 7.668 -
|
N_506 Net - - - - 1
|
q_out_2_cry_4 Net - - - - 1
|
cpu0.regs.eamem_addr_cry_1_0 CCU2D C1 In 0.000 8.154 -
|
cpu0.alu.alu8.a8.q_out_2_cry_5_0 CCU2D CIN In 0.000 7.668 -
|
cpu0.regs.eamem_addr_cry_1_0 CCU2D COUT Out 1.544 9.698 -
|
cpu0.alu.alu8.a8.q_out_2_cry_5_0 CCU2D COUT Out 0.143 7.811 -
|
eamem_addr_cry_2 Net - - - - 1
|
q_out_2_cry_6 Net - - - - 1
|
cpu0.regs.eamem_addr_cry_3_0 CCU2D CIN In 0.000 9.698 -
|
cpu0.alu.alu8.a8.q_out_2_cry_7_0 CCU2D CIN In 0.000 7.811 -
|
cpu0.regs.eamem_addr_cry_3_0 CCU2D COUT Out 0.143 9.841 -
|
cpu0.alu.alu8.a8.q_out_2_cry_7_0 CCU2D S0 Out 1.549 9.360 -
|
eamem_addr_cry_4 Net - - - - 1
|
N_2388 Net - - - - 1
|
cpu0.regs.eamem_addr_cry_5_0 CCU2D CIN In 0.000 9.841 -
|
cpu0.alu.alu8.a8.q_out_3[7] ORCALUT4 A In 0.000 9.360 -
|
cpu0.regs.eamem_addr_cry_5_0 CCU2D COUT Out 0.143 9.984 -
|
cpu0.alu.alu8.a8.q_out_3[7] ORCALUT4 Z Out 1.089 10.448 -
|
eamem_addr_cry_6 Net - - - - 1
|
arith_q[7] Net - - - - 2
|
cpu0.regs.eamem_addr_cry_7_0 CCU2D CIN In 0.000 9.984 -
|
cpu0.alu.alu8.q_out_4_am[7] ORCALUT4 A In 0.000 10.448 -
|
cpu0.regs.eamem_addr_cry_7_0 CCU2D COUT Out 0.143 10.127 -
|
cpu0.alu.alu8.q_out_4_am[7] ORCALUT4 Z Out 1.017 11.465 -
|
eamem_addr_cry_8 Net - - - - 1
|
q_out_4_am[7] Net - - - - 1
|
cpu0.regs.eamem_addr_cry_9_0 CCU2D CIN In 0.000 10.127 -
|
cpu0.alu.alu8.q_out_4[7] PFUMX BLUT In 0.000 11.465 -
|
cpu0.regs.eamem_addr_cry_9_0 CCU2D S0 Out 1.685 11.812 -
|
cpu0.alu.alu8.q_out_4[7] PFUMX Z Out 0.286 11.751 -
|
regs_o_eamem_addr[9] Net - - - - 3
|
N_160 Net - - - - 2
|
cpu0.regs.eamem_addr_cry_9_0_RNISAU9 ORCALUT4 A In 0.000 11.812 -
|
cpu0.alu.alu8.q_out_5_RNIRSTD1[7] ORCALUT4 A In 0.000 11.751 -
|
cpu0.regs.eamem_addr_cry_9_0_RNISAU9 ORCALUT4 Z Out 1.089 12.901 -
|
cpu0.alu.alu8.q_out_5_RNIRSTD1[7] ORCALUT4 Z Out 1.089 12.840 -
|
datamux_o_dest_6[9] Net - - - - 2
|
q8_out[7] Net - - - - 2
|
cpu0.regs.k_new_pc_1[9] ORCALUT4 A In 0.000 12.901 -
|
cpu0.alu.q_out[7] ORCALUT4 A In 0.000 12.840 -
|
cpu0.regs.k_new_pc_1[9] ORCALUT4 Z Out 1.017 13.917 -
|
cpu0.alu.q_out[7] ORCALUT4 Z Out 0.449 13.289 -
|
N_953 Net - - - - 1
|
alu_o_result[7] Net - - - - 1
|
cpu0.regs.k_new_pc_2[9] ORCALUT4 A In 0.000 13.917 -
|
cpu0.alu.alu8.l8.datamux_o_dest[7] PFUMX ALUT In 0.000 13.289 -
|
cpu0.regs.k_new_pc_2[9] ORCALUT4 Z Out 1.017 14.934 -
|
cpu0.alu.alu8.l8.datamux_o_dest[7] PFUMX Z Out 0.286 13.575 -
|
N_969 Net - - - - 1
|
datamux_o_dest[7] Net - - - - 2
|
cpu0.regs.k_new_pc_5[9] ORCALUT4 A In 0.000 14.934 -
|
cpu0.regs.path_left_data_RNIOEVA1[7] ORCALUT4 B In 0.000 13.575 -
|
cpu0.regs.k_new_pc_5[9] ORCALUT4 Z Out 1.017 15.951 -
|
cpu0.regs.path_left_data_RNIOEVA1[7] ORCALUT4 Z Out 1.273 14.848 -
|
k_new_pc[9] Net - - - - 1
|
left_1[7] Net - - - - 9
|
cpu0.regs.PC_11_am[9] ORCALUT4 A In 0.000 15.951 -
|
cpu0.regs.SS_16_0[7] ORCALUT4 B In 0.000 14.848 -
|
cpu0.regs.PC_11_am[9] ORCALUT4 Z Out 1.017 16.968 -
|
cpu0.regs.SS_16_0[7] ORCALUT4 Z Out 1.017 15.865 -
|
PC_11_am[9] Net - - - - 1
|
N_250 Net - - - - 1
|
cpu0.regs.PC_11[9] PFUMX BLUT In 0.000 16.968 -
|
cpu0.regs.SS_16[7] ORCALUT4 A In 0.000 15.865 -
|
cpu0.regs.PC_11[9] PFUMX Z Out 0.214 17.182 -
|
cpu0.regs.SS_16[7] ORCALUT4 Z Out 1.017 16.882 -
|
PC_11[9] Net - - - - 1
|
SS_16[7] Net - - - - 1
|
cpu0.regs.PC_cry_0[8] CCU2D B1 In 0.000 17.182 -
|
cpu0.regs.SS_228_m3 ORCALUT4 B In 0.000 16.882 -
|
cpu0.regs.PC_cry_0[8] CCU2D COUT Out 1.544 18.727 -
|
cpu0.regs.SS_228_m3 ORCALUT4 Z Out 1.017 17.898 -
|
PC_cry[9] Net - - - - 1
|
SS_228_i1_mux Net - - - - 1
|
cpu0.regs.PC_cry_0[10] CCU2D CIN In 0.000 18.727 -
|
cpu0.regs.SS_cry_0[6] CCU2D C1 In 0.000 17.898 -
|
cpu0.regs.PC_cry_0[10] CCU2D COUT Out 0.143 18.869 -
|
cpu0.regs.SS_cry_0[6] CCU2D COUT Out 1.544 19.443 -
|
PC_cry[11] Net - - - - 1
|
SS_cry[7] Net - - - - 1
|
cpu0.regs.PC_cry_0[12] CCU2D CIN In 0.000 18.869 -
|
cpu0.regs.SS_cry_0[8] CCU2D CIN In 0.000 19.443 -
|
cpu0.regs.PC_cry_0[12] CCU2D COUT Out 0.143 19.012 -
|
cpu0.regs.SS_cry_0[8] CCU2D COUT Out 0.143 19.586 -
|
PC_cry[13] Net - - - - 1
|
SS_cry[9] Net - - - - 1
|
cpu0.regs.PC_cry_0[14] CCU2D CIN In 0.000 19.012 -
|
cpu0.regs.SS_cry_0[10] CCU2D CIN In 0.000 19.586 -
|
cpu0.regs.PC_cry_0[14] CCU2D S1 Out 1.549 20.561 -
|
cpu0.regs.SS_cry_0[10] CCU2D COUT Out 0.143 19.729 -
|
PC_s[15] Net - - - - 1
|
SS_cry[11] Net - - - - 1
|
cpu0.regs.PC[15] FD1P3AX D In 0.000 20.561 -
|
cpu0.regs.SS_cry_0[12] CCU2D CIN In 0.000 19.729 -
|
=======================================================================================================
|
cpu0.regs.SS_cry_0[12] CCU2D COUT Out 0.143 19.871 -
|
|
SS_cry[13] Net - - - - 1
|
|
cpu0.regs.SS_cry_0[14] CCU2D CIN In 0.000 19.871 -
|
|
cpu0.regs.SS_cry_0[14] CCU2D S1 Out 1.549 21.420 -
|
|
SS_s[15] Net - - - - 1
|
|
cpu0.regs.SS[15] FD1P3AX D In 0.000 21.420 -
|
|
=========================================================================================================
|
|
|
|
|
|
|
##### END OF TIMING REPORT #####]
|
##### END OF TIMING REPORT #####]
|
|
|
---------------------------------------
|
---------------------------------------
|
Resource Usage Report
|
Resource Usage Report
|
Part: lcmxo2_7000he-4
|
Part: lcmxo2_7000he-4
|
|
|
Register bits: 488 of 6864 (7%)
|
Register bits: 439 of 6864 (6%)
|
PIC Latch: 0
|
PIC Latch: 0
|
I/O cells: 49
|
I/O cells: 49
|
Block Rams : 10 of 26 (38%)
|
Block Rams : 10 of 26 (38%)
|
|
|
|
|
Details:
|
Details:
|
CCU2D: 196
|
CCU2D: 196
|
DP8KC: 10
|
DP8KC: 10
|
FD1P3AX: 441
|
FD1P3AX: 393
|
FD1P3DX: 6
|
FD1P3DX: 6
|
FD1P3IX: 1
|
|
FD1S3AX: 28
|
FD1S3AX: 28
|
FD1S3IX: 2
|
FD1S3IX: 2
|
GSR: 1
|
GSR: 1
|
IB: 1
|
IB: 1
|
INV: 20
|
INV: 19
|
L6MUX21: 37
|
L6MUX21: 26
|
OB: 40
|
OB: 40
|
OBZ: 8
|
OBZ: 8
|
OFS1P3DX: 9
|
OFS1P3DX: 9
|
OFS1P3IX: 1
|
OFS1P3IX: 1
|
ORCALUT4: 2025
|
ORCALUT4: 2024
|
PFUMX: 273
|
PFUMX: 222
|
PUR: 1
|
PUR: 1
|
VHI: 10
|
VHI: 13
|
VLO: 16
|
VLO: 20
|
true: 6
|
false: 1
|
|
true: 8
|
Mapper successful!
|
Mapper successful!
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 43MB peak: 226MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 44MB peak: 229MB)
|
|
|
Process took 0h:00m:16s realtime, 0h:00m:16s cputime
|
Process took 0h:00m:14s realtime, 0h:00m:14s cputime
|
# Sun Jan 5 08:23:08 2014
|
# Mon Jan 6 06:54:29 2014
|
|
|
###########################################################]
|
###########################################################]
|
|
|
|
|
Synthesis exit by 0.
|
Synthesis exit by 0.
|
Line 715... |
Line 718... |
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
|
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
|
WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...
|
WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...
|
On or above line 310 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 299 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...
|
WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...
|
On or above line 318 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 307 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
|
On or above line 1762 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
|
On or above line 3985 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 1832 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 4141 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 4556 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 5267 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 9109 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 5492 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 9904 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 9169 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 10621 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 10988 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 10919 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 13438 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 11654 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 14340 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 12094 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 15057 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 13053 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 15354 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 15901 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 16157 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 28685 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 16308 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 31454 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 18673 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 34211 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 22261 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 34629 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 32987 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 40141 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 35566 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
On or above line 40954 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
On or above line 38271 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
|
On or above line 38689 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
|
On or above line 42846 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
|
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
|
|
On or above line 43639 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
|
|
|
Writing the design to P6809_P6809.ngo...
|
Writing the design to P6809_P6809.ngo...
|
|
|
|
|
ngdbuild -a "MachXO2" -d LCMXO2-7000HE -p "/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data" -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice" "P6809_P6809.ngo" "P6809_P6809.ngd"
|
ngdbuild -a "MachXO2" -d LCMXO2-7000HE -p "/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data" -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice" "P6809_P6809.ngo" "P6809_P6809.ngd"
|
Line 788... |
Line 806... |
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/or5g00/data/orc5glib.ngl'...
|
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/or5g00/data/orc5glib.ngl'...
|
|
|
|
|
Running DRC...
|
Running DRC...
|
|
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_15_0_COUT' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S0_0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S1_0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_15_0_COUT' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_0_0_S0_0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_0_0_S1_0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_2_cry_15_0_COUT' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_2_cry_0_0_S0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_0_cry_15_0_COUT' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_0_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_COUT' has no load
|
Line 809... |
Line 837... |
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sbc16_w_cry_15_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un8_q_out_cry_7_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sbc16_w_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un8_q_out_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sub16_w_cry_15_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un8_q_out_cry_0_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sub16_w_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_cry_7_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sub16_w_cry_0_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/add16_w_cry_15_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_cry_0_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/add16_w_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_2_cry_7_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/add16_w_cry_0_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_2_cry_0_0_S0_0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_s_15_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_0_cry_7_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_s_15_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_0_cry_0_S0_0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_13_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_s_15_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_13_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_s_15_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_11_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_11_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_cry_0_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_9_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_s_15_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_9_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_s_15_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_7_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_7_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_cry_0_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_5_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/ea/k_new_pc_4_s_15_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_5_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/ea/k_new_pc_4_s_15_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_3_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/ea/k_new_pc_4_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_3_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/ea/k_new_pc_4_cry_0_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_1_0_S0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_1_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_0_0_S0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_0_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sub8_w_cry_7_0_COUT' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sub8_w_cry_0_0_S0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sub8_w_cry_0_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sbc8_w_cry_7_0_COUT' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sbc8_w_cry_0_0_S0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/add8_w_cry_7_0_COUT' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/add8_w_cry_0_0_S0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/add8_w_cry_0_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_s_7_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/SU_cry_0_COUT[14]' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_s_7_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/SU_lcry_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_5_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/SU_lcry_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_5_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/SS_cry_0_COUT[14]' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_3_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/SS_lcry_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_3_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/SS_lcry_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_1_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/right_s_15_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_1_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/right_s_15_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/regs/right_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_0_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_s_15_0_COUT' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_s_15_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_cry_0_0_S0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_cry_0_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_s_15_0_COUT' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_s_15_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_cry_0_0_S0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_cry_0_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_s_15_0_COUT' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_s_15_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_cry_0_0_S0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_cry_0_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_s_15_0_COUT' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_s_15_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_cry_0_0_S0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_cry_0_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_s_15_0_COUT' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_s_15_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_cry_0_0_S0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_cry_0_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/PC_cry_0_COUT[14]' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/PC_lcry_0_S0' has no load
|
|
WARNING - ngdbuild: logical net 'cpu0/regs/PC_lcry_0_S1' has no load
|
|
WARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_S1' has no load
|
WARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_S1' has no load
|
WARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S0' has no load
|
WARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S0' has no load
|
WARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S1' has no load
|
WARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S1' has no load
|
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_7_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_7_0_COUT' has no load
|
Line 905... |
Line 897... |
WARNING - ngdbuild: logical net 'textctrl/hsync_cnt_cry_0_S0[0]' has no load
|
WARNING - ngdbuild: logical net 'textctrl/hsync_cnt_cry_0_S0[0]' has no load
|
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_COUT' has no load
|
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S0' has no load
|
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S1' has no load
|
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S1' has no load
|
WARNING - ngdbuild: DRC complete with 117 warnings
|
WARNING - ngdbuild: DRC complete with 91 warnings
|
|
|
Design Results:
|
Design Results:
|
3125 blocks expanded
|
3019 blocks expanded
|
complete the first expansion
|
complete the first expansion
|
Writing 'P6809_P6809.ngd' ...
|
Writing 'P6809_P6809.ngd' ...
|
|
|
map -a "MachXO2" -p LCMXO2-7000HE -t TQFP144 -s 4 -oc Commercial "P6809_P6809.ngd" -o "P6809_P6809_map.ncd" -pr "P6809_P6809.prf" -mp "P6809_P6809.mrp" "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809.lpf" -c 0
|
map -a "MachXO2" -p LCMXO2-7000HE -t TQFP144 -s 4 -oc Commercial "P6809_P6809.ngd" -o "P6809_P6809_map.ncd" -pr "P6809_P6809.prf" -mp "P6809_P6809.mrp" "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809.lpf" -c 0
|
map: version Diamond (64-bit) 2.2.0.101
|
map: version Diamond (64-bit) 2.2.0.101
|
Line 938... |
Line 930... |
Package Status: Final Version 1.36
|
Package Status: Final Version 1.36
|
|
|
Running general design DRC...
|
Running general design DRC...
|
Removing unused logic...
|
Removing unused logic...
|
Optimizing...
|
Optimizing...
|
7 CCU2 constant inputs absorbed.
|
5 CCU2 constant inputs absorbed.
|
WARNING - map: Using local reset signal 'reset_o_c' to infer global GSR net.
|
WARNING - map: Using local reset signal 'reset_o_c' to infer global GSR net.
|
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_0_3' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
|
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_0_3' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
|
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_1_2' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
|
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_1_2' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
|
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_2_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
|
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_2_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
|
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_3_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
|
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_3_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
|
Line 954... |
Line 946... |
WARNING - map: The reset of EBR 'bios/bios2k_0_0_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
|
WARNING - map: The reset of EBR 'bios/bios2k_0_0_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
|
|
|
|
|
|
|
Design Summary:
|
Design Summary:
|
Number of registers: 488
|
Number of registers: 439
|
PFU registers: 478
|
PFU registers: 429
|
PIO registers: 10
|
PIO registers: 10
|
Number of SLICEs: 1219 out of 3432 (36%)
|
Number of SLICEs: 1218 out of 3432 (35%)
|
SLICEs(logic/ROM): 858 out of 858 (100%)
|
SLICEs(logic/ROM): 858 out of 858 (100%)
|
SLICEs(logic/ROM/RAM): 361 out of 2574 (14%)
|
SLICEs(logic/ROM/RAM): 360 out of 2574 (14%)
|
As RAM: 0 out of 2574 (0%)
|
As RAM: 0 out of 2574 (0%)
|
As Logic/ROM: 361 out of 2574 (14%)
|
As Logic/ROM: 360 out of 2574 (14%)
|
Number of logic LUT4s: 2044
|
Number of logic LUT4s: 2043
|
Number of distributed RAM: 0 (0 LUT4s)
|
Number of distributed RAM: 0 (0 LUT4s)
|
Number of ripple logic: 196 (392 LUT4s)
|
Number of ripple logic: 196 (392 LUT4s)
|
Number of shift registers: 0
|
Number of shift registers: 0
|
Total number of LUT4s: 2436
|
Total number of LUT4s: 2435
|
Number of PIO sites used: 49 + 4(JTAG) out of 115 (46%)
|
Number of PIO sites used: 49 + 4(JTAG) out of 115 (46%)
|
Number of block RAMs: 10 out of 26 (38%)
|
Number of block RAMs: 10 out of 26 (38%)
|
Number of GSRs: 1 out of 1 (100%)
|
Number of GSRs: 1 out of 1 (100%)
|
EFB used : No
|
EFB used : No
|
JTAG used : No
|
JTAG used : No
|
Line 991... |
Line 983... |
Number of ECLKBRIDGECS: 0 out of 2 (0%)
|
Number of ECLKBRIDGECS: 0 out of 2 (0%)
|
Notes:-
|
Notes:-
|
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
|
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
|
2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
|
2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
|
Number of clocks: 1
|
Number of clocks: 1
|
Net cpu_clkgen: 305 loads, 305 rising, 0 falling (Driver: PIO clk40_i )
|
Net cpu_clkgen: 290 loads, 290 rising, 0 falling (Driver: PIO clk40_i )
|
Number of Clock Enables: 35
|
Number of Clock Enables: 36
|
Net cpu_clk: 97 loads, 97 LSLICEs
|
Net cpu_clk: 80 loads, 80 LSLICEs
|
Net leds_r_cnv[0]: 8 loads, 0 LSLICEs
|
Net k_cpu_we_RNIKJPB: 8 loads, 0 LSLICEs
|
Net textctrl/un1_CPU_OE_EN_0_a2: 8 loads, 0 LSLICEs
|
Net textctrl/un1_CPU_OE_EN_0_a2: 8 loads, 0 LSLICEs
|
Net textctrl/line_cnte: 2 loads, 2 LSLICEs
|
Net textctrl/line_cnte: 2 loads, 2 LSLICEs
|
|
Net textctrl/tshift_1_sqmuxa: 4 loads, 4 LSLICEs
|
|
Net textctrl/N_103_i: 4 loads, 4 LSLICEs
|
Net textctrl/y_cnte: 4 loads, 4 LSLICEs
|
Net textctrl/y_cnte: 4 loads, 4 LSLICEs
|
Net textctrl/x_cnte: 4 loads, 4 LSLICEs
|
Net textctrl/x_cnte: 4 loads, 4 LSLICEs
|
Net textctrl/N_4: 6 loads, 6 LSLICEs
|
Net textctrl/N_4: 6 loads, 6 LSLICEs
|
Net textctrl/tshift_1_sqmuxa: 4 loads, 4 LSLICEs
|
|
Net textctrl/N_103_i_0: 4 loads, 4 LSLICEs
|
|
Net textctrl/vsync_cnt_0_sqmuxa_4: 4 loads, 4 LSLICEs
|
Net textctrl/vsync_cnt_0_sqmuxa_4: 4 loads, 4 LSLICEs
|
Net un1_bios_en_0_a2: 4 loads, 0 LSLICEs
|
Net un1_bios_en_0_a2: 4 loads, 0 LSLICEs
|
Net cpu0/un1_state_23_RNIKLF8L: 3 loads, 3 LSLICEs
|
Net cpu0/k_mul_cnt_RNI6QASC: 3 loads, 3 LSLICEs
|
Net cpu0/un1_state_53_RNIKL6IT: 4 loads, 4 LSLICEs
|
|
Net cpu0/k_memhi_0_sqmuxa_RNIS2L63: 4 loads, 4 LSLICEs
|
|
Net cpu0/k_ealo_cnv_0[0]: 16 loads, 16 LSLICEs
|
Net cpu0/k_ealo_cnv_0[0]: 16 loads, 16 LSLICEs
|
Net cpu0/un1_state_12_1_RNIGGP7P: 4 loads, 4 LSLICEs
|
Net cpu0/k_cpu_we_3_RNI4P5E: 8 loads, 8 LSLICEs
|
Net cpu0/un1_cpu_reset_6_0_a3_1_RNI3DL77: 3 loads, 3 LSLICEs
|
Net cpu0/k_memhi_0_sqmuxa_RNIGVP52: 4 loads, 4 LSLICEs
|
Net cpu0/next_state10_RNIVT0PU: 2 loads, 2 LSLICEs
|
Net cpu0/mode53_0_RNIULGBO: 3 loads, 3 LSLICEs
|
Net cpu0/un1_dest_reg44_1_0_a2_1_0_RNIUSPTD1: 8 loads, 8 LSLICEs
|
Net cpu0/k_eahi_0_sqmuxa_2_RNI9C57A: 4 loads, 4 LSLICEs
|
Net cpu0/un1_cpu_reset_5_0_a3_2_RNIUKBUL: 2 loads, 2 LSLICEs
|
Net cpu0/un1_state_82_1_RNI3MDV1: 4 loads, 4 LSLICEs
|
Net cpu0/un1_state_82_1_RNICEGM2: 4 loads, 4 LSLICEs
|
Net cpu0/un1_state_100_i_o4_RNI60VG1: 4 loads, 4 LSLICEs
|
Net cpu0/un1_cpu_reset_10_0_a3_0_0_RNIDMV84: 2 loads, 2 LSLICEs
|
Net cpu0/k_pp_regs60_RNIHUUP8: 2 loads, 2 LSLICEs
|
|
Net cpu0/state_cnst_i_a15_1_0_RNI7NDU[5]: 4 loads, 4 LSLICEs
|
|
Net cpu0/k_new_pc29_0_o2_0_RNIRRPH4: 4 loads, 4 LSLICEs
|
|
Net cpu0/k_new_pc29_0_o2_0_RNI939S3: 4 loads, 4 LSLICEs
|
|
Net cpu0/un1_state_50_1_i_o2_RNI0FLID: 4 loads, 4 LSLICEs
|
|
Net cpu0/un1_state_21_RNIMEOJ: 4 loads, 4 LSLICEs
|
|
Net cpu0/regs/cff_1_sqmuxa_2_RNI9H8F: 7 loads, 7 LSLICEs
|
Net cpu0/regs/eflag_RNO: 1 loads, 1 LSLICEs
|
Net cpu0/regs/eflag_RNO: 1 loads, 1 LSLICEs
|
Net cpu0/un1_state_18_2_RNI7CC51: 4 loads, 4 LSLICEs
|
Net cpu0/regs/PC_1_sqmuxa_2_RNIDL992: 16 loads, 16 LSLICEs
|
Net cpu0/un1_state_56_RNI0KNU2: 8 loads, 8 LSLICEs
|
Net cpu0/regs/IY_1_sqmuxa_2_1_0_RNISJTR1: 8 loads, 8 LSLICEs
|
Net cpu0/regs/cff_0_sqmuxa_1_0_RNI212L: 7 loads, 7 LSLICEs
|
Net cpu0/regs/IX_0_sqmuxa_1_1_RNIVGKH3: 8 loads, 8 LSLICEs
|
Net cpu0/regs/IY_0_sqmuxa_1_RNI1CVH1: 17 loads, 17 LSLICEs
|
Net cpu0/regs/DP_1_sqmuxa_1_1_0_RNIFF9C1: 5 loads, 5 LSLICEs
|
Net cpu0/regs/IX_0_sqmuxa_1_1_RNIGA2K1: 19 loads, 19 LSLICEs
|
Net cpu0/regs/ACCB_0_sqmuxa_1_RNIIOBV: 4 loads, 4 LSLICEs
|
Net cpu0/regs/DP_1_sqmuxa_0_RNI70L71: 5 loads, 5 LSLICEs
|
Net cpu0/regs/un1_right_reg_4_RNIM2L32: 4 loads, 4 LSLICEs
|
Net cpu0/regs/ACCB_0_sqmuxa_1_RNIHOBV: 4 loads, 4 LSLICEs
|
Net cpu0/un1_k_opcode_3_3_RNIC8F8I: 14 loads, 14 LSLICEs
|
Net cpu0/regs/ACCB45_RNIMT5N2: 4 loads, 4 LSLICEs
|
Net cpu0/state57_RNI9L0F7[0]: 2 loads, 2 LSLICEs
|
Net cpu0/un1_state_18_2_RNI3MPQ: 4 loads, 4 LSLICEs
|
Net cpu0/un1_state_73_RNI7H5S5: 2 loads, 2 LSLICEs
|
Net cpu0/k_ofshi_cnv[0]: 4 loads, 4 LSLICEs
|
|
Net cpu0/state_RNIGVAO2[5]: 4 loads, 4 LSLICEs
|
|
Net cpu0/un1_state_84_1_RNITNQJ9: 4 loads, 4 LSLICEs
|
|
Number of local set/reset loads for net reset_o_c merged into GSR: 6
|
Number of local set/reset loads for net reset_o_c merged into GSR: 6
|
Number of LSRs: 2
|
Number of LSRs: 1
|
Net textctrl.vsync_cnt[10]: 3 loads, 2 LSLICEs
|
Net textctrl.vsync_cnt[10]: 3 loads, 2 LSLICEs
|
Net cpu0/G_7: 1 loads, 1 LSLICEs
|
|
Number of nets driven by tri-state buffers: 0
|
Number of nets driven by tri-state buffers: 0
|
Top 10 highest fanout non-clock nets:
|
Top 10 highest fanout non-clock nets:
|
Net cpu_clk: 117 loads
|
Net cpu_clk: 101 loads
|
Net state_o_c[1]: 103 loads
|
Net cpu0/alu/rop_in[1]: 100 loads
|
Net cpu0/dec_o_alu_opcode[0]: 92 loads
|
Net state_o_c[1]: 84 loads
|
Net state_o_c[4]: 81 loads
|
Net state_o_c[5]: 77 loads
|
Net state_o_c[2]: 74 loads
|
Net cpu0/use_s_1: 75 loads
|
Net cpu0/k_opcode[1]: 72 loads
|
Net state_o_c[2]: 75 loads
|
Net cpu0/dec_o_p1_mode[0]: 70 loads
|
Net state_o_c[4]: 74 loads
|
Net cpu0/dec_o_alu_opcode[4]: 66 loads
|
Net cpu0/alu/rop_in[0]: 71 loads
|
Net cpu0/dec_o_alu_opcode[3]: 63 loads
|
Net state_o_c[3]: 68 loads
|
Net cpu0/k_opcode[3]: 63 loads
|
Net cpu0/k_opcode[3]: 66 loads
|
|
|
Number of warnings: 11
|
Number of warnings: 11
|
Number of errors: 0
|
Number of errors: 0
|
|
|
|
|
Line 1078... |
Line 1070... |
Performance Hardware Data Status: Final) Version 23.4
|
Performance Hardware Data Status: Final) Version 23.4
|
Setup and Hold Report
|
Setup and Hold Report
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
|
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
|
Sun Jan 5 08:23:12 2014
|
Mon Jan 6 06:54:33 2014
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
Line 1104... |
Line 1096... |
|
|
|
|
Timing summary (Setup):
|
Timing summary (Setup):
|
---------------
|
---------------
|
|
|
Timing errors: 1702 Score: 686102
|
Timing errors: 672 Score: 491074
|
Cumulative negative slack: 686102
|
Cumulative negative slack: 491074
|
|
|
Constraints cover 3270002 paths, 1 nets, and 9158 connections (96.1% coverage)
|
Constraints cover 1007472 paths, 1 nets, and 9180 connections (96.2% coverage)
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
|
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
|
Sun Jan 5 08:23:12 2014
|
Mon Jan 6 06:54:33 2014
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
Line 1140... |
Line 1132... |
---------------
|
---------------
|
|
|
Timing errors: 0 Score: 0
|
Timing errors: 0 Score: 0
|
Cumulative negative slack: 0
|
Cumulative negative slack: 0
|
|
|
Constraints cover 3270002 paths, 1 nets, and 9437 connections (99.1% coverage)
|
Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
|
|
|
|
|
|
|
Timing summary (Setup and Hold):
|
Timing summary (Setup and Hold):
|
---------------
|
---------------
|
|
|
Timing errors: 1702 (setup), 0 (hold)
|
Timing errors: 672 (setup), 0 (hold)
|
Score: 686102 (setup), 0 (hold)
|
Score: 491074 (setup), 0 (hold)
|
Cumulative negative slack: 686102 (686102+0)
|
Cumulative negative slack: 491074 (491074+0)
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
Total time: 0 secs
|
Total time: 0 secs
|
Line 1163... |
Line 1155... |
---- MParTrce Tool ----
|
---- MParTrce Tool ----
|
Removing old design directory at request of -rem command line option to this program.
|
Removing old design directory at request of -rem command line option to this program.
|
Running par. Please wait . . .
|
Running par. Please wait . . .
|
|
|
Lattice Place and Route Report for Design "P6809_P6809_map.ncd"
|
Lattice Place and Route Report for Design "P6809_P6809_map.ncd"
|
Sun Jan 5 08:23:12 2014
|
Mon Jan 6 06:54:33 2014
|
|
|
PAR: Place And Route Diamond (64-bit) 2.2.0.101.
|
PAR: Place And Route Diamond (64-bit) 2.2.0.101.
|
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prf
|
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prf
|
Preference file: P6809_P6809.prf.
|
Preference file: P6809_P6809.prf.
|
Placement level-cost: 5-1.
|
Placement level-cost: 5-1.
|
Line 1191... |
Line 1183... |
|
|
PIO (prelim) 49+4(JTAG)/336 14% used
|
PIO (prelim) 49+4(JTAG)/336 14% used
|
49+4(JTAG)/115 42% bonded
|
49+4(JTAG)/115 42% bonded
|
IOLOGIC 10/336 2% used
|
IOLOGIC 10/336 2% used
|
|
|
SLICE 1219/3432 35% used
|
SLICE 1218/3432 35% used
|
|
|
GSR 1/1 100% used
|
GSR 1/1 100% used
|
EBR 10/26 38% used
|
EBR 10/26 38% used
|
|
|
|
|
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
|
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
|
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
|
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
|
Number of Signals: 2800
|
Number of Signals: 2816
|
Number of Connections: 9525
|
Number of Connections: 9541
|
|
|
Pin Constraint Summary:
|
Pin Constraint Summary:
|
49 out of 49 pins locked (100% locked).
|
49 out of 49 pins locked (100% locked).
|
|
|
The following 1 signal is selected to use the primary clock routing resources:
|
The following 1 signal is selected to use the primary clock routing resources:
|
cpu_clkgen (driver: clk40_i, clk load #: 305)
|
cpu_clkgen (driver: clk40_i, clk load #: 290)
|
|
|
|
|
The following 4 signals are selected to use the secondary clock routing resources:
|
The following 4 signals are selected to use the secondary clock routing resources:
|
cpu_clk (driver: SLICE_407, clk load #: 0, sr load #: 0, ce load #: 97)
|
cpu_clk (driver: SLICE_383, clk load #: 0, sr load #: 0, ce load #: 80)
|
cpu0/regs/IX_0_sqmuxa_1_1_RNIGA2K1 (driver: cpu0/SLICE_803, clk load #: 0, sr load #: 0, ce load #: 19)
|
cpu0/k_ealo_cnv_0[0] (driver: cpu0/SLICE_689, clk load #: 0, sr load #: 0, ce load #: 16)
|
cpu0/regs/IY_0_sqmuxa_1_RNI1CVH1 (driver: cpu0/SLICE_804, clk load #: 0, sr load #: 0, ce load #: 17)
|
cpu0/regs/PC_1_sqmuxa_2_RNIDL992 (driver: SLICE_383, clk load #: 0, sr load #: 0, ce load #: 16)
|
cpu0/k_ealo_cnv_0[0] (driver: cpu0/SLICE_793, clk load #: 0, sr load #: 0, ce load #: 16)
|
cpu0/un1_k_opcode_3_3_RNIC8F8I (driver: cpu0/regs/SLICE_634, clk load #: 0, sr load #: 0, ce load #: 14)
|
|
|
Signal reset_o_c is selected as Global Set/Reset.
|
Signal reset_o_c is selected as Global Set/Reset.
|
Starting Placer Phase 0.
|
Starting Placer Phase 0.
|
...........
|
............
|
Finished Placer Phase 0. REAL time: 5 secs
|
Finished Placer Phase 0. REAL time: 4 secs
|
|
|
Starting Placer Phase 1.
|
Starting Placer Phase 1.
|
......................
|
......................
|
Placer score = 869535.
|
Placer score = 892427.
|
Finished Placer Phase 1. REAL time: 13 secs
|
Finished Placer Phase 1. REAL time: 12 secs
|
|
|
Starting Placer Phase 2.
|
Starting Placer Phase 2.
|
.
|
.
|
Placer score = 857738
|
Placer score = 881873
|
Finished Placer Phase 2. REAL time: 14 secs
|
Finished Placer Phase 2. REAL time: 13 secs
|
|
|
|
|
------------------ Clock Report ------------------
|
------------------ Clock Report ------------------
|
|
|
Global Clock Resources:
|
Global Clock Resources:
|
Line 1240... |
Line 1232... |
PLL : 0 out of 2 (0%)
|
PLL : 0 out of 2 (0%)
|
DCM : 0 out of 2 (0%)
|
DCM : 0 out of 2 (0%)
|
DCC : 0 out of 8 (0%)
|
DCC : 0 out of 8 (0%)
|
|
|
Quadrants All (TL, TR, BL, BR) - Global Clocks:
|
Quadrants All (TL, TR, BL, BR) - Global Clocks:
|
PRIMARY "cpu_clkgen" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 305
|
PRIMARY "cpu_clkgen" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 290
|
SECONDARY "cpu_clk" from Q0 on comp "SLICE_407" on site "R21C20C", clk load = 0, ce load = 97, sr load = 0
|
SECONDARY "cpu_clk" from Q0 on comp "SLICE_383" on site "R2C25B", clk load = 0, ce load = 80, sr load = 0
|
SECONDARY "cpu0/k_ealo_cnv_0[0]" from F1 on comp "cpu0/SLICE_793" on site "R25C35A", clk load = 0, ce load = 16, sr load = 0
|
SECONDARY "cpu0/k_ealo_cnv_0[0]" from F1 on comp "cpu0/SLICE_689" on site "R15C40A", clk load = 0, ce load = 16, sr load = 0
|
SECONDARY "cpu0/regs/IY_0_sqmuxa_1_RNI1CVH1" from F1 on comp "cpu0/SLICE_804" on site "R14C20A", clk load = 0, ce load = 17, sr load = 0
|
SECONDARY "cpu0/regs/PC_1_sqmuxa_2_RNIDL992" from F1 on comp "SLICE_383" on site "R2C25B", clk load = 0, ce load = 16, sr load = 0
|
SECONDARY "cpu0/regs/IX_0_sqmuxa_1_1_RNIGA2K1" from F1 on comp "cpu0/SLICE_803" on site "R14C18D", clk load = 0, ce load = 19, sr load = 0
|
SECONDARY "cpu0/un1_k_opcode_3_3_RNIC8F8I" from F0 on comp "cpu0/regs/SLICE_634" on site "R25C35C", clk load = 0, ce load = 14, sr load = 0
|
|
|
PRIMARY : 1 out of 8 (12%)
|
PRIMARY : 1 out of 8 (12%)
|
SECONDARY: 4 out of 8 (50%)
|
SECONDARY: 4 out of 8 (50%)
|
|
|
Edge Clocks:
|
Edge Clocks:
|
Line 1277... |
Line 1269... |
|
|
Total placer CPU time: 13 secs
|
Total placer CPU time: 13 secs
|
|
|
Dumping design to file P6809_P6809.dir/5_1.ncd.
|
Dumping design to file P6809_P6809.dir/5_1.ncd.
|
|
|
0 connections routed; 9525 unrouted.
|
0 connections routed; 9541 unrouted.
|
Starting router resource preassignment
|
Starting router resource preassignment
|
|
|
Completed router resource preassignment. Real time: 17 secs
|
Completed router resource preassignment. Real time: 16 secs
|
|
|
Start NBR router at Sun Jan 05 08:23:29 CET 2014
|
Start NBR router at Mon Jan 06 06:54:49 CET 2014
|
|
|
*****************************************************************
|
*****************************************************************
|
Info: NBR allows conflicts(one node used by more than one signal)
|
Info: NBR allows conflicts(one node used by more than one signal)
|
in the earlier iterations. In each iteration, it tries to
|
in the earlier iterations. In each iteration, it tries to
|
solve the conflicts while keeping the critical connections
|
solve the conflicts while keeping the critical connections
|
Line 1297... |
Line 1289... |
worst slack and total negative slack may not be the same as
|
worst slack and total negative slack may not be the same as
|
that in TRCE report. You should always run TRCE to verify
|
that in TRCE report. You should always run TRCE to verify
|
your design. Thanks.
|
your design. Thanks.
|
*****************************************************************
|
*****************************************************************
|
|
|
Start NBR special constraint process at Sun Jan 05 08:23:29 CET 2014
|
Start NBR special constraint process at Mon Jan 06 06:54:49 CET 2014
|
|
|
Start NBR section for initial routing
|
Start NBR section for initial routing
|
Level 1, iteration 1
|
Level 1, iteration 1
|
126(0.03%) conflicts; 8022(84.22%) untouched conns; 0 (nbr) score;
|
91(0.02%) conflicts; 8164(85.57%) untouched conns; 0 (nbr) score;
|
Estimated worst slack/total negative slack: 0.040ns/0.000ns; real time: 19 secs
|
Estimated worst slack/total negative slack: 0.240ns/0.000ns; real time: 18 secs
|
Level 2, iteration 1
|
Level 2, iteration 1
|
102(0.03%) conflicts; 7583(79.61%) untouched conns; 0 (nbr) score;
|
14(0.00%) conflicts; 8033(84.19%) untouched conns; 0 (nbr) score;
|
Estimated worst slack/total negative slack: 0.119ns/0.000ns; real time: 20 secs
|
Estimated worst slack/total negative slack: 0.378ns/0.000ns; real time: 18 secs
|
Level 3, iteration 1
|
Level 3, iteration 1
|
64(0.02%) conflicts; 5994(62.93%) untouched conns; 0 (nbr) score;
|
53(0.01%) conflicts; 6834(71.63%) untouched conns; 0 (nbr) score;
|
Estimated worst slack/total negative slack: 0.026ns/0.000ns; real time: 21 secs
|
Estimated worst slack/total negative slack: 1.074ns/0.000ns; real time: 19 secs
|
Level 4, iteration 1
|
Level 4, iteration 1
|
315(0.08%) conflicts; 0(0.00%) untouched conn; 58 (nbr) score;
|
396(0.10%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
Estimated worst slack/total negative slack: -0.003ns/-0.058ns; real time: 22 secs
|
Estimated worst slack/total negative slack: 1.051ns/0.000ns; real time: 21 secs
|
|
|
Info: Initial congestion level at 75% usage is 0
|
Info: Initial congestion level at 75% usage is 0
|
Info: Initial congestion area at 75% usage is 24 (2.40%)
|
Info: Initial congestion area at 75% usage is 5 (0.50%)
|
|
|
Start NBR section for normal routing
|
Start NBR section for normal routing
|
Level 1, iteration 1
|
Level 1, iteration 1
|
21(0.01%) conflicts; 420(4.41%) untouched conns; 0 (nbr) score;
|
13(0.00%) conflicts; 564(5.91%) untouched conns; 0 (nbr) score;
|
Estimated worst slack/total negative slack: 0.064ns/0.000ns; real time: 23 secs
|
Estimated worst slack/total negative slack: 1.051ns/0.000ns; real time: 21 secs
|
Level 2, iteration 1
|
Level 2, iteration 1
|
17(0.00%) conflicts; 420(4.41%) untouched conns; 0 (nbr) score;
|
10(0.00%) conflicts; 565(5.92%) untouched conns; 0 (nbr) score;
|
Estimated worst slack/total negative slack: 0.064ns/0.000ns; real time: 23 secs
|
Estimated worst slack/total negative slack: 1.051ns/0.000ns; real time: 21 secs
|
Level 3, iteration 1
|
Level 3, iteration 1
|
22(0.01%) conflicts; 410(4.30%) untouched conns; 0 (nbr) score;
|
17(0.00%) conflicts; 541(5.67%) untouched conns; 0 (nbr) score;
|
Estimated worst slack/total negative slack: 0.064ns/0.000ns; real time: 23 secs
|
Estimated worst slack/total negative slack: 1.051ns/0.000ns; real time: 21 secs
|
Level 4, iteration 1
|
Level 4, iteration 1
|
171(0.05%) conflicts; 0(0.00%) untouched conn; 59 (nbr) score;
|
192(0.05%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
Estimated worst slack/total negative slack: -0.003ns/-0.059ns; real time: 24 secs
|
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 22 secs
|
Level 4, iteration 2
|
Level 4, iteration 2
|
101(0.03%) conflicts; 0(0.00%) untouched conn; 97 (nbr) score;
|
92(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
Estimated worst slack/total negative slack: -0.005ns/-0.097ns; real time: 24 secs
|
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 22 secs
|
Level 4, iteration 3
|
Level 4, iteration 3
|
61(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
36(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
Estimated worst slack/total negative slack: 0.001ns/0.000ns; real time: 24 secs
|
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 22 secs
|
Level 4, iteration 4
|
Level 4, iteration 4
|
39(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
11(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
Estimated worst slack/total negative slack: 0.001ns/0.000ns; real time: 25 secs
|
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 22 secs
|
Level 4, iteration 5
|
Level 4, iteration 5
|
11(0.00%) conflicts; 0(0.00%) untouched conn; 2436 (nbr) score;
|
7(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
Estimated worst slack/total negative slack: -0.101ns/-2.436ns; real time: 25 secs
|
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
|
Level 4, iteration 6
|
Level 4, iteration 6
|
7(0.00%) conflicts; 0(0.00%) untouched conn; 2436 (nbr) score;
|
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
Estimated worst slack/total negative slack: -0.101ns/-2.436ns; real time: 25 secs
|
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
|
Level 4, iteration 7
|
Level 4, iteration 7
|
3(0.00%) conflicts; 0(0.00%) untouched conn; 2252 (nbr) score;
|
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
Estimated worst slack/total negative slack: -0.094ns/-2.252ns; real time: 25 secs
|
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
|
Level 4, iteration 8
|
Level 4, iteration 8
|
3(0.00%) conflicts; 0(0.00%) untouched conn; 2252 (nbr) score;
|
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
Estimated worst slack/total negative slack: -0.094ns/-2.252ns; real time: 25 secs
|
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
|
Level 4, iteration 9
|
Level 4, iteration 9
|
1(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score;
|
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 25 secs
|
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
|
Level 4, iteration 10
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score;
|
|
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 25 secs
|
|
|
|
Start NBR section for performance tunning (iteration 1)
|
|
Level 4, iteration 1
|
|
2(0.00%) conflicts; 0(0.00%) untouched conn; 1916 (nbr) score;
|
|
Estimated worst slack/total negative slack: -0.094ns/-1.916ns; real time: 26 secs
|
|
Level 4, iteration 2
|
|
2(0.00%) conflicts; 0(0.00%) untouched conn; 1916 (nbr) score;
|
|
Estimated worst slack/total negative slack: -0.094ns/-1.916ns; real time: 26 secs
|
|
Level 4, iteration 3
|
|
1(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score;
|
|
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 26 secs
|
|
Level 4, iteration 4
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score;
|
|
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 26 secs
|
|
|
|
Start NBR section for re-routing
|
Start NBR section for re-routing
|
Level 4, iteration 1
|
Level 4, iteration 1
|
0(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score;
|
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 26 secs
|
Estimated worst slack/total negative slack: 1.054ns/0.000ns; real time: 23 secs
|
|
|
Start NBR section for post-routing
|
Start NBR section for post-routing
|
|
|
End NBR router with 0 unrouted connection
|
End NBR router with 0 unrouted connection
|
|
|
NBR Summary
|
NBR Summary
|
-----------
|
-----------
|
Number of unrouted connections : 0 (0.00%)
|
Number of unrouted connections : 0 (0.00%)
|
Number of connections with timing violations : 28 (0.29%)
|
Number of connections with timing violations : 0 (0.00%)
|
Estimated worst slack : -0.094ns
|
Estimated worst slack : 1.054ns
|
Timing score : 281
|
Timing score : 0
|
-----------
|
-----------
|
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
|
|
|
|
|
|
------------------------------------------------------------------------------------------------------------------------------------
|
Hold time optimization iteration 0:
|
WARNING - par: Hold timing correction is skipped because the worst (setup) slack(-0.094ns) is worse than the default value(0.000ns).
|
All hold time violations have been successfully corrected in speed grade M
|
------------------------------------------------------------------------------------------------------------------------------------
|
|
|
|
Total CPU time 26 secs
|
Total CPU time 26 secs
|
Total REAL time: 27 secs
|
Total REAL time: 27 secs
|
Completely routed.
|
Completely routed.
|
End of route. 9525 routed (100.00%); 0 unrouted.
|
End of route. 9541 routed (100.00%); 0 unrouted.
|
Checking DRC ...
|
Checking DRC ...
|
No errors found.
|
No errors found.
|
|
|
Hold time timing score: 0, hold timing errors: 0
|
Hold time timing score: 0, hold timing errors: 0
|
|
|
Timing score: 281
|
Timing score: 0
|
|
|
Dumping design to file P6809_P6809.dir/5_1.ncd.
|
Dumping design to file P6809_P6809.dir/5_1.ncd.
|
|
|
|
|
PAR_SUMMARY::Run status = completed
|
PAR_SUMMARY::Run status = completed
|
PAR_SUMMARY::Number of unrouted conns = 0
|
PAR_SUMMARY::Number of unrouted conns = 0
|
PAR_SUMMARY::Worst slack> = -0.094
|
PAR_SUMMARY::Worst slack> = 1.054
|
PAR_SUMMARY::Timing score> = 0.281
|
PAR_SUMMARY::Timing score> = 0.000
|
PAR_SUMMARY::Worst slack> =
|
PAR_SUMMARY::Worst slack> = 0.180
|
PAR_SUMMARY::Timing score> =
|
PAR_SUMMARY::Timing score> = 0.000
|
|
|
Total CPU time to completion: 27 secs
|
Total CPU time to completion: 27 secs
|
Total REAL time to completion: 28 secs
|
Total REAL time to completion: 27 secs
|
|
|
par done!
|
par done!
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Line 1452... |
Line 1426... |
Performance Hardware Data Status: Final) Version 23.4
|
Performance Hardware Data Status: Final) Version 23.4
|
Setup and Hold Report
|
Setup and Hold Report
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
|
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
|
Sun Jan 5 08:23:43 2014
|
Mon Jan 6 06:55:04 2014
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
Line 1478... |
Line 1452... |
|
|
|
|
Timing summary (Setup):
|
Timing summary (Setup):
|
---------------
|
---------------
|
|
|
Timing errors: 6 Score: 281
|
Timing errors: 0 Score: 0
|
Cumulative negative slack: 281
|
Cumulative negative slack: 0
|
|
|
Constraints cover 3270002 paths, 1 nets, and 9437 connections (99.1% coverage)
|
Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
|
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
|
Sun Jan 5 08:23:43 2014
|
Mon Jan 6 06:55:04 2014
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
Line 1514... |
Line 1488... |
---------------
|
---------------
|
|
|
Timing errors: 0 Score: 0
|
Timing errors: 0 Score: 0
|
Cumulative negative slack: 0
|
Cumulative negative slack: 0
|
|
|
Constraints cover 3270002 paths, 1 nets, and 9437 connections (99.1% coverage)
|
Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
|
|
|
|
|
|
|
Timing summary (Setup and Hold):
|
Timing summary (Setup and Hold):
|
---------------
|
---------------
|
|
|
Timing errors: 6 (setup), 0 (hold)
|
Timing errors: 0 (setup), 0 (hold)
|
Score: 281 (setup), 0 (hold)
|
Score: 0 (setup), 0 (hold)
|
Cumulative negative slack: 281 (281+0)
|
Cumulative negative slack: 0 (0+0)
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
Total time: 0 secs
|
Total time: 0 secs
|
|
|
bitgen -f "P6809_P6809.t2b" -w "P6809_P6809.ncd" -jedec "P6809_P6809.prf"
|
|
|
|
|
|
BITGEN: Bitstream Generator Diamond (64-bit) 2.2.0.101
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
|
|
|
|
|
|
Loading design for application Bitgen from file P6809_P6809.ncd.
|
|
Design name: CC3_top
|
|
NCD version: 3.2
|
|
Vendor: LATTICE
|
|
Device: LCMXO2-7000HE
|
|
Package: TQFP144
|
|
Performance: 4
|
|
Loading device for application Bitgen from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
|
|
Package Status: Final Version 1.36
|
|
Performance Hardware Data Status: Final) Version 23.4
|
|
|
|
Running DRC.
|
|
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
|
|
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
|
|
DRC detected 0 errors and 0 warnings.
|
|
Reading Preference File from P6809_P6809.prf...
|
|
|
|
Preference Summary:
|
|
+---------------------------------+---------------------------------+
|
|
| Preference | Current Setting |
|
|
+---------------------------------+---------------------------------+
|
|
| RamCfg | Reset** |
|
|
+---------------------------------+---------------------------------+
|
|
| MCCLK_FREQ | 2.08** |
|
|
+---------------------------------+---------------------------------+
|
|
| CONFIG_SECURE | OFF** |
|
|
+---------------------------------+---------------------------------+
|
|
| JTAG_PORT | ENABLE** |
|
|
+---------------------------------+---------------------------------+
|
|
| SDM_PORT | DISABLE** |
|
|
+---------------------------------+---------------------------------+
|
|
| SLAVE_SPI_PORT | DISABLE** |
|
|
+---------------------------------+---------------------------------+
|
|
| MASTER_SPI_PORT | DISABLE** |
|
|
+---------------------------------+---------------------------------+
|
|
| I2C_PORT | DISABLE** |
|
|
+---------------------------------+---------------------------------+
|
|
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
|
+---------------------------------+---------------------------------+
|
|
| CONFIGURATION | CFG** |
|
|
+---------------------------------+---------------------------------+
|
|
| COMPRESS_CONFIG | ON** |
|
|
+---------------------------------+---------------------------------+
|
|
| MY_ASSP | OFF** |
|
|
+---------------------------------+---------------------------------+
|
|
| ONE_TIME_PROGRAM | OFF** |
|
|
+---------------------------------+---------------------------------+
|
|
| ENABLE_TRANSFR | DISABLE** |
|
|
+---------------------------------+---------------------------------+
|
|
| SHAREDEBRINIT | DISABLE** |
|
|
+---------------------------------+---------------------------------+
|
|
* Default setting.
|
|
** The specified setting matches the default setting.
|
|
|
|
|
|
Creating bit map...
|
|
|
|
Bitstream Status: Final Version 1.83
|
|
|
|
Saving bit stream in "P6809_P6809.jed".
|
|
|
|
===========
|
|
UFM Summary
|
|
===========
|
|
UFM Size: 2046 Pages (128*2046 Bits)
|
|
UFM Utilization: General Purpose Flash Memory
|
|
|
|
Available General Purpose Flash Memory: 2046 Pages (Page 0 to Page 2045)
|
|
Initialized UFM Pages: 0 Page
|
|
|
|