OpenCores
URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [hdla_gen_hierarchy.html] - Diff between revs 9 and 10

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 9 Rev 10
Line 7... Line 7... 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(8,10-8,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(8,10-8,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v(9,10-9,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v(9,10-9,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v(699,24-699,29) WARNING: (VERI-1208) literal value truncated to fit in 4 bits
 
 
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v(4,10-4,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v(4,10-4,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v(10,8-10,15) INFO: (VERI-1018) compiling module CC3_top
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v(10,8-10,15) INFO: (VERI-1018) compiling module CC3_top
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v(10,1-134,10) INFO: (VERI-9000) elaborating module 'CC3_top'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v(10,1-175,10) INFO: (VERI-9000) elaborating module 'CC3_top'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v(10,1-1049,10) INFO: (VERI-9000) elaborating module 'MC6809_cpu_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v(10,1-1110,10) INFO: (VERI-9000) elaborating module 'MC6809_cpu_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v(8,1-171,10) INFO: (VERI-9000) elaborating module 'bios2k_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v(8,1-171,10) INFO: (VERI-9000) elaborating module 'bios2k_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v(2,1-192,10) INFO: (VERI-9000) elaborating module 'vgatext_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v(2,1-192,10) INFO: (VERI-9000) elaborating module 'vgatext_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(15,1-57,10) INFO: (VERI-9000) elaborating module 'alu_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(15,1-57,10) INFO: (VERI-9000) elaborating module 'alu_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v(7,1-188,10) INFO: (VERI-9000) elaborating module 'regblock_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v(7,1-188,10) INFO: (VERI-9000) elaborating module 'regblock_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(9,1-135,10) INFO: (VERI-9000) elaborating module 'decode_regs_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(9,1-133,10) INFO: (VERI-9000) elaborating module 'decode_regs_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(138,1-261,10) INFO: (VERI-9000) elaborating module 'decode_op_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(136,1-259,10) INFO: (VERI-9000) elaborating module 'decode_op_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(266,1-290,10) INFO: (VERI-9000) elaborating module 'decode_ea_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(264,1-288,10) INFO: (VERI-9000) elaborating module 'decode_ea_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(292,1-363,10) INFO: (VERI-9000) elaborating module 'decode_alu_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(290,1-361,10) INFO: (VERI-9000) elaborating module 'decode_alu_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(365,1-401,10) INFO: (VERI-9000) elaborating module 'test_condition_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(363,1-399,10) INFO: (VERI-9000) elaborating module 'test_condition_uniq_1'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) INFO: (VERI-9000) elaborating module 'VHI_uniq_1'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) INFO: (VERI-9000) elaborating module 'VHI_uniq_1'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_1'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_1'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_2'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_2'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO_uniq_1'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v(8,1-295,10) INFO: (VERI-9000) elaborating module 'fontrom_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v(8,1-295,10) INFO: (VERI-9000) elaborating module 'fontrom_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v(8,1-305,10) INFO: (VERI-9000) elaborating module 'textmem4k_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v(8,1-305,10) INFO: (VERI-9000) elaborating module 'textmem4k_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(197,1-322,10) INFO: (VERI-9000) elaborating module 'alu8_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(198,1-323,10) INFO: (VERI-9000) elaborating module 'alu8_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(325,1-601,10) INFO: (VERI-9000) elaborating module 'alu16_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(326,1-602,10) INFO: (VERI-9000) elaborating module 'alu16_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v(191,1-285,10) INFO: (VERI-9000) elaborating module 'calc_ea_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v(191,1-285,10) INFO: (VERI-9000) elaborating module 'calc_ea_uniq_1'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) INFO: (VERI-9000) elaborating module 'VHI_uniq_2'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) INFO: (VERI-9000) elaborating module 'VHI_uniq_2'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) INFO: (VERI-9000) elaborating module 'VHI_uniq_3'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) INFO: (VERI-9000) elaborating module 'VHI_uniq_3'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_3'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_3'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_4'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_4'
Line 48... Line 47... 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_9'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_9'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_10'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_10'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO_uniq_2'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO_uniq_2'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO_uniq_3'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO_uniq_3'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(62,1-79,10) INFO: (VERI-9000) elaborating module 'logic8_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(62,1-79,10) INFO: (VERI-9000) elaborating module 'logic8_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(85,1-122,10) INFO: (VERI-9000) elaborating module 'arith8_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(85,1-123,10) INFO: (VERI-9000) elaborating module 'arith8_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(157,1-194,10) INFO: (VERI-9000) elaborating module 'shift8_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(158,1-195,10) INFO: (VERI-9000) elaborating module 'shift8_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(603,1-627,10) INFO: (VERI-9000) elaborating module 'mul8x8_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(604,1-628,10) INFO: (VERI-9000) elaborating module 'mul8x8_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(128,1-155,10) INFO: (VERI-9000) elaborating module 'arith16_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(129,1-156,10) INFO: (VERI-9000) elaborating module 'arith16_uniq_1'
 
Design load finished with (0) errors, and (1) warnings.
 
Design load finished with (0) errors, and (0) warnings.
 
 
 
 
 
</PRE></BODY></HTML>
 
</PRE></BODY></HTML>
 
 No newline at end of file
 
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.