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URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [hdla_gen_hierarchy.html] - Diff between revs 5 and 6

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Rev 5 Rev 6
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INFO: (VHDL-1504) The default vhdl library search path is now "/usr/local/diamond/2.2_x64/cae_library/vhdl_packages/vdbs"
 
INFO: (VHDL-1504) The default vhdl library search path is now "/usr/local/diamond/2.2_x64/cae_library/vhdl_packages/vdbs"
 
-- (VERI-1482) Analyzing Verilog file /usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v
 
-- (VERI-1482) Analyzing Verilog file /usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(12,10-12,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(12,10-12,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(517,1-517,10) ERROR: (VERI-1137) syntax error near endmodule
 
 
 
-- (VERI-1483) Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v ignored due to errors
 
 
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(8,10-8,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(8,10-8,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v(9,10-9,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v(9,10-9,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
 
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v(727,24-727,29) WARNING: (VERI-1208) literal value truncated to fit in 4 bits
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v(4,10-4,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v(4,10-4,18) INFO: (VERI-1328) analyzing included file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v
 
-- (VERI-1482) Analyzing Verilog file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v(10,8-10,15) INFO: (VERI-1018) compiling module CC3_top
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v(10,8-10,15) INFO: (VERI-1018) compiling module CC3_top
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v(10,1-109,10) INFO: (VERI-9000) elaborating module 'CC3_top'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v(10,1-109,10) INFO: (VERI-9000) elaborating module 'CC3_top'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v(10,1-976,10) INFO: (VERI-9000) elaborating module 'MC6809_cpu_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v(10,1-1027,10) INFO: (VERI-9000) elaborating module 'MC6809_cpu_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v(8,1-171,10) INFO: (VERI-9000) elaborating module 'bios2k_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v(8,1-171,10) INFO: (VERI-9000) elaborating module 'bios2k_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(13,1-503,10) INFO: (VERI-9000) elaborating module 'alu16_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(15,1-55,10) INFO: (VERI-9000) elaborating module 'alu_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v(7,1-255,10) INFO: (VERI-9000) elaborating module 'regblock_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v(7,1-254,10) INFO: (VERI-9000) elaborating module 'regblock_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(9,1-128,10) INFO: (VERI-9000) elaborating module 'decode_regs_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(9,1-128,10) INFO: (VERI-9000) elaborating module 'decode_regs_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(131,1-254,10) INFO: (VERI-9000) elaborating module 'decode_op_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(131,1-254,10) INFO: (VERI-9000) elaborating module 'decode_op_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(259,1-283,10) INFO: (VERI-9000) elaborating module 'decode_ea_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(259,1-283,10) INFO: (VERI-9000) elaborating module 'decode_ea_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(285,1-356,10) INFO: (VERI-9000) elaborating module 'decode_alu_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(285,1-356,10) INFO: (VERI-9000) elaborating module 'decode_alu_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(358,1-394,10) INFO: (VERI-9000) elaborating module 'test_condition_uniq_1'
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v(358,1-394,10) INFO: (VERI-9000) elaborating module 'test_condition_uniq_1'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) INFO: (VERI-9000) elaborating module 'VHI_uniq_1'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) INFO: (VERI-9000) elaborating module 'VHI_uniq_1'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_1'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_1'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_2'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_2'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO_uniq_1'
 
/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO_uniq_1'
 
Design load finished with (1) errors, and (0) warnings.
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(57,1-322,10) INFO: (VERI-9000) elaborating module 'alu8_uniq_1'
 
 
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(325,1-648,10) INFO: (VERI-9000) elaborating module 'alu16_uniq_1'
 
 
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(650,1-674,10) INFO: (VERI-9000) elaborating module 'mul8x8_uniq_1'
 
 
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(32,19-32,29) WARNING: (VERI-1330) actual bit length 8 differs from formal bit length 16 for port a_in
 
 
 
/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v(32,31-32,41) WARNING: (VERI-1330) actual bit length 8 differs from formal bit length 16 for port b_in
 
 
 
Design load finished with (0) errors, and (3) warnings.
 
 
 
 
 
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