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#-- Synopsys, Inc.
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#-- Synopsys, Inc.
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#-- Version G-2012.09L-SP1
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#-- Version I-2013.09L
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#-- Project file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/scratchproject.prs
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#-- Project file C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\scratchproject.prs
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#project files
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#project files
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add_file -verilog "/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"
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add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/CC3_top.v"
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add_file -verilog "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
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add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v"
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add_file -verilog "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
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add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v"
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add_file -verilog "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
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add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/defs.v"
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add_file -verilog "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
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add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/MC6809_cpu.v"
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add_file -verilog "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
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add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v"
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add_file -verilog "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
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add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/bios2k.v"
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add_file -verilog "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
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add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/vgatext.v"
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add_file -verilog "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"
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add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/fontrom.v"
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add_file -verilog "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"
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add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/textmem4k.v"
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add_file -verilog "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"
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#implementation: "P6809"
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#implementation: "P6809"
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impl -add /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809 -type fpga
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impl -add C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809 -type fpga
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#
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#
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#implementation attributes
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#implementation attributes
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set_option -vlog_std sysv
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set_option -vlog_std v2001
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set_option -project_relative_includes 1
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set_option -project_relative_includes 1
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set_option -include_path {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/}
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set_option -include_path {C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809/}
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set_option -include_path {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice;/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice;/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice}
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set_option -include_path {C:/02_Elektronik/020_V6809/trunk/syn/lattice}
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#device options
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#device options
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set_option -technology MACHXO2
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set_option -technology MACHXO2
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set_option -part LCMXO2_7000HE
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set_option -part LCMXO2_7000HE
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set_option -package TG144C
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set_option -package TG144C
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#compilation/mapping options
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#compilation/mapping options
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set_option -top_module "CC3_top"
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set_option -top_module "CC3_top"
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# mapper_options
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# mapper_options
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set_option -frequency auto
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set_option -frequency 1
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set_option -write_verilog 0
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set_option -write_verilog 0
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set_option -write_vhdl 0
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set_option -write_vhdl 0
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set_option -srs_instrumentation 1
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set_option -srs_instrumentation 1
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# Lattice XP
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# Lattice XP
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set_option -maxfan 1000
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set_option -maxfan 1000
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set_option -disable_io_insertion 0
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set_option -disable_io_insertion 0
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set_option -retiming 0
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set_option -retiming 0
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set_option -pipe 1
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set_option -pipe 1
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set_option -forcegsr no
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set_option -forcegsr false
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set_option -fix_gated_and_generated_clocks 1
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set_option -fix_gated_and_generated_clocks 1
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set_option -RWCheckOnRam 1
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set_option -RWCheckOnRam 1
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set_option -update_models_cp 0
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set_option -update_models_cp 0
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set_option -syn_edif_array_rename 1
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set_option -syn_edif_array_rename 1
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#automatic place and route (vendor) options
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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set_option -write_apr_constraint 1
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#set result format/file last
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#set result format/file last
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project -result_file "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809.edi"
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project -result_file "C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809/P6809_P6809.edi"
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#set log file
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set_option log_file "C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809/P6809_P6809.srf"
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impl -active "P6809"
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impl -active "P6809"
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