URL
https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
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Line 76... |
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exit status=0
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exit status=0
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Save changes for project:
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Save changes for project:
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C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\proj_1.prj
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C:\02_Elektronik\020_V6809\trunk\synlog file: "C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809.srr"
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batch mode default:no
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Running P6809_syn|P6809
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Running: Compile on P6809_syn|P6809
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Running: Compile Process on P6809_syn|P6809
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Running: Compile Input on P6809_syn|P6809
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Copied C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\synwork\P6809_comp.srs to C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809.srs
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compiler Completed with warnings
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Return Code: 1
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Run Time:0h:00m:04s
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Complete: Compile Process on P6809_syn|P6809
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Running: Premap on P6809_syn|P6809
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premap Completed with warnings
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Return Code: 1
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Run Time:0h:00m:01s
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Complete: Compile on P6809_syn|P6809
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Running: Map on P6809_syn|P6809
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Running: Map & Optimize on P6809_syn|P6809
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fpga_mapper Completed with warnings
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Return Code: 1
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Run Time:0h:00m:22s
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Complete: Map on P6809_syn|P6809
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Complete: Logic Synthesis on P6809_syn|P6809
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Opening object source file c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v
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Opening object source file c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v
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Opening object source file c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v
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Opening object source file c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v
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exit status=0
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