URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [bios2k.lpc] - Diff between revs 7 and 10

Rev 7	Rev 10
Line 14...	Line 14...
`CoreName=RAM_DP_TRUE`	`CoreName=RAM_DP_TRUE`
`CoreRevision=7.2`	`CoreRevision=7.2`
`ModuleName=bios2k`	`ModuleName=bios2k`
`SourceFormat=Verilog HDL`	`SourceFormat=Verilog HDL`
`ParameterFileVersion=1.0`	`ParameterFileVersion=1.0`
`Date=01/03/2014`	`Date=02/06/2014`
`Time=08:42:51`	`Time=15:31:10`

`[Parameters]`	`[Parameters]`
`Verilog=1`	`Verilog=1`
`VHDL=0`	`VHDL=0`
`EDIF=1`	`EDIF=1`
Line 39...	Line 39...
`ByteSize=9`	`ByteSize=9`
`Optimization=Speed`	`Optimization=Speed`
`Reset=Sync`	`Reset=Sync`
`Reset1=Sync`	`Reset1=Sync`
`Init=mem`	`Init=mem`
`MemFile=test1.mem`	`MemFile=/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/test1.mem`
`MemFormat=orca`	`MemFormat=orca`
`EnECC=0`	`EnECC=0`
`Pipeline=0`	`Pipeline=0`
`WriteA=Normal`	`WriteA=Normal`
`WriteB=Normal`	`WriteB=Normal`
`init_data=0`	`init_data=0`

`[FilesGenerated]`	`[FilesGenerated]`
`test1.mem=mem`	`/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/test1.mem=mem`
`/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/test1.mem=mem`	`/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/test1.mem=mem`