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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/10/28 16:43:12 simont
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// add module oc8051_wb_iinterface
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//
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// Revision 1.6 2002/10/24 13:36:53 simont
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// Revision 1.6 2002/10/24 13:36:53 simont
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// add instruction cache and DELAY parameters for external ram, rom
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// add instruction cache and DELAY parameters for external ram, rom
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//
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//
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// Revision 1.5 2002/10/17 19:00:50 simont
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// Revision 1.5 2002/10/17 19:00:50 simont
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// add external rom
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// add external rom
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| Line 63... |
Line 66... |
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module oc8051_tb;
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module oc8051_tb;
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reg rst, clk;
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reg rst, clk;
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reg [15:0] pc_in;
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reg [7:0] p0_in, p1_in, p2_in;
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reg [7:0] p0_in, p1_in, p2_in;
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wire [31:0] idat_i;
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wire [31:0] idat_i;
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wire [15:0] ext_addr, iadr_o;
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wire [15:0] ext_addr, iadr_o;
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wire write, write_xram, write_uart, txd, rxd, int_uart, int0, int1, t0, t1, bit_out, stb_o, ack_i, ack_xram, ack_uart, cyc_o, iack_i, istb_o, icyc_o;
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wire write, write_xram, write_uart, txd, rxd, int_uart, int0, int1, t0, t1, bit_out, stb_o, ack_i;
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wire ack_xram, ack_uart, cyc_o, iack_i, istb_o, icyc_o, t2, t2ex;
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wire [7:0] data_in, data_out, p0_out, p1_out, p2_out, p3_out, data_out_uart, data_out_xram, p3_in;
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wire [7:0] data_in, data_out, p0_out, p1_out, p2_out, p3_out, data_out_uart, data_out_xram, p3_in;
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///
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///
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/// buffer for test vectors
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/// buffer for test vectors
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///
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///
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//
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//
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// buffer
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// buffer
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Line 89... |
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//
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//
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// oc8051 controller
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// oc8051 controller
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//
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//
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oc8051_top oc8051_top_1(.rst(rst), .clk(clk), .int0(int0), .int1(int1),
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oc8051_top oc8051_top_1(.rst_i(rst), .clk(clk), .int0(int0), .int1(int1),
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.dat_i(data_in), .dat_o(data_out),
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.ddat_i(data_in), .ddat_o(data_out),
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.adr_o(ext_addr), .iadr_o(iadr_o), .istb_o(istb_o), .iack_i(iack_i),
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.dadr_o(ext_addr), .iadr_o(iadr_o), .istb_o(istb_o), .iack_i(iack_i),
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.icyc_o(icyc_o), .we_o(write), .p0_in(p0_in),
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.icyc_o(icyc_o), .dwe_o(write), .p0_in(p0_in),
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.ack_i(ack_i), .stb_o(stb_o), .cyc_o(cyc_o),
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.dack_i(ack_i), .dstb_o(stb_o), .dcyc_o(cyc_o),
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.p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in), .p0_out(p0_out), .p1_out(p1_out),
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.p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in), .p0_out(p0_out), .p1_out(p1_out),
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.p2_out(p2_out), .p3_out(p3_out), .idat_i(idat_i), .ea(ea[0]),
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.p2_out(p2_out), .p3_out(p3_out), .idat_i(idat_i), .ea(ea[0]),
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.rxd(rxd), .txd(txd), .t0(t0), .t1(t1));
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.rxd(rxd), .txd(txd), .t0(t0), .t1(t1), .t2(t2), .t2ex(t2ex));
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//
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//
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// external data ram
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// external data ram
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//
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//
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Line 171... |
defparam oc8051_xrom1.DELAY = 5;
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defparam oc8051_xrom1.DELAY = 5;
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//
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//
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// test wb interface
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// test wb interface
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//
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//
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reg [31:0] log_file;
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reg [31:0] log_file;
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initial
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initial
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begin
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begin
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log_file = $fopen("log_file");
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log_file = $fopen("log_file");
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$fdisplay(log_file, "file open");
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$fdisplay(log_file, "file open");
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end
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end
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// cache/cpu to instruction rom
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//
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WB_BUS_MON wb_bus_mon1(.CLK_I(clk), .RST_I(rst), .ACK_I(iack_o), .ADDR_O({16'h0000, iadr_i}), .CYC_O(icyc_i),
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.DAT_I(idat_o), .DAT_O(32'd0), .ERR_I(1'b0), .RTY_I(1'b0), .SEL_O(4'b0000), .STB_O(istb_i),
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.WE_O(1'b0), .TAG_I(4'h0), .TAG_O(4'h0), .CAB_O(1'b0), .log_file_desc(log_file));
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// cpu to data ram
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//
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WB_BUS_MON wb_bus_mon3(.CLK_I(clk), .RST_I(rst), .ACK_I(ack_i), .ADDR_O({16'h0000, ext_addr}), .CYC_O(cyc_o),
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.DAT_I({24'h000000, data_in}), .DAT_O({24'h000000, data_out}), .ERR_I(1'b0), .RTY_I(1'b0), .SEL_O(4'b0000), .STB_O(stb_o),
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.WE_O(write), .TAG_I(4'h0), .TAG_O(4'h0), .CAB_O(1'b0), .log_file_desc(log_file));
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//
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//
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//
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//
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assign write_xram = p3_out[7] & write;
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assign write_xram = p3_out[7] & write;
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assign write_uart = !p3_out[7] & write;
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assign write_uart = !p3_out[7] & write;
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assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
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assign data_in = p3_out[7] ? data_out_xram : data_out_uart;
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assign ack_i = p3_out[7] ? ack_xram : ack_uart;
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assign ack_i = p3_out[7] ? ack_xram : ack_uart;
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assign p3_in = {7'b000000, bit_out, int_uart};
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assign p3_in = {6'h0, bit_out, int_uart};
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assign t0 = p3_out[5];
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assign t0 = p3_out[5];
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assign t1 = p3_out[6];
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assign t1 = p3_out[6];
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assign int0 = p3_out[3];
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assign int0 = p3_out[3];
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assign int1 = p3_out[4];
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assign int1 = p3_out[4];
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assign t2 = p3_out[5];
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assign t2ex = p3_out[2];
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initial begin
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initial begin
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clk= 1'b0;
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clk= 1'b0;
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rst= 1'b1;
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rst= 1'b1;
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pc_in = 16'h0000;
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p0_in = 8'h00;
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p0_in = 8'h00;
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p1_in = 8'h00;
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p1_in = 8'h00;
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p2_in = 8'h00;
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p2_in = 8'h00;
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#22
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#22
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rst = 1'b0;
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rst = 1'b0;
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//#444000
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#7000000
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#7000000
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$fclose(log_file);
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$fclose(log_file);
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$display("time ",$time, "\n faulire: end of time\n \n");
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$display("time ",$time, "\n faulire: end of time\n \n");
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$finish;
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$finish;
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| Line 267... |
Line 252... |
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initial $dumpvars;
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initial $dumpvars;
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//initial $monitor("time ",$time," acc %h", data_out, " dptr %h", ext_addr, " write ", write, " p0_out %h", p0_out, " p1_out %h", p1_out);
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//initial $monitor("time ",$time, " p0_out ", p0_out);
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//initial $monitor("time ",$time," write ", write, " p0_out %h", p0_out, " p1_out %h", p1_out, " p2_out %h", p2_out, " p3_out %h", p3_out);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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