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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2003/01/13 14:14:40 simont
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// replace some modules
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//
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// Revision 1.8 2002/11/05 17:23:54 simont
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// Revision 1.8 2002/11/05 17:23:54 simont
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// add module oc8051_sfr, 256 bytes internal ram
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// add module oc8051_sfr, 256 bytes internal ram
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//
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//
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// Revision 1.7 2002/09/30 17:33:59 simont
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// Revision 1.7 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_acc (clk, rst, bit_in, data_in, data2_in, wr, wr_bit, wr_addr, rd_addr,
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module oc8051_acc (clk, rst,
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data_out, bit_out, p, wr_sfr);
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bit_in, data_in, data2_in,
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// clk (in) clock
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data_out,
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// rst (in) reset
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wr, wr_bit, wr_addr,
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// bit_in (in) bit input - used in case of writing bits to acc (bit adddressable memory space - alu carry) [oc8051_alu.desCy]
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p, wr_sfr);
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// data_in (in) data input - used to write to acc (from alu destiantion 1) [oc8051_alu.des1]
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// data2_in (in) data 2 input - write to acc, from alu detination 2 - instuctions mul and div [oc8051_alu.des2]
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// wr (in) write - actine high [oc8051_decoder.wr -r]
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// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
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// wr_addr (in) write address (if is addres of acc and white high must be written to acc) [oc8051_ram_wr_sel.out]
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// data_out (out) data output [oc8051_alu_src1_sel.acc oc8051_alu_src2_sel.acc oc8051_comp.acc oc8051_ram_sel.acc]
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// p (out) parity [oc8051_psw.p]
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// mx_ext (in) mx extension
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// wr_sfr
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//
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input clk, rst, wr, wr_bit, bit_in;
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input clk, rst, wr, wr_bit, bit_in;
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input [2:0] rd_addr, wr_sfr;
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input [2:0] wr_sfr;
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input [7:0] wr_addr, data_in, data2_in;
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input [7:0] wr_addr, data_in, data2_in;
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output p, bit_out;
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output p;
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output [7:0] data_out;
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output [7:0] data_out;
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reg [7:0] data_out;
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reg [7:0] data_out;
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reg bit_out;
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//
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//
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//calculates parity
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//calculates parity
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assign p = ^data_out;
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assign p = ^data_out;
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data_out[wr_addr[2:0]] <= #1 bit_in;
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data_out[wr_addr[2:0]] <= #1 bit_in;
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end
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end
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end
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end
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end
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end
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always @(posedge clk or posedge rst)
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begin
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if (rst) bit_out <= #1 1'b0;
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else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin
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bit_out <= #1 bit_in;
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end else if (((wr_addr==`OC8051_SFR_ACC) & wr & !wr_bit) || (wr_sfr==`OC8051_WRS_ACC1)) begin
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bit_out <= #1 data_in[rd_addr];
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end else if ((wr_sfr==`OC8051_WRS_ACC2) || (wr_sfr==`OC8051_WRS_BA)) begin
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bit_out <= #1 data2_in[rd_addr];
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end else bit_out <= #1 data_out[rd_addr];
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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