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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2003/04/09 15:49:42 simont
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// Register oc8051_sfr dato output, add signal wait_data.
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//
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// Revision 1.10 2003/04/07 14:58:02 simont
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// Revision 1.10 2003/04/07 14:58:02 simont
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// change sfr's interface.
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// change sfr's interface.
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//
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//
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// Revision 1.9 2003/01/13 14:14:40 simont
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// Revision 1.9 2003/01/13 14:14:40 simont
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// replace some modules
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// replace some modules
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Line 74... |
wr, wr_bit, wr_addr,
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wr, wr_bit, wr_addr,
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p, wr_sfr);
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p, wr_sfr);
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input clk, rst, wr, wr_bit, bit_in;
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input clk, rst, wr, wr_bit, bit_in;
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input [2:0] wr_sfr;
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input [1:0] wr_sfr;
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input [7:0] wr_addr, data_in, data2_in;
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input [7:0] wr_addr, data_in, data2_in;
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output p;
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output p;
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output [7:0] data_out;
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output [7:0] data_out;
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Line 89... |
//
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//
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//calculates parity
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//calculates parity
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assign p = ^acc;
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assign p = ^acc;
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assign wr_acc = (wr_sfr==`OC8051_WRS_ACC1) | (wr & !wr_bit & (wr_addr==`OC8051_SFR_ACC));
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assign wr_acc = (wr_sfr==`OC8051_WRS_ACC1) | (wr & !wr_bit & (wr_addr==`OC8051_SFR_ACC));
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assign wr2_acc = (wr_sfr==`OC8051_WRS_ACC2) | (wr_sfr==`OC8051_WRS_BA);
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assign wr2_acc = (wr_sfr==`OC8051_WRS_ACC2);
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assign wr_bit_acc = (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_ACC));
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assign wr_bit_acc = (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_ACC));
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//
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//
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//writing to acc
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//writing to acc
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always @(wr_sfr or data2_in or wr2_acc or wr_acc or wr_bit_acc or wr_addr[2:0] or data_in or bit_in or data_out)
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always @(wr_sfr or data2_in or wr2_acc or wr_acc or wr_bit_acc or wr_addr[2:0] or data_in or bit_in or data_out)
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begin
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begin
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