| Line 39... |
Line 39... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// ver: 1
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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| Line 62... |
Line 64... |
// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
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// wr_bit (in) write bit addresable - actine high [oc8051_decoder.bit_addr -r]
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// wad2 (in) write data 2 [oc8051_decoder.wad2 -r]
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// wad2 (in) write data 2 [oc8051_decoder.wad2 -r]
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// wr_addr (in) write address (if is addres of acc and white high must be written to acc) [oc8051_ram_wr_sel.out]
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// wr_addr (in) write address (if is addres of acc and white high must be written to acc) [oc8051_ram_wr_sel.out]
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// data_out (out) data output [oc8051_alu_src1_sel.acc oc8051_alu_src2_sel.acc oc8051_comp.acc oc8051_ram_sel.acc]
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// data_out (out) data output [oc8051_alu_src1_sel.acc oc8051_alu_src2_sel.acc oc8051_comp.acc oc8051_ram_sel.acc]
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// p (out) parity [oc8051_psw.p]
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// p (out) parity [oc8051_psw.p]
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// stb_o (in) strobe
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// we_o (in) write to external ram
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// ack_i (in) acknowlage from external ram
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// xdata (in) external data input
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//
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input clk, rst, wr, wr_bit, wad2, bit_in, stb_o, we_o, ack_i;
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input clk, rst, wr, wr_bit, wad2, bit_in, stb_o, we_o, ack_i;
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input [2:0] rd_addr;
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input [2:0] rd_addr;
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input [7:0] wr_addr, data_in, data2_in, xdata;
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input [7:0] wr_addr, data_in, data2_in, xdata;
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