| Line 74... |
Line 74... |
wire div0, div1;
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wire div0, div1;
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wire [7:0] rem0, rem1, rem2;
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wire [7:0] rem0, rem1, rem2;
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wire [8:0] sub0, sub1;
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wire [8:0] sub0, sub1;
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wire [15:0] cmp0, cmp1;
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wire [15:0] cmp0, cmp1;
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wire [7:0] div_out, rem_out;
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wire [7:0] div_out, rem_out;
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wire [7:0] div;
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// real registers
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// real registers
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reg [1:0] cycle;
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reg [1:0] cycle;
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reg [5:0] tmp_div;
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reg [5:0] tmp_div;
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reg [7:0] tmp_rem;
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reg [7:0] tmp_rem;
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| Line 89... |
Line 88... |
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assign rem2 = cycle != 0 ? tmp_rem : src1;
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assign rem2 = cycle != 0 ? tmp_rem : src1;
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assign sub1 = {1'b0, rem2} - {1'b0, cmp1[7:0]};
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assign sub1 = {1'b0, rem2} - {1'b0, cmp1[7:0]};
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assign div1 = |cmp1[15:8] ? 1'b0 : !sub1[8];
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assign div1 = |cmp1[15:8] ? 1'b0 : !sub1[8];
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assign rem1 = div1 ? sub1[7:0] : cmp1[7:0];
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assign rem1 = div1 ? sub1[7:0] : rem2[7:0];
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assign sub0 = {1'b0, rem1} - {1'b0, cmp0[7:0]};
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assign sub0 = {1'b0, rem1} - {1'b0, cmp0[7:0]};
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assign div0 = |cmp0[15:8] ? 1'b0 : !sub0[8];
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assign div0 = |cmp0[15:8] ? 1'b0 : !sub0[8];
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assign rem0 = div0 ? sub0[7:0] : cmp0[7:0];
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assign rem0 = div0 ? sub0[7:0] : rem1[7:0];
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//
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//
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// in clock cycle 0 we first calculate two MSB bits, ...
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// in clock cycle 0 we first calculate two MSB bits, ...
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// till finally in clock cycle 3 we calculate two LSB bits
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// till finally in clock cycle 3 we calculate two LSB bits
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assign div_out = {tmp_div, div1, div0};
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assign div_out = {tmp_div, div1, div0};
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