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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_multiply.v] - Diff between revs 5 and 20
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Rev 20 |
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Line 45... |
// ver: 1
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// ver: 1
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//
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//
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// ver: 2 markom
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// ver: 2 markom
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// changed to two cycle multiplication, to save resources and
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// changed to two cycle multiplication, to save resources and
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// increase speed
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// increase speed
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//
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// ver: 3 markom
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// changed to four cycle multiplication, to save resources and
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// increase speed
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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Line 77... |
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// wires
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// wires
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wire [15:0] mul_result1, mul_result;
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wire [15:0] mul_result1, mul_result;
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// real registers
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// real registers
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reg cycle;
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reg [1:0] cycle;
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reg [11:0] tmp_mul;
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reg [13:0] tmp_mul;
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assign mul_result1 = src1 * (cycle == 0 ? src2[7:6]
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: cycle == 1 ? src2[5:4]
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: cycle == 2 ? src2[3:2]
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: src2[1:0]);
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assign mul_result1 = src1 * (cycle ? src2[7:4] : src2[3:0]);
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assign mul_result = mul_result1 + {2'b0, tmp_mul};
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assign mul_result = mul_result1 + {4'b0, tmp_mul};
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assign des1 = mul_result[7:0];
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assign des1 = mul_result[7:0];
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assign des2 = mul_result[15:8];
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assign des2 = mul_result[15:8];
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assign desOv = des2 != 8'h0;
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assign desOv = des2 != 8'h0;
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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cycle <= #1 1'b0;
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cycle <= #1 1'b0;
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tmp_mul <= #1 12'b0;
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tmp_mul <= #1 14'b0;
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end else begin
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end else begin
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if (enable && !cycle) cycle <= #1 1'b1;
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if (enable || cycle != 0) cycle <= #1 cycle + 2'b1;
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else cycle <= #1 1'b0;
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tmp_mul <= #1 mul_result1[13:0];
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tmp_mul <= #1 mul_result1[11:0];
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end
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end
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end
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end
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endmodule
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endmodule
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