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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_multiply.v] - Diff between revs 25 and 32
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| Rev 25 |
Rev 32 |
| Line 84... |
Line 84... |
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assign mul_result1 = src1 * (cycle == 2'h0 ? src2[7:6]
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assign mul_result1 = src1 * (cycle == 2'h0 ? src2[7:6]
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: cycle == 2'h1 ? src2[5:4]
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: cycle == 2'h1 ? src2[5:4]
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: cycle == 2'h2 ? src2[3:2]
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: cycle == 2'h2 ? src2[3:2]
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: src2[1:0]);
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: src2[1:0]);
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assign shifted = (cycle == 2'h0 ? 16'h0 : {tmp_mul[13:0], 2'b00});
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assign shifted = (cycle == 2'h0 ? 16'h0 : {tmp_mul[13:0], 2'b00});
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assign mul_result = mul_result1 + shifted;
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assign mul_result = mul_result1 + shifted;
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assign des1 = mul_result[15:8];
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assign des1 = mul_result[15:8];
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assign des2 = mul_result[7:0];
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assign des2 = mul_result[7:0];
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assign desOv = src2 != 8'h0;
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assign desOv = | des1;
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) begin
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if (rst) begin
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cycle <= #1 2'b0;
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cycle <= #1 2'b0;
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