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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_psw.v] - Diff between revs 22 and 27
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| Rev 22 |
Rev 27 |
| Line 134... |
Line 134... |
always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst) bit_out <= #1 1'b0;
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if (rst) bit_out <= #1 1'b0;
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else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin
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else if ((rd_addr==wr_addr[2:0]) & wr & wr_bit) begin
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bit_out <= #1 cy_in;
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bit_out <= #1 cy_in;
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end else if ((wr_addr[7:3]==`OC8051_SFR_PSW) & wr & !wr_bit) begin
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end else if ((wr_addr==`OC8051_SFR_PSW) & wr & !wr_bit) begin
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bit_out <= #1 data_in[rd_addr];
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bit_out <= #1 data_in[rd_addr];
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end else bit_out <= #1 data_out[rd_addr];
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end else bit_out <= #1 data_out[rd_addr];
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end
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end
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endmodule
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endmodule
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