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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2003/01/13 14:14:41 simont
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// replace some modules
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//
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// Revision 1.4 2002/09/30 17:33:59 simont
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// Revision 1.4 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_ram_top (clk, rst, rd_addr, rd_data, wr_addr, bit_addr, wr_data, wr, bit_data_in, bit_data_out);
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module oc8051_ram_top (clk, rst, rd_addr, rd_data, wr_addr, bit_addr, wr_data, wr, bit_data_in, bit_data_out);
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// on-chip ram-size (2**ram_aw bytes)
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parameter ram_aw = 8; // default 256 bytes
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//
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//
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// clk (in) clock
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// clk (in) clock
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// rd_addr (in) read addres [oc8051_ram_rd_sel.out]
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// rd_addr (in) read addres [oc8051_ram_rd_sel.out]
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// rd_data (out) read data [oc8051_ram_sel.in_ram]
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// rd_data (out) read data [oc8051_ram_sel.in_ram]
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// wr_addr (in) write addres [oc8051_ram_wr_sel.out]
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// wr_addr (in) write addres [oc8051_ram_wr_sel.out]
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reg [2:0] bit_select;
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reg [2:0] bit_select;
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assign bit_data_out = rd_data[bit_select];
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assign bit_data_out = rd_data[bit_select];
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/*
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oc8051_ram oc8051_ram1(.clk(clk), .rst(rst), .rd_addr(rd_addr_m), .rd_data(rd_data), .wr_addr(wr_addr_m),
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oc8051_ram oc8051_ram1(.clk(clk), .rst(rst), .rd_addr(rd_addr_m), .rd_data(rd_data), .wr_addr(wr_addr_m),
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.wr_data(wr_data_m), .wr(wr));
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.wr_data(wr_data_m), .wr(wr));
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*/
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generic_dpram #(ram_aw, 8) oc8051_ram1(
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.rclk ( clk ),
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.rrst ( rst ),
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.rce ( 1'b1 ),
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.oe ( 1'b1 ),
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.raddr ( rd_addr_m ),
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.do ( rd_data ),
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.wclk ( clk ),
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.wrst ( rst ),
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.wce ( 1'b1 ),
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.we ( wr ),
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.waddr ( wr_addr_m ),
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.di ( wr_data_m )
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);
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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bit_addr_r <= #1 1'b0;
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bit_addr_r <= #1 1'b0;
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end else begin
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end else begin
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bit_addr_r <= #1 bit_addr;
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bit_addr_r <= #1 bit_addr;
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bit_select <= #1 rd_addr[2:0];
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bit_select <= #1 rd_addr[2:0];
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end
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end
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always @(rd_addr or bit_addr)
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always @(rd_addr or bit_addr)
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begin
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casex ( {bit_addr, rd_addr[7]} ) // synopsys full_case parallel_case
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case ({bit_addr, rd_addr[7]})
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2'b0?: rd_addr_m = rd_addr;
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2'b10: rd_addr_m = {4'b0010, rd_addr[6:3]};
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2'b10: rd_addr_m = {4'b0010, rd_addr[6:3]};
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2'b11: rd_addr_m = {1'b1, rd_addr[6:3], 3'b000};
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2'b11: rd_addr_m = {1'b1, rd_addr[6:3], 3'b000};
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default: rd_addr_m = rd_addr;
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endcase
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endcase
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end
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always @(wr_addr or bit_addr_r)
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always @(wr_addr or bit_addr_r)
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begin
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casex ( {bit_addr_r, wr_addr[7]} ) // synopsys full_case parallel_case
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casex ({bit_addr_r, wr_addr[7]})
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2'b0?: wr_addr_m = wr_addr;
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2'b10: wr_addr_m = {8'h00, 4'b0010, wr_addr[6:3]};
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2'b10: wr_addr_m = {8'h00, 4'b0010, wr_addr[6:3]};
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2'b11: wr_addr_m = {8'h00, 1'b1, wr_addr[6:3], 3'b000};
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2'b11: wr_addr_m = {8'h00, 1'b1, wr_addr[6:3], 3'b000};
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default: wr_addr_m = wr_addr;
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endcase
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endcase
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end
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always @(rd_data or bit_select or bit_data_in or wr_data or bit_addr_r)
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always @(rd_data or bit_select or bit_data_in or wr_data or bit_addr_r)
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begin
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casex ( {bit_addr_r, bit_select} ) // synopsys full_case parallel_case
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if (bit_addr_r) begin
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4'b0_???: wr_data_m = wr_data;
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case (bit_select)
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4'b1_000: wr_data_m = {rd_data[7:1], bit_data_in};
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3'b000: wr_data_m = {rd_data[7:1], bit_data_in};
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4'b1_001: wr_data_m = {rd_data[7:2], bit_data_in, rd_data[0]};
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3'b001: wr_data_m = {rd_data[7:2], bit_data_in, rd_data[0]};
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4'b1_010: wr_data_m = {rd_data[7:3], bit_data_in, rd_data[1:0]};
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3'b010: wr_data_m = {rd_data[7:3], bit_data_in, rd_data[1:0]};
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4'b1_011: wr_data_m = {rd_data[7:4], bit_data_in, rd_data[2:0]};
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3'b011: wr_data_m = {rd_data[7:4], bit_data_in, rd_data[2:0]};
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4'b1_100: wr_data_m = {rd_data[7:5], bit_data_in, rd_data[3:0]};
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3'b100: wr_data_m = {rd_data[7:5], bit_data_in, rd_data[3:0]};
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4'b1_101: wr_data_m = {rd_data[7:6], bit_data_in, rd_data[4:0]};
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3'b101: wr_data_m = {rd_data[7:6], bit_data_in, rd_data[4:0]};
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4'b1_110: wr_data_m = {rd_data[7], bit_data_in, rd_data[5:0]};
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3'b110: wr_data_m = {rd_data[7], bit_data_in, rd_data[5:0]};
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4'b1_111: wr_data_m = {bit_data_in, rd_data[6:0]};
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default: wr_data_m = {bit_data_in, rd_data[6:0]};
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endcase
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endcase
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end else
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wr_data_m = wr_data;
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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