| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2003/04/07 14:58:02 simont
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// change sfr's interface.
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//
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// Revision 1.6 2003/04/07 13:29:16 simont
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// Revision 1.6 2003/04/07 13:29:16 simont
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// change uart to meet timing.
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// change uart to meet timing.
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//
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//
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// Revision 1.5 2003/04/04 10:35:07 simont
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// Revision 1.5 2003/04/04 10:35:07 simont
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// signal prsc_ow added.
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// signal prsc_ow added.
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| Line 69... |
Line 72... |
// synopsys translate_on
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// synopsys translate_on
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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module oc8051_sfr (rst, clk, adr0, adr1, dat0, dat1, dat2, we, bit_in, bit_out, wr_bit,
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module oc8051_sfr (rst, clk,
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adr0, adr1, dat0,
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dat1, dat2,
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we, bit_in, wr_bit,
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bit_out,
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wr_sfr, acc, ram_wr_sel, ram_rd_sel, sp, sp_w, bank_sel, desAc, desOv, psw_set, srcAc, cy, rmw,
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wr_sfr, acc, ram_wr_sel, ram_rd_sel, sp, sp_w, bank_sel, desAc, desOv, psw_set, srcAc, cy, rmw,
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p0_out, p1_out, p2_out, p3_out, p0_in, p1_in, p2_in, p3_in, rxd, txd, int_ack, intr, int0,
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p0_out, p1_out, p2_out, p3_out, p0_in, p1_in, p2_in, p3_in, rxd, txd, int_ack, intr, int0,
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int1, reti, int_src, t0, t1, dptr_hi, dptr_lo, t2, t2ex);
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int1, reti, int_src, t0, t1, dptr_hi, dptr_lo, t2, t2ex,
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wait_data);
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//
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//
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// rst (in) reset - pin
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// rst (in) reset - pin
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// clk (in) clock - pin
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// clk (in) clock - pin
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// adr0, adr1 (in) address input
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// adr0, adr1 (in) address input
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// dat0 (out) data output
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// dat0 (out) data output
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| Line 149... |
Line 157... |
input int_ack, int0, int1, reti, wr_bit, t0, t1;
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input int_ack, int0, int1, reti, wr_bit, t0, t1;
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input [1:0] psw_set;
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input [1:0] psw_set;
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input [2:0] ram_rd_sel, ram_wr_sel, wr_sfr;
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input [2:0] ram_rd_sel, ram_wr_sel, wr_sfr;
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input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in;
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input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in;
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output bit_out, txd, intr, srcAc, cy;
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output bit_out, txd, intr, srcAc, cy, wait_data;
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output [1:0] bank_sel;
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output [1:0] bank_sel;
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output [7:0] dat0, p0_out, p1_out, p2_out, p3_out, int_src, dptr_hi, dptr_lo, acc;
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output [7:0] dat0, p0_out, p1_out, p2_out, p3_out, int_src, dptr_hi, dptr_lo, acc;
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output [7:0] sp, sp_w;
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output [7:0] sp, sp_w;
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reg bit_out;
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reg bit_out, wait_data;
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reg [7:0] dat0, adr0_r;
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reg [7:0] dat0, adr0_r;
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reg wr_bit_r;
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reg wr_bit_r;
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reg [2:0] ram_wr_sel_r;
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reg [2:0] ram_wr_sel_r;
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| Line 183... |
Line 191... |
// stack
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// stack
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sp_out;
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sp_out;
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wire pres_ow;
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wire pres_ow;
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assign cy = psw[7];
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assign cy = psw[7];
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assign srcAc = psw [6];
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assign srcAc = psw [6];
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| Line 280... |
Line 289... |
always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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adr0_r <= #1 8'h00;
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adr0_r <= #1 8'h00;
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ram_wr_sel_r <= #1 3'b000;
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ram_wr_sel_r <= #1 3'b000;
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wr_bit_r <= #1 1'b0;
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wr_bit_r <= #1 1'b0;
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// wait_data <= #1 1'b0;
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end else begin
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end else begin
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adr0_r <= #1 adr0;
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adr0_r <= #1 adr0;
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ram_wr_sel_r <= #1 ram_wr_sel;
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ram_wr_sel_r <= #1 ram_wr_sel;
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wr_bit_r <= #1 wr_bit;
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wr_bit_r <= #1 wr_bit;
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end
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end
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/*
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//
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//set output in case of address (byte)
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always @(adr0_r or psw or acc or dptr_hi or dptr_lo or b_reg or
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//ports
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p0_data or p1_data or p2_data or p3_data or
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//interrupt control
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ie or tcon or ip or
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// t/c 2
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t2con or tl2 or th2 or rcap2l or rcap2h or
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// t/c 0,1
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tmod or tl0 or th0 or tl1 or th1 or
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// serial interface
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scon or pcon or sbuf or
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// stack
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sp_out)
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begin
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case (adr0_r)
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`OC8051_SFR_ACC: dat0 = acc;
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`OC8051_SFR_PSW: dat0 = psw;
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`OC8051_SFR_P0: dat0 = p0_data;
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`OC8051_SFR_P1: dat0 = p1_data;
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`OC8051_SFR_P2: dat0 = p2_data;
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`OC8051_SFR_P3: dat0 = p3_data;
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`OC8051_SFR_SP: dat0 = sp_out;
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`OC8051_SFR_B: dat0 = b_reg;
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`OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
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`OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
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`OC8051_SFR_SCON: dat0 = scon;
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`OC8051_SFR_SBUF: dat0 = sbuf;
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`OC8051_SFR_PCON: dat0 = pcon;
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`OC8051_SFR_TH0: dat0 = th0;
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`OC8051_SFR_TH1: dat0 = th1;
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`OC8051_SFR_TL0: dat0 = tl0;
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`OC8051_SFR_TL1: dat0 = tl1;
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`OC8051_SFR_TMOD: dat0 = tmod;
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`OC8051_SFR_IP: dat0 = ip;
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`OC8051_SFR_IE: dat0 = ie;
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`OC8051_SFR_TCON: dat0 = tcon;
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`OC8051_SFR_RCAP2H: dat0 = rcap2h;
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`OC8051_SFR_RCAP2L: dat0 = rcap2l;
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`OC8051_SFR_TH2: dat0 = th2;
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`OC8051_SFR_TL2: dat0 = tl2;
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`OC8051_SFR_T2CON: dat0 = t2con;
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default: dat0 = 8'h00;
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endcase
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end
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//
|
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//set output in case of address (bit)
|
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always @(adr0_r or psw or acc or b_reg or
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//ports
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p0_data or p1_data or p2_data or p3_data or
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//interrupt control
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ie or tcon or ip or
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// t/c 2
|
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t2con or
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// serial interface
|
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scon)
|
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begin
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case (adr0_r[7:3])
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`OC8051_SFR_B_ACC: bit_out = acc[adr0_r[2:0]];
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`OC8051_SFR_B_PSW: bit_out = psw[adr0_r[2:0]];
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`OC8051_SFR_B_P0: bit_out = p0_data[adr0_r[2:0]];
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`OC8051_SFR_B_P1: bit_out = p1_data[adr0_r[2:0]];
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`OC8051_SFR_B_P2: bit_out = p2_data[adr0_r[2:0]];
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`OC8051_SFR_B_P3: bit_out = p3_data[adr0_r[2:0]];
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`OC8051_SFR_B_B: bit_out = b_reg[adr0_r[2:0]];
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`OC8051_SFR_B_IP: bit_out = ip[adr0_r[2:0]];
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`OC8051_SFR_B_IE: bit_out = ie[adr0_r[2:0]];
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`OC8051_SFR_B_TCON: bit_out = tcon[adr0_r[2:0]];
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`OC8051_SFR_B_SCON: bit_out = scon[adr0_r[2:0]];
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`OC8051_SFR_B_T2CON: bit_out = t2con[adr0_r[2:0]];
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default: bit_out = 1'b0;
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endcase
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end
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*/
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//
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//
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//set output in case of address (byte)
|
//set output in case of address (byte)
|
always @(adr0_r or psw or acc or dptr_hi or dptr_lo or b_reg or
|
always @(posedge clk or posedge rst)
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//ports
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p0_data or p1_data or p2_data or p3_data or
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//interrupt control
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ie or tcon or ip or
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// t/c 2
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t2con or tl2 or th2 or rcap2l or rcap2h or
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// t/c 0,1
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tmod or tl0 or th0 or tl1 or th1 or
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// serial interface
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scon or pcon or sbuf or
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// stack
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sp_out)
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begin
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begin
|
case (adr0_r)
|
if (rst) begin
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`OC8051_SFR_ACC: dat0 = acc;
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dat0 <= #1 8'h00;
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`OC8051_SFR_PSW: dat0 = psw;
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wait_data <= #1 1'b0;
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`OC8051_SFR_P0: dat0 = p0_data;
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/* end else if (((adr0==`OC8051_SFR_PSW) & (((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r)) |
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`OC8051_SFR_P1: dat0 = p1_data;
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(({adr1[7:3], 3'b000}==adr0) & we & wr_bit_r)) & !wait_data) begin
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`OC8051_SFR_P2: dat0 = p2_data;
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// dat0 <= #1 {dat1[7:1], p};
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`OC8051_SFR_P3: dat0 = p3_data;
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wait_data <= #1 1'b1;
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`OC8051_SFR_SP: dat0 = sp_out;
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end else if ((adr0==`OC8051_SFR_PSW) & (adr1==adr0) & we & !wr_bit_r & !wait_data) begin
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`OC8051_SFR_B: dat0 = b_reg;
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// dat0 <= #1 {dat1[7:1], p};
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`OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
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wait_data <= #1 1'b1;*/
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`OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
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end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
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`OC8051_SFR_SCON: dat0 = scon;
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dat0 <= #1 dat1;
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`OC8051_SFR_SBUF: dat0 = sbuf;
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wait_data <= #1 1'b0;
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`OC8051_SFR_PCON: dat0 = pcon;
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end else if (
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`OC8051_SFR_TH0: dat0 = th0;
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(((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) | //write to acc
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`OC8051_SFR_TH1: dat0 = th1;
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) | //write to dpl
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`OC8051_SFR_TL0: dat0 = tl0;
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((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_B)) | //write to b
|
`OC8051_SFR_TL1: dat0 = tl1;
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(adr1[7] & (adr1==adr0) & we & !wr_bit_r)) & !wait_data) begin //write and read same address
|
`OC8051_SFR_TMOD: dat0 = tmod;
|
// dat0 <= #1 dat1;
|
`OC8051_SFR_IP: dat0 = ip;
|
wait_data <= #1 1'b1;
|
`OC8051_SFR_IE: dat0 = ie;
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|
`OC8051_SFR_TCON: dat0 = tcon;
|
end else if (
|
`OC8051_SFR_RCAP2H: dat0 = rcap2h;
|
(((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) | //write to acc
|
`OC8051_SFR_RCAP2L: dat0 = rcap2l;
|
((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) | //write to dph
|
`OC8051_SFR_TH2: dat0 = th2;
|
((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_ACC))) & !wait_data) begin //write to b
|
`OC8051_SFR_TL2: dat0 = tl2;
|
// dat0 <= #1 dat2;
|
`OC8051_SFR_T2CON: dat0 = t2con;
|
wait_data <= #1 1'b1;
|
default: dat0 = 8'h00;
|
|
|
// else if (({adr1[7:3], 3'b000}==adr0_r) & we & wr_bit_r)
|
|
// dat0 <= #1 dat1;
|
|
end else begin
|
|
case (adr0)
|
|
`OC8051_SFR_ACC: dat0 <= #1 acc;
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|
`OC8051_SFR_PSW: dat0 <= #1 psw;
|
|
`OC8051_SFR_P0: dat0 <= #1 p0_data;
|
|
`OC8051_SFR_P1: dat0 <= #1 p1_data;
|
|
`OC8051_SFR_P2: dat0 <= #1 p2_data;
|
|
`OC8051_SFR_P3: dat0 <= #1 p3_data;
|
|
// `OC8051_SFR_SP: dat0 <= #1 sp_out;
|
|
`OC8051_SFR_SP: dat0 <= #1 sp;
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|
`OC8051_SFR_B: dat0 <= #1 b_reg;
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`OC8051_SFR_DPTR_HI: dat0 <= #1 dptr_hi;
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`OC8051_SFR_DPTR_LO: dat0 <= #1 dptr_lo;
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`OC8051_SFR_SCON: dat0 <= #1 scon;
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`OC8051_SFR_SBUF: dat0 <= #1 sbuf;
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`OC8051_SFR_PCON: dat0 <= #1 pcon;
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`OC8051_SFR_TH0: dat0 <= #1 th0;
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`OC8051_SFR_TH1: dat0 <= #1 th1;
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`OC8051_SFR_TL0: dat0 <= #1 tl0;
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|
`OC8051_SFR_TL1: dat0 <= #1 tl1;
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`OC8051_SFR_TMOD: dat0 <= #1 tmod;
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`OC8051_SFR_IP: dat0 <= #1 ip;
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|
`OC8051_SFR_IE: dat0 <= #1 ie;
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|
`OC8051_SFR_TCON: dat0 <= #1 tcon;
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|
`OC8051_SFR_RCAP2H: dat0 <= #1 rcap2h;
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`OC8051_SFR_RCAP2L: dat0 <= #1 rcap2l;
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`OC8051_SFR_TH2: dat0 <= #1 th2;
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`OC8051_SFR_TL2: dat0 <= #1 tl2;
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|
`OC8051_SFR_T2CON: dat0 <= #1 t2con;
|
|
default: dat0 <= #1 8'h00;
|
endcase
|
endcase
|
|
wait_data <= #1 1'b0;
|
|
end
|
end
|
end
|
|
|
|
|
//
|
//
|
//set output in case of address (bit)
|
//set output in case of address (bit)
|
always @(adr0_r or psw or acc or b_reg or
|
always @(posedge clk or posedge rst)
|
//ports
|
|
p0_data or p1_data or p2_data or p3_data or
|
|
//interrupt control
|
|
ie or tcon or ip or
|
|
// t/c 2
|
|
t2con or
|
|
// serial interface
|
|
scon)
|
|
begin
|
begin
|
case (adr0_r[7:3])
|
if (rst)
|
`OC8051_SFR_B_ACC: bit_out = acc[adr0_r[2:0]];
|
bit_out <= #1 1'h0;
|
`OC8051_SFR_B_PSW: bit_out = psw[adr0_r[2:0]];
|
else if (
|
`OC8051_SFR_B_P0: bit_out = p0_data[adr0_r[2:0]];
|
((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) |
|
`OC8051_SFR_B_P1: bit_out = p1_data[adr0_r[2:0]];
|
((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) | //write to acc
|
`OC8051_SFR_B_P2: bit_out = p2_data[adr0_r[2:0]];
|
((wr_sfr==`OC8051_WRS_BA) & (adr0[7:3]==`OC8051_SFR_B_B))) //write to b
|
`OC8051_SFR_B_P3: bit_out = p3_data[adr0_r[2:0]];
|
|
`OC8051_SFR_B_B: bit_out = b_reg[adr0_r[2:0]];
|
bit_out <= #1 dat1[adr0[2:0]];
|
`OC8051_SFR_B_IP: bit_out = ip[adr0_r[2:0]];
|
else if ((adr1==adr0) & we & wr_bit_r)
|
`OC8051_SFR_B_IE: bit_out = ie[adr0_r[2:0]];
|
bit_out <= #1 bit_in;
|
`OC8051_SFR_B_TCON: bit_out = tcon[adr0_r[2:0]];
|
else
|
`OC8051_SFR_B_SCON: bit_out = scon[adr0_r[2:0]];
|
case (adr0[7:3])
|
`OC8051_SFR_B_T2CON: bit_out = t2con[adr0_r[2:0]];
|
`OC8051_SFR_B_ACC: bit_out <= #1 acc[adr0[2:0]];
|
default: bit_out = 1'b0;
|
`OC8051_SFR_B_PSW: bit_out <= #1 psw[adr0[2:0]];
|
|
`OC8051_SFR_B_P0: bit_out <= #1 p0_data[adr0[2:0]];
|
|
`OC8051_SFR_B_P1: bit_out <= #1 p1_data[adr0[2:0]];
|
|
`OC8051_SFR_B_P2: bit_out <= #1 p2_data[adr0[2:0]];
|
|
`OC8051_SFR_B_P3: bit_out <= #1 p3_data[adr0[2:0]];
|
|
`OC8051_SFR_B_B: bit_out <= #1 b_reg[adr0[2:0]];
|
|
`OC8051_SFR_B_IP: bit_out <= #1 ip[adr0[2:0]];
|
|
`OC8051_SFR_B_IE: bit_out <= #1 ie[adr0[2:0]];
|
|
`OC8051_SFR_B_TCON: bit_out <= #1 tcon[adr0[2:0]];
|
|
`OC8051_SFR_B_SCON: bit_out <= #1 scon[adr0[2:0]];
|
|
`OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
|
|
default: bit_out <= #1 1'b0;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
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No newline at end of file
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No newline at end of file
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