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//////////////////////////////////////////////////////////////////////
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//// ////
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//// 8051 cores timer/counter control ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// Description ////
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//// timers and counters handling for 8051 core ////
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//// ////
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//// To Do: ////
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//// Nothing ////
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//// ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// version 0.9
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//
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//clk clock (pin)
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//rst reset (pin)
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//sfr_sel address for selecting different registers (TMOD, TL0, TH0, TL1, TH1) (input)
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//data_in data input (input)
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//wr read/write signal (input)
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//ie0 condition signal (one of), must be low for T/C 0 to start counting (input)
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//ie1 condition signal (one of), must be low for T/C 1 to start counting (input)
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//tr0 signal which activates Timer/Counter 0 (input)
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//tr1 signal which activates Timer/Counter 1 (input)
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//t0 external signal that increases Counter 0 (input)
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//t1 external signal that increases Counter 1 (input)
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//data_out data output from the chosen register (TMOD, TL0, TH0, TL1, TH1) (output)
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//tf0 overflow flag for T/C 0 (output)
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//tf1 overflow flag for T/C 1 (output)
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//tmod register that describes T/C modes (internal)
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//tl0 T/C 0 register, lower eight bits (internal)
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//th0 T/C 0 register, higher eight bits (internal)
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//tl1 T/C 1 register, lower eight bits (internal)
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//th1 T/C 1 register, higher eight bits (internal)
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`include "oc8051_defines.v"
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`include "oc8051_defines.v"
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//synopsys translate_off
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//synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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