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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_tc2.v] - Diff between revs 81 and 112

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Rev 81 Rev 112
Line 42... Line 42... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.1  2003/01/13 14:13:12  simont
 
 
 
// initial import
 
 
 
//
 
//
 
//
 
//
 
//
 
 
 
 
 
`include "oc8051_defines.v"
 
`include "oc8051_defines.v"
 
 
 
 
Line 53... Line 56... 
`include "oc8051_timescale.v"
 
`include "oc8051_timescale.v"
 
//synopsys translate_on
 
//synopsys translate_on
 
 
 
 
 
 
 
 
 
 
 
 
 
module oc8051_tc2 (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, bit_in, t2, t2ex, data_out, bit_out,
 
module oc8051_tc2 (clk, rst,
 
            rclk, tclk, brate2, tc2_int);
 
            wr_addr, rd_addr,
 
 
 
            data_in, data_out, bit_out,
 
input [7:0] wr_addr, data_in, rd_addr;
 
            wr, wr_bit, bit_in,
 
input clk, rst, wr, wr_bit, t2, t2ex, bit_in;
 
            t2, t2ex,
 
 
 
            rclk, tclk,
 
 
 
            brate2, tc2_int,
 
 
 
            pres_ow);
 
 
 
 
 
 
 
input [7:0]  wr_addr,
 
 
 
             data_in,
 
 
 
             rd_addr;
 
 
 
input        clk,
 
 
 
             rst,
 
 
 
             wr,
 
 
 
             wr_bit,
 
 
 
             t2,
 
 
 
             t2ex,
 
 
 
             bit_in,
 
 
 
             pres_ow;   //prescalre owerflov
 
output [7:0] data_out;
 
output [7:0] data_out;
 
output tc2_int, bit_out, rclk, tclk, brate2;
 
output       tc2_int,
 
 
 
             bit_out,
 
 
 
             rclk,
 
 
 
             tclk,
 
 
 
             brate2;
 
 
 
 
 
reg [7:0] data_out;
 
reg [7:0] data_out;
 
 
 
 
 
reg brate2;
 
reg brate2;
 
reg [7:0] t2con, t2mod, tl2, th2, rcap2l, rcap2h;
 
reg [7:0] t2con, tl2, th2, rcap2l, rcap2h;
 
 
 
 
 
reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;
 
reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;
 
 
 
 
 
wire run;
 
wire run;
 
 
 
 
 
wire dcen;
 
 
 
assign dcen = t2mod[0];
 
 
 
 
 
 
 
//
 
//
 
// t2con
 
// t2con
 
wire tf2, exf2, exen2, tr2, ct2, cprl2;
 
wire tf2, exf2, exen2, tr2, ct2, cprl2;
 
 
 
 
 
assign tc2_int = tf2 | exf2;
 
assign tc2_int = tf2 | exf2;
Line 98... Line 118... 
    t2con <= #1 data_in;
 
    t2con <= #1 data_in;
 
  end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
 
  end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
 
    t2con[wr_addr[2:0]] <= #1 bit_in;
 
    t2con[wr_addr[2:0]] <= #1 bit_in;
 
  end else if (tf2_set) begin
 
  end else if (tf2_set) begin
 
    t2con[7] <= #1 1'b1;
 
    t2con[7] <= #1 1'b1;
 
//auto reload mode, dcen=1 : toggle exf2;
 
  end else if (exen2 & neg_trans) begin
 
    if (!(rclk | tclk) & !cprl2 & dcen)
 
    t2con[6] <= #1 1'b1;
 
      t2con[6] <= #1 !t2con[6];
 
 
 
  end else if (exen2 & (rclk | tclk | cprl2 | !dcen) & neg_trans) begin
 
 
 
    t2con <= #1 {t2con[7], 1'b1, t2con[5:0]};
 
 
 
  end
 
  end
 
end
 
end
 
 
 
 
 
 
 
 
 
//
 
//
 
// t2mod
 
 
 
 
 
 
 
always @(posedge clk or posedge rst)
 
 
 
begin
 
 
 
  if (rst) begin
 
 
 
    t2mod <= #1 `OC8051_RST_T2MOD;
 
 
 
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2MOD)) begin
 
 
 
    t2mod <= #1 data_in;
 
 
 
  end
 
 
 
end
 
 
 
 
 
 
 
//
 
 
 
//th2, tl2
 
//th2, tl2
 
assign run = tr2 & (!ct2 | (ct2 & tc2_event));
 
assign run = tr2 & ((!ct2 & pres_ow) | (ct2 & tc2_event));
 
 
 
 
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or posedge rst)
 
begin
 
begin
 
  if (rst) begin
 
  if (rst) begin
 
//
 
//
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  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
 
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
 
//
 
//
 
// write to timer 2 low
 
// write to timer 2 low
 
//
 
//
 
    tl2 <= #1 data_in;
 
    tl2 <= #1 data_in;
 
  end else if (!(rclk | tclk) & !cprl2 & exen2 & !dcen) begin
 
  end else if (!(rclk | tclk) & !cprl2 & exen2 & neg_trans) begin
 
//
 
//
 
// avto reload mode, exen2=1, 0-1 transition on t2ex pin
 
// avto reload mode, exen2=1, 0-1 transition on t2ex pin
 
//
 
//
 
    th2 <= #1 rcap2h;
 
    th2 <= #1 rcap2h;
 
    tl2 <= #1 rcap2l;
 
    tl2 <= #1 rcap2l;
Line 168... Line 173... 
    end else if (cprl2) begin
 
    end else if (cprl2) begin
 
//
 
//
 
// capture mode
 
// capture mode
 
//
 
//
 
      {tf2_set, th2, tl2}  <= #1 {1'b0, th2, tl2} + 17'h1;
 
      {tf2_set, th2, tl2}  <= #1 {1'b0, th2, tl2} + 17'h1;
 
    end else if (!dcen | t2ex) begin
 
    end else begin
 
//
 
//
 
// auto reload mode, up counter
 
// auto reload mode
 
//
 
//
 
      if (&{th2, tl2}) begin
 
      if (&{th2, tl2}) begin
 
        th2 <= #1 rcap2h;
 
        th2 <= #1 rcap2h;
 
        tl2 <= #1 rcap2l;
 
        tl2 <= #1 rcap2l;
 
        tf2_set <= #1 1'b1;
 
        tf2_set <= #1 1'b1;
 
      end else begin
 
      end else begin
 
        {tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
 
        {tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
 
      end
 
      end
 
    end else begin
 
 
 
//
 
 
 
// auto reload mode, down counter
 
 
 
//
 
 
 
      if ({th2, tl2}=={rcap2h, rcap2l}) begin
 
 
 
        th2 <= #1 8'hff;
 
 
 
        tl2 <= #1 8'hff;
 
 
 
        tf2_set <= #1 1'b1;
 
 
 
      end else begin
 
 
 
        {tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} - 17'h1;
 
 
 
      end
 
 
 
    end
 
    end
 
  end else tf2_set <= #1 1'b0;
 
  end else tf2_set <= #1 1'b0;
 
end
 
end
 
 
 
 
 
 
 
 
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  end else begin
 
  end else begin
 
    tc2_event <= #1 1'b0;
 
    tc2_event <= #1 1'b0;
 
  end
 
  end
 
end
 
end
 
 
 
 
 
always @(rd_addr or t2con or t2mod or tl2 or th2 or rcap2l or rcap2h)
 
always @(rd_addr or t2con or tl2 or th2 or rcap2l or rcap2h)
 
begin
 
begin
 
  case (rd_addr)
 
  case (rd_addr)
 
    `OC8051_SFR_RCAP2H: data_out = rcap2h;
 
    `OC8051_SFR_RCAP2H: data_out = rcap2h;
 
    `OC8051_SFR_RCAP2L: data_out = rcap2l;
 
    `OC8051_SFR_RCAP2L: data_out = rcap2l;
 
    `OC8051_SFR_TH2:    data_out = th2;
 
    `OC8051_SFR_TH2:    data_out = th2;
 
    `OC8051_SFR_TL2:    data_out = tl2;
 
    `OC8051_SFR_TL2:    data_out = tl2;
 
    `OC8051_SFR_T2MOD:  data_out = t2mod;
 
 
 
    default:            data_out = t2con;
 
    default:            data_out = t2con;
 
  endcase
 
  endcase
 
 
 
 
 
end
 
end
 
 
 
 

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