| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.22 2003/04/09 16:24:04 simont
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// change wr_sft to 2 bit wire.
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//
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// Revision 1.21 2003/04/09 15:49:42 simont
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// Revision 1.21 2003/04/09 15:49:42 simont
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// Register oc8051_sfr dato output, add signal wait_data.
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// Register oc8051_sfr dato output, add signal wait_data.
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//
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//
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// Revision 1.20 2003/04/03 19:13:28 simont
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// Revision 1.20 2003/04/03 19:13:28 simont
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// Include instruction cache.
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// Include instruction cache.
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| Line 78... |
Line 81... |
// synopsys translate_on
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// synopsys translate_on
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module oc8051_top (wb_rst_i, wb_clk_i,
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module oc8051_top (wb_rst_i, wb_clk_i,
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//interface to instruction rom
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//interface to instruction rom
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wbi_adr_o, wbi_dat_i, wbi_stb_o, wbi_ack_i, wbi_cyc_o, wbi_err_i,
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wbi_adr_o,
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wbi_dat_i,
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wbi_stb_o,
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wbi_ack_i,
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wbi_cyc_o,
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wbi_err_i,
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|
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//interface to data ram
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//interface to data ram
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wbd_dat_i, wbd_dat_o,
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wbd_dat_i,
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wbd_adr_o, wbd_we_o, wbd_ack_i, wbd_stb_o, wbd_cyc_o, wbd_err_i,
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wbd_dat_o,
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wbd_adr_o,
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wbd_we_o,
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wbd_ack_i,
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wbd_stb_o,
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wbd_cyc_o,
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wbd_err_i,
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|
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// interrupt interface
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// interrupt interface
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int0_i, int1_i,
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int0_i,
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int1_i,
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// external access (active low)
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// external access (active low)
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ea_in,
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ea_in,
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|
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// port interface
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// port interface
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p0_i, p1_i, p2_i, p3_i,
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`ifdef OC8051_PORTS
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p0_o, p1_o, p2_o, p3_o,
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`ifdef OC8051_PORT0
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p0_i,
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p0_o,
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`endif
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`ifdef OC8051_PORT1
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p1_i,
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p1_o,
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`endif
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|
|
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`ifdef OC8051_PORT2
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p2_i,
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p2_o,
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`endif
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|
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`ifdef OC8051_PORT3
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p3_i,
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p3_o,
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`endif
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`endif
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// serial interface
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// serial interface
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`ifdef OC8051_UART
|
rxd_i, txd_o,
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rxd_i, txd_o,
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`endif
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|
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// counter interface
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// counter interface
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t0_i, t1_i, t2_i, t2ex_i);
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`ifdef OC8051_TC01
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t0_i, t1_i,
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`endif
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`ifdef OC8051_TC2
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t2_i, t2ex_i
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`endif
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);
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|
|
|
|
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input wb_rst_i, // reset input
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input wb_rst_i, // reset input
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wb_clk_i, // clock input
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wb_clk_i, // clock input
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int0_i, // interrupt 0
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int0_i, // interrupt 0
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int1_i, // interrupt 1
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int1_i, // interrupt 1
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ea_in, // external access
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ea_in, // external access
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rxd_i, // receive
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t0_i, // counter 0 input
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t1_i, // counter 1 input
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wbd_ack_i, // data acknowalge
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wbd_ack_i, // data acknowalge
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wbi_ack_i, // instruction acknowlage
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wbi_ack_i, // instruction acknowlage
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wbd_err_i, // data error
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wbd_err_i, // data error
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wbi_err_i, // instruction error
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wbi_err_i; // instruction error
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t2_i, // counter 2 input
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t2ex_i; // ???
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input [7:0] wbd_dat_i; // ram data input
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input [7:0] wbd_dat_i, // ram data input
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p0_i, // port 0 input
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p1_i, // port 1 input
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p2_i, // port 2 input
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p3_i; // port 3 input
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input [31:0] wbi_dat_i; // rom data input
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input [31:0] wbi_dat_i; // rom data input
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|
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output wbd_we_o, // data write enable
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output wbd_we_o, // data write enable
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txd_o, // transnmit
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wbd_stb_o, // data strobe
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wbd_stb_o, // data strobe
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wbd_cyc_o, // data cycle
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wbd_cyc_o, // data cycle
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wbi_stb_o, // instruction strobe
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wbi_stb_o, // instruction strobe
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wbi_cyc_o; // instruction cycle
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wbi_cyc_o; // instruction cycle
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|
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output [7:0] wbd_dat_o, // data output
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output [7:0] wbd_dat_o; // data output
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p0_o, // port 0 output
|
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p1_o, // port 1 output
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p2_o, // port 2 output
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p3_o; // port 3 output
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|
|
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output [15:0] wbd_adr_o, // data address
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output [15:0] wbd_adr_o, // data address
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wbi_adr_o; // instruction address
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wbi_adr_o; // instruction address
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|
|
|
`ifdef OC8051_PORTS
|
|
|
|
`ifdef OC8051_PORT0
|
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input [7:0] p0_i; // port 0 input
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output [7:0] p0_o; // port 0 output
|
|
`endif
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|
|
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`ifdef OC8051_PORT1
|
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input [7:0] p1_i; // port 1 input
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output [7:0] p1_o; // port 1 output
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|
`endif
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|
|
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`ifdef OC8051_PORT2
|
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input [7:0] p2_i; // port 2 input
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output [7:0] p2_o; // port 2 output
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|
`endif
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|
|
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`ifdef OC8051_PORT3
|
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input [7:0] p3_i; // port 3 input
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output [7:0] p3_o; // port 3 output
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`endif
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`endif
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|
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wire [7:0] op1_i, op2_i, op3_i, dptr_hi, dptr_lo, ri, rn_mem, data_out;
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wire [7:0] op1, op2, op3;
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wire [7:0] acc, p0_out, p1_out, p2_out, p3_out;
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wire [7:0] sp, sp_w;
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|
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`ifdef OC8051_UART
|
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input rxd_i; // receive
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output txd_o; // transnmit
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`endif
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`ifdef OC8051_TC01
|
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input t0_i, // counter 0 input
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t1_i; // counter 1 input
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|
`endif
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|
|
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`ifdef OC8051_TC2
|
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input t2_i, // counter 2 input
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t2ex_i; //
|
|
`endif
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|
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wire [7:0] op1_i,
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op2_i,
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op3_i,
|
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dptr_hi,
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dptr_lo,
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ri,
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rn_mem,
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data_out,
|
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op1,
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op2,
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op3,
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acc,
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p0_out,
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p1_out,
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p2_out,
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p3_out,
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sp,
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sp_w;
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wire [15:0] pc;
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wire [15:0] pc;
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assign wbd_cyc_o = wbd_stb_o;
|
assign wbd_cyc_o = wbd_stb_o;
|
//assign wbi_cyc_o = wbi_stb_o;
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|
|
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//
|
|
// ram_rd_sel ram read (internal)
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// ram_wr_sel ram write (internal)
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|
// src_sel1, src_sel2 from decoder to register
|
|
wire src_sel3;
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wire src_sel3;
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wire [1:0] wr_sfr;
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wire [1:0] wr_sfr;
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wire [2:0] ram_rd_sel, ram_wr_sel;
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wire [2:0] ram_rd_sel, // ram read
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wire [2:0] src_sel2, src_sel1;
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ram_wr_sel, // ram write
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src_sel2,
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//
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src_sel1;
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// wr_addr ram write addres
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// ram_out data from ram
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wire [7:0] ram_data,
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// rd_addr data ram read addres
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ram_out, //data from ram
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// rd_addr_r data ram read addres registerd
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sfr_out,
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wire [7:0] ram_data, ram_out, sfr_out, wr_dat;
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wr_dat,
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wire [7:0] wr_addr, rd_addr;
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wr_addr, //ram write addres
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rd_addr; //data ram read addres
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wire sfr_bit;
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wire sfr_bit;
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|
|
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wire [1:0] cy_sel, //carry select; from decoder to cy_selct1
|
//
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bank_sel;
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// cy_sel carry select; from decoder to cy_selct1
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wire rom_addr_sel, //rom addres select; alu or pc
|
// rom_addr_sel rom addres select; alu or pc
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rmw,
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// ext_adddr_sel external addres select; data pointer or Ri
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ea_int;
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// write_p output from decoder; write to external ram, go to register;
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wire [1:0] cy_sel, bank_sel;
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wire reti,
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wire rom_addr_sel, rmw, ea_int;
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intr,
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int_ack,
|
//
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istb;
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// int_uart interrupt from uart
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// tf0 interrupt from t/c 0
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// tf1 interrupt from t/c 1
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// tr0 timer 0 run
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// tr1 timer 1 run
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wire reti, intr, int_ack, istb;
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wire [7:0] int_src;
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wire [7:0] int_src;
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//
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//alu_op alu operation (from decoder)
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//psw_set write to psw or not; from decoder to psw (through register)
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wire mem_wait;
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wire mem_wait;
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wire [2:0] mem_act;
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wire [2:0] mem_act;
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wire [3:0] alu_op;
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wire [3:0] alu_op; //alu operation (from decoder)
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wire [1:0] psw_set;
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wire [1:0] psw_set; //write to psw or not; from decoder to psw (through register)
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//
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// immediate1_r from imediate_sel1 to alu_src1_sel1
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// immediate2_r from imediate_sel1 to alu_src2_sel1
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// src1. src2, src2 alu sources
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// des2, des2 alu destinations
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// des1_r destination 1 registerd (to comp1)
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// desCy carry out
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// desAc
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// desOv overflow
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// wr write to data ram
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wire [7:0] src1, src2, des1, des2, des1_r;
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wire [7:0] src3;
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wire desCy, desAc, desOv, alu_cy, wr, wr_o;
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|
|
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//
|
wire [7:0] src1, //alu sources 1
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// rd read program rom
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src2, //alu sources 2
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// pc_wr_sel program counter write select (from decoder to pc)
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src3, //alu sources 3
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wire rd, pc_wr;
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des1, //alu destination 1
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wire [2:0] pc_wr_sel;
|
des2, //alu destinations 2
|
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des1_r; //destination 1 registerd (to comp1)
|
//
|
wire desCy, //carry out
|
// op1_n from op_select to decoder
|
desAc,
|
// op2_n, output of op_select, to immediate_sel1, pc1, comp1
|
desOv, //overflow
|
// op3_n, output of op_select, to immediate_sel1, ram_wr_sel1
|
alu_cy,
|
// op2_dr, output of op_select, to ram_rd_sel1, ram_wr_sel1
|
wr, //write to data ram
|
wire [7:0] op1_n, op2_n, op3_n;
|
wr_o;
|
|
|
//
|
wire rd, //read program rom
|
// comp_sel select source1 and source2 to compare
|
pc_wr;
|
// eq result (from comp1 to decoder)
|
wire [2:0] pc_wr_sel; //program counter write select (from decoder to pc)
|
wire [1:0] comp_sel;
|
|
wire eq, srcAc, cy, rd_ind, wr_ind;
|
wire [7:0] op1_n, //from memory_interface to decoder
|
|
op2_n,
|
|
op3_n;
|
|
|
|
wire [1:0] comp_sel; //select source1 and source2 to compare
|
|
wire eq, //result (from comp1 to decoder)
|
|
srcAc,
|
|
cy,
|
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rd_ind,
|
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wr_ind;
|
wire [2:0] op1_cur;
|
wire [2:0] op1_cur;
|
|
|
|
wire bit_addr, //bit addresable instruction
|
//
|
bit_data, //bit data from ram to ram_select
|
// bit_addr bit addresable instruction
|
bit_out, //bit data from ram_select to alu and cy_select
|
// bit_data bit data from ram to ram_select
|
bit_addr_o,
|
// bit_out bit data from ram_select to alu and cy_select
|
wait_data;
|
wire bit_addr, bit_data, bit_out, bit_addr_o;
|
|
|
|
//
|
//
|
// cpu to cache/wb_interface
|
// cpu to cache/wb_interface
|
wire iack_i,
|
wire iack_i,
|
istb_o,
|
istb_o,
|
icyc_o;
|
icyc_o;
|
wire [31:0] idat_i;
|
wire [31:0] idat_i;
|
wire [15:0] iadr_o;
|
wire [15:0] iadr_o;
|
wire wait_data;
|
|
|
|
|
|
//
|
//
|
// decoder
|
// decoder
|
oc8051_decoder oc8051_decoder1(.clk(wb_clk_i), .rst(wb_rst_i), .op_in(op1_n), .op1_c(op1_cur),
|
oc8051_decoder oc8051_decoder1(.clk(wb_clk_i),
|
.ram_rd_sel_o(ram_rd_sel), .ram_wr_sel_o(ram_wr_sel), .bit_addr(bit_addr),
|
.rst(wb_rst_i),
|
.src_sel1(src_sel1), .src_sel2(src_sel2),
|
.op_in(op1_n),
|
.src_sel3(src_sel3), .alu_op_o(alu_op), .psw_set(psw_set),
|
.op1_c(op1_cur),
|
.cy_sel(cy_sel), .wr_o(wr), .pc_wr(pc_wr),
|
.ram_rd_sel_o(ram_rd_sel),
|
.pc_sel(pc_wr_sel), .comp_sel(comp_sel), .eq(eq),
|
.ram_wr_sel_o(ram_wr_sel),
|
.wr_sfr_o(wr_sfr), .rd(rd), .rmw(rmw),
|
.bit_addr(bit_addr),
|
.istb(istb), .mem_act(mem_act), .mem_wait(mem_wait),
|
|
|
.src_sel1(src_sel1),
|
|
.src_sel2(src_sel2),
|
|
.src_sel3(src_sel3),
|
|
|
|
.alu_op_o(alu_op),
|
|
.psw_set(psw_set),
|
|
.cy_sel(cy_sel),
|
|
.wr_o(wr),
|
|
.pc_wr(pc_wr),
|
|
.pc_sel(pc_wr_sel),
|
|
.comp_sel(comp_sel),
|
|
.eq(eq),
|
|
.wr_sfr_o(wr_sfr),
|
|
.rd(rd),
|
|
.rmw(rmw),
|
|
.istb(istb),
|
|
.mem_act(mem_act),
|
|
.mem_wait(mem_wait),
|
.wait_data(wait_data));
|
.wait_data(wait_data));
|
|
|
|
|
//
|
//
|
//alu
|
//alu
|
oc8051_alu oc8051_alu1(.rst(wb_rst_i), .clk(wb_clk_i), .op_code(alu_op), .rd(rd),
|
oc8051_alu oc8051_alu1(.rst(wb_rst_i),
|
.src1(src1), .src2(src2), .src3(src3), .srcCy(alu_cy), .srcAc(srcAc),
|
.clk(wb_clk_i),
|
.des1(des1), .des2(des2), .des1_r(des1_r), .desCy(desCy),
|
.op_code(alu_op),
|
.desAc(desAc), .desOv(desOv), .bit_in(bit_out));
|
.rd(rd),
|
|
.src1(src1),
|
|
.src2(src2),
|
|
.src3(src3),
|
|
.srcCy(alu_cy),
|
|
.srcAc(srcAc),
|
|
.des1(des1),
|
|
.des2(des2),
|
|
.des1_r(des1_r),
|
|
.desCy(desCy),
|
|
.desAc(desAc),
|
|
.desOv(desOv),
|
|
.bit_in(bit_out));
|
|
|
//
|
//
|
//data ram
|
//data ram
|
oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i), .rst(wb_rst_i), .rd_addr(rd_addr), .rd_data(ram_data),
|
oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i),
|
.wr_addr(wr_addr), .bit_addr(bit_addr_o), .wr_data(wr_dat), .wr(wr_o && (!wr_addr[7] || wr_ind)),
|
.rst(wb_rst_i),
|
.bit_data_in(desCy), .bit_data_out(bit_data));
|
.rd_addr(rd_addr),
|
|
.rd_data(ram_data),
|
|
.wr_addr(wr_addr),
|
|
.bit_addr(bit_addr_o),
|
|
.wr_data(wr_dat),
|
|
.wr(wr_o && (!wr_addr[7] || wr_ind)),
|
|
.bit_data_in(desCy),
|
|
.bit_data_out(bit_data));
|
|
|
//
|
//
|
|
|
oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i), .rst(wb_rst_i), .rd(rd),
|
oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i),
|
.sel1(src_sel1), .sel2(src_sel2), .sel3(src_sel3),
|
.rst(wb_rst_i),
|
.acc(acc), .ram(ram_out), .pc(pc), .dptr({dptr_hi, dptr_lo}),
|
.rd(rd),
|
.op1(op1_n), .op2(op2_n), .op3(op3_n),
|
|
.src1(src1), .src2(src2), .src3(src3));
|
.sel1(src_sel1),
|
|
.sel2(src_sel2),
|
|
.sel3(src_sel3),
|
|
|
|
.acc(acc),
|
|
.ram(ram_out),
|
|
.pc(pc),
|
|
.dptr({dptr_hi, dptr_lo}),
|
|
.op1(op1_n),
|
|
.op2(op2_n),
|
|
.op3(op3_n),
|
|
|
|
.src1(src1),
|
|
.src2(src2),
|
|
.src3(src3));
|
|
|
|
|
//
|
//
|
//
|
//
|
oc8051_comp oc8051_comp1(.sel(comp_sel), .eq(eq), .b_in(bit_out), .cy(cy), .acc(acc), .des(des1_r));
|
oc8051_comp oc8051_comp1(.sel(comp_sel),
|
|
.eq(eq),
|
|
.b_in(bit_out),
|
|
.cy(cy),
|
|
.acc(acc),
|
|
.des(des1_r));
|
|
|
|
|
//
|
//
|
//program rom
|
//program rom
|
oc8051_rom oc8051_rom1(.rst(wb_rst_i), .clk(wb_clk_i), .ea_int(ea_int), .addr(iadr_o),
|
oc8051_rom oc8051_rom1(.rst(wb_rst_i),
|
.data1(op1_i), .data2(op2_i), .data3(op3_i));
|
.clk(wb_clk_i),
|
|
.ea_int(ea_int),
|
|
.addr(iadr_o),
|
|
.data1(op1_i),
|
|
.data2(op2_i),
|
|
.data3(op3_i));
|
|
|
//
|
//
|
//
|
//
|
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel), .cy_in(cy), .data_in(bit_out),
|
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),
|
|
.cy_in(cy),
|
|
.data_in(bit_out),
|
.data_out(alu_cy));
|
.data_out(alu_cy));
|
//
|
//
|
//
|
//
|
oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i), .rst(wb_rst_i), .rd_addr(rd_addr), .wr_addr(wr_addr),
|
oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i),
|
.data_in(wr_dat), .wr(wr_o), .wr_bit(bit_addr_o), .rn_out(rn_mem),
|
.rst(wb_rst_i),
|
.ri_out(ri), .sel(op1_cur), .bank(bank_sel));
|
.rd_addr(rd_addr),
|
|
.wr_addr(wr_addr),
|
|
.data_in(wr_dat),
|
|
.wr(wr_o),
|
|
.wr_bit(bit_addr_o),
|
|
.rn_out(rn_mem),
|
|
.ri_out(ri),
|
|
.sel(op1_cur),
|
|
.bank(bank_sel));
|
|
|
|
|
|
|
assign icyc_o = istb_o;
|
assign icyc_o = istb_o;
|
//
|
//
|
//
|
//
|
oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i), .rst(wb_rst_i),
|
oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i),
|
|
.rst(wb_rst_i),
|
// internal ram
|
// internal ram
|
.wr_i(wr), .wr_o(wr_o), .wr_bit_i(bit_addr), .wr_bit_o(bit_addr_o), .wr_dat(wr_dat),
|
.wr_i(wr),
|
.des1(des1), .des2(des2),
|
.wr_o(wr_o),
|
.rd_addr(rd_addr), .wr_addr(wr_addr),
|
.wr_bit_i(bit_addr),
|
|
.wr_bit_o(bit_addr_o),
|
|
.wr_dat(wr_dat),
|
|
.des1(des1),
|
|
.des2(des2),
|
|
.rd_addr(rd_addr),
|
|
.wr_addr(wr_addr),
|
.wr_ind(wr_ind),
|
.wr_ind(wr_ind),
|
.bit_in(bit_data), .in_ram(ram_data),
|
.bit_in(bit_data),
|
.sfr(sfr_out), .sfr_bit(sfr_bit), .bit_out(bit_out), .iram_out(ram_out),
|
.in_ram(ram_data),
|
|
.sfr(sfr_out),
|
|
.sfr_bit(sfr_bit),
|
|
.bit_out(bit_out),
|
|
.iram_out(ram_out),
|
|
|
// external instrauction rom
|
// external instrauction rom
|
.iack_i(iack_i),
|
.iack_i(iack_i),
|
.iadr_o(iadr_o),
|
.iadr_o(iadr_o),
|
.idat_i(idat_i),
|
.idat_i(idat_i),
|
.istb_o(istb_o),
|
.istb_o(istb_o),
|
|
|
// internal instruction rom
|
// internal instruction rom
|
.op1_i(op1_i), .op2_i(op2_i), .op3_i(op3_i),
|
.op1_i(op1_i),
|
|
.op2_i(op2_i),
|
|
.op3_i(op3_i),
|
|
|
// data memory
|
// data memory
|
.dadr_o(wbd_adr_o), .ddat_o(wbd_dat_o),
|
.dadr_o(wbd_adr_o),
|
.dwe_o(wbd_we_o), .dstb_o(wbd_stb_o),
|
.ddat_o(wbd_dat_o),
|
.ddat_i(wbd_dat_i), .dack_i(wbd_ack_i),
|
.dwe_o(wbd_we_o),
|
|
.dstb_o(wbd_stb_o),
|
|
.ddat_i(wbd_dat_i),
|
|
.dack_i(wbd_ack_i),
|
|
|
// from decoder
|
// from decoder
|
.rd_sel(ram_rd_sel), .wr_sel(ram_wr_sel), .rn({bank_sel, op1_n[2:0]}),
|
.rd_sel(ram_rd_sel),
|
.rd_ind(rd_ind), .rd(rd),
|
.wr_sel(ram_wr_sel),
|
.mem_act(mem_act), .mem_wait(mem_wait),
|
.rn({bank_sel, op1_n[2:0]}),
|
|
.rd_ind(rd_ind),
|
|
.rd(rd),
|
|
.mem_act(mem_act),
|
|
.mem_wait(mem_wait),
|
|
|
// external access
|
// external access
|
.ea(ea_in), .ea_int(ea_int),
|
.ea(ea_in),
|
|
.ea_int(ea_int),
|
|
|
// instructions outputs to cpu
|
// instructions outputs to cpu
|
.op1_out(op1_n), .op2_out(op2_n), .op3_out(op3_n),
|
.op1_out(op1_n),
|
|
.op2_out(op2_n),
|
|
.op3_out(op3_n),
|
|
|
// interrupt interface
|
// interrupt interface
|
.intr(intr), .int_v(int_src), .int_ack(int_ack), .istb(istb),
|
.intr(intr),
|
|
.int_v(int_src),
|
|
.int_ack(int_ack),
|
|
.istb(istb),
|
.reti(reti),
|
.reti(reti),
|
|
|
//pc
|
//pc
|
.pc_wr_sel(pc_wr_sel), .pc_wr(pc_wr), .pc(pc),
|
.pc_wr_sel(pc_wr_sel),
|
|
.pc_wr(pc_wr),
|
|
.pc(pc),
|
|
|
// sfr's
|
// sfr's
|
.sp_w(sp_w), .dptr({dptr_hi, dptr_lo}),
|
.sp_w(sp_w),
|
.ri(ri), .rn_mem(rn_mem),
|
.dptr({dptr_hi, dptr_lo}),
|
.acc(acc), .sp(sp)
|
.ri(ri),
|
|
.rn_mem(rn_mem),
|
|
.acc(acc),
|
|
.sp(sp)
|
);
|
);
|
|
|
|
|
//
|
//
|
//
|
//
|
|
|
oc8051_sfr oc8051_sfr1(.rst(wb_rst_i), .clk(wb_clk_i), .adr0(rd_addr[7:0]), .adr1(wr_addr[7:0]),
|
oc8051_sfr oc8051_sfr1(.rst(wb_rst_i),
|
.dat0(sfr_out), .dat1(wr_dat), .dat2(des2), .we(wr_o && !wr_ind), .bit_in(desCy),
|
.clk(wb_clk_i),
|
.bit_out(sfr_bit), .wr_bit(bit_addr_o), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
|
.adr0(rd_addr[7:0]),
|
|
.adr1(wr_addr[7:0]),
|
|
.dat0(sfr_out),
|
|
.dat1(wr_dat),
|
|
.dat2(des2),
|
|
.we(wr_o && !wr_ind),
|
|
.bit_in(desCy),
|
|
.bit_out(sfr_bit),
|
|
.wr_bit(bit_addr_o),
|
|
.ram_rd_sel(ram_rd_sel),
|
|
.ram_wr_sel(ram_wr_sel),
|
.wr_sfr(wr_sfr),
|
.wr_sfr(wr_sfr),
|
// acc
|
// acc
|
.acc(acc),
|
.acc(acc),
|
// sp
|
// sp
|
.sp(sp), .sp_w(sp_w),
|
.sp(sp),
|
|
.sp_w(sp_w),
|
// psw
|
// psw
|
.bank_sel(bank_sel), .desAc(desAc), .desOv(desOv), .psw_set(psw_set),
|
.bank_sel(bank_sel),
|
.srcAc(srcAc), .cy(cy),
|
.desAc(desAc),
|
|
.desOv(desOv),
|
|
.psw_set(psw_set),
|
|
.srcAc(srcAc),
|
|
.cy(cy),
|
// ports
|
// ports
|
.rmw(rmw), .p0_out(p0_o), .p1_out(p1_o), .p2_out(p2_o), .p3_out(p3_o),
|
.rmw(rmw),
|
.p0_in(p0_i), .p1_in(p1_i), .p2_in(p2_i), .p3_in(p3_i),
|
|
|
`ifdef OC8051_PORTS
|
|
`ifdef OC8051_PORT0
|
|
.p0_out(p0_o),
|
|
.p0_in(p0_i),
|
|
`endif
|
|
|
|
`ifdef OC8051_PORT1
|
|
.p1_out(p1_o),
|
|
.p1_in(p1_i),
|
|
`endif
|
|
|
|
`ifdef OC8051_PORT2
|
|
.p2_out(p2_o),
|
|
.p2_in(p2_i),
|
|
`endif
|
|
|
|
`ifdef OC8051_PORT3
|
|
.p3_out(p3_o),
|
|
.p3_in(p3_i),
|
|
`endif
|
|
`endif
|
|
|
// uart
|
// uart
|
|
`ifdef OC8051_UART
|
.rxd(rxd_i), .txd(txd_o),
|
.rxd(rxd_i), .txd(txd_o),
|
|
`endif
|
|
|
// int
|
// int
|
.int_ack(int_ack), .intr(intr), .int0(int0_i), .int1(int1_i),
|
.int_ack(int_ack),
|
.reti(reti), .int_src(int_src),
|
.intr(intr),
|
// t/c
|
.int0(int0_i),
|
.t0(t0_i), .t1(t1_i), .t2(t2_i), .t2ex(t2ex_i),
|
.int1(int1_i),
|
|
.reti(reti),
|
|
.int_src(int_src),
|
|
|
|
// t/c 0,1
|
|
`ifdef OC8051_TC01
|
|
.t0(t0_i),
|
|
.t1(t1_i),
|
|
`endif
|
|
|
|
// t/c 2
|
|
`ifdef OC8051_TC2
|
|
.t2(t2_i),
|
|
.t2ex(t2ex_i),
|
|
`endif
|
|
|
// dptr
|
// dptr
|
.dptr_hi(dptr_hi), .dptr_lo(dptr_lo),
|
.dptr_hi(dptr_hi),
|
.wait_data(wait_data));
|
.dptr_lo(dptr_lo),
|
|
.wait_data(wait_data)
|
|
);
|
|
|
|
|
|
|
|
|
`ifdef OC8051_CACHE
|
`ifdef OC8051_CACHE
|
