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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_top.v] - Diff between revs 141 and 144

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Rev 141 Rev 144
Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.28  2003/05/06 09:41:35  simont
 
// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
 
//
// Revision 1.27  2003/05/05 15:46:37  simont
// Revision 1.27  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
// add aditional alu destination to solve critical path.
//
//
// Revision 1.26  2003/04/29 11:24:31  simont
// Revision 1.26  2003/04/29 11:24:31  simont
// fix bug in case execution of two data dependent instructions.
// fix bug in case execution of two data dependent instructions.
Line 419... Line 422...
oc8051_comp oc8051_comp1(.sel(comp_sel),
oc8051_comp oc8051_comp1(.sel(comp_sel),
                         .eq(eq),
                         .eq(eq),
                         .b_in(bit_out),
                         .b_in(bit_out),
                         .cy(cy),
                         .cy(cy),
                         .acc(acc),
                         .acc(acc),
                         .des(des_acc)
                         .des(des1)
                         );
                         );
 
 
 
 
//
//
//program rom
//program rom

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